4 * Copyright (C) 2013 Texas Instruments Incorporated
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
11 #define DSS_SUBSYS_NAME "HDMIPLL"
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/clk.h>
19 #include <linux/seq_file.h>
20 #include <linux/pm_runtime.h>
26 void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s)
28 #define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\
29 hdmi_read_reg(pll->base, r))
31 DUMPPLL(PLLCTRL_PLL_CONTROL);
32 DUMPPLL(PLLCTRL_PLL_STATUS);
33 DUMPPLL(PLLCTRL_PLL_GO);
34 DUMPPLL(PLLCTRL_CFG1);
35 DUMPPLL(PLLCTRL_CFG2);
36 DUMPPLL(PLLCTRL_CFG3);
37 DUMPPLL(PLLCTRL_SSC_CFG1);
38 DUMPPLL(PLLCTRL_SSC_CFG2);
39 DUMPPLL(PLLCTRL_CFG4);
42 static int hdmi_pll_enable(struct dss_pll *dsspll)
44 struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll);
45 struct hdmi_wp_data *wp = pll->wp;
48 r = pm_runtime_get_sync(&pll->pdev->dev);
51 dss_ctrl_pll_enable(DSS_PLL_HDMI, true);
53 r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
60 static void hdmi_pll_disable(struct dss_pll *dsspll)
62 struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll);
63 struct hdmi_wp_data *wp = pll->wp;
66 hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF);
68 dss_ctrl_pll_enable(DSS_PLL_HDMI, false);
70 r = pm_runtime_put_sync(&pll->pdev->dev);
71 WARN_ON(r < 0 && r != -ENOSYS);
74 static const struct dss_pll_ops hdmi_pll_ops = {
75 .enable = hdmi_pll_enable,
76 .disable = hdmi_pll_disable,
77 .set_config = dss_pll_write_config_type_b,
80 static const struct dss_pll_hw dss_omap4_hdmi_pll_hw = {
81 .type = DSS_PLL_TYPE_B,
90 .clkdco_min = 500000000,
91 .clkdco_low = 1000000000,
92 .clkdco_max = 2000000000,
102 .has_selfreqdco = true,
105 static const struct dss_pll_hw dss_omap5_hdmi_pll_hw = {
106 .type = DSS_PLL_TYPE_B,
115 .clkdco_min = 750000000,
116 .clkdco_low = 1500000000,
117 .clkdco_max = 2500000000UL,
127 .has_selfreqdco = true,
131 static int hdmi_init_pll_data(struct platform_device *pdev,
132 struct hdmi_pll_data *hpll)
134 struct dss_pll *pll = &hpll->pll;
138 clk = devm_clk_get(&pdev->dev, "sys_clk");
140 DSSERR("can't get sys_clk\n");
145 pll->id = DSS_PLL_HDMI;
146 pll->base = hpll->base;
149 if (hpll->wp->version == 4)
150 pll->hw = &dss_omap4_hdmi_pll_hw;
152 pll->hw = &dss_omap5_hdmi_pll_hw;
154 pll->ops = &hdmi_pll_ops;
156 r = dss_pll_register(pll);
163 int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll,
164 struct hdmi_wp_data *wp)
167 struct resource *res;
172 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll");
173 pll->base = devm_ioremap_resource(&pdev->dev, res);
174 if (IS_ERR(pll->base))
175 return PTR_ERR(pll->base);
177 r = hdmi_init_pll_data(pdev, pll);
179 DSSERR("failed to init HDMI PLL\n");
186 void hdmi_pll_uninit(struct hdmi_pll_data *hpll)
188 struct dss_pll *pll = &hpll->pll;
190 dss_pll_unregister(pll);