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11 * The above copyright notice and this permission notice shall be included in
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20 * DEALINGS IN THE SOFTWARE.
25 #include <core/gpuobj.h>
28 * The BL header format used by GM20B's firmware is slightly different
29 * from the one of GM200. Fix the differences here.
31 struct gm20b_flcn_bl_desc {
37 u32 non_sec_code_size;
46 gm20b_secboot_prepare_blobs(struct gm200_secboot *gsb)
48 struct nvkm_subdev *subdev = &gsb->base.subdev;
52 ret = gm20x_secboot_prepare_blobs(gsb);
56 acr_size = gsb->acr_load_blob->size;
58 * On Tegra the WPR region is set by the bootloader. It is illegal for
59 * the HS blob to be larger than this region.
61 if (acr_size > gsb->wpr_size) {
62 nvkm_error(subdev, "WPR region too small for FW blob!\n");
63 nvkm_error(subdev, "required: %dB\n", acr_size);
64 nvkm_error(subdev, "WPR size: %dB\n", gsb->wpr_size);
72 * gm20b_secboot_fixup_bl_desc - adapt BL descriptor to format used by GM20B FW
74 * There is only a slight format difference (DMA addresses being 32-bits and
75 * 256B-aligned) to address.
78 gm20b_secboot_fixup_bl_desc(const struct gm200_flcn_bl_desc *desc, void *ret)
80 struct gm20b_flcn_bl_desc *gdesc = ret;
83 memcpy(gdesc->reserved, desc->reserved, sizeof(gdesc->reserved));
84 memcpy(gdesc->signature, desc->signature, sizeof(gdesc->signature));
85 gdesc->ctx_dma = desc->ctx_dma;
86 addr = desc->code_dma_base.hi;
88 addr |= desc->code_dma_base.lo;
89 gdesc->code_dma_base = lower_32_bits(addr >> 8);
90 gdesc->non_sec_code_off = desc->non_sec_code_off;
91 gdesc->non_sec_code_size = desc->non_sec_code_size;
92 gdesc->sec_code_off = desc->sec_code_off;
93 gdesc->sec_code_size = desc->sec_code_size;
94 gdesc->code_entry_point = desc->code_entry_point;
95 addr = desc->data_dma_base.hi;
97 addr |= desc->data_dma_base.lo;
98 gdesc->data_dma_base = lower_32_bits(addr >> 8);
99 gdesc->data_size = desc->data_size;
103 gm20b_secboot_fixup_hs_desc(struct gm200_secboot *gsb,
104 struct hsflcn_acr_desc *desc)
106 desc->ucode_blob_base = gsb->ls_blob->addr;
107 desc->ucode_blob_size = gsb->ls_blob->size;
109 desc->wpr_offset = 0;
112 static const struct gm200_secboot_func
113 gm20b_secboot_func = {
114 .bl_desc_size = sizeof(struct gm20b_flcn_bl_desc),
115 .fixup_bl_desc = gm20b_secboot_fixup_bl_desc,
116 .fixup_hs_desc = gm20b_secboot_fixup_hs_desc,
117 .prepare_blobs = gm20b_secboot_prepare_blobs,
121 #ifdef CONFIG_ARCH_TEGRA
122 #define TEGRA_MC_BASE 0x70019000
123 #define MC_SECURITY_CARVEOUT2_CFG0 0xc58
124 #define MC_SECURITY_CARVEOUT2_BOM_0 0xc5c
125 #define MC_SECURITY_CARVEOUT2_BOM_HI_0 0xc60
126 #define MC_SECURITY_CARVEOUT2_SIZE_128K 0xc64
127 #define TEGRA_MC_SECURITY_CARVEOUT_CFG_LOCKED (1 << 1)
129 * sb_tegra_read_wpr() - read the WPR registers on Tegra
131 * On dGPU, we can manage the WPR region ourselves, but on Tegra the WPR region
132 * is reserved from system memory by the bootloader and irreversibly locked.
133 * This function reads the address and size of the pre-configured WPR region.
136 gm20b_tegra_read_wpr(struct gm200_secboot *gsb)
138 struct nvkm_secboot *sb = &gsb->base;
142 mc = ioremap(TEGRA_MC_BASE, 0xd00);
144 nvkm_error(&sb->subdev, "Cannot map Tegra MC registers\n");
147 gsb->wpr_addr = ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_0) |
148 ((u64)ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_HI_0) << 32);
149 gsb->wpr_size = ioread32_native(mc + MC_SECURITY_CARVEOUT2_SIZE_128K)
151 cfg = ioread32_native(mc + MC_SECURITY_CARVEOUT2_CFG0);
154 /* Check that WPR settings are valid */
155 if (gsb->wpr_size == 0) {
156 nvkm_error(&sb->subdev, "WPR region is empty\n");
160 if (!(cfg & TEGRA_MC_SECURITY_CARVEOUT_CFG_LOCKED)) {
161 nvkm_error(&sb->subdev, "WPR region not locked\n");
169 gm20b_tegra_read_wpr(struct gm200_secboot *gsb)
171 nvkm_error(&gsb->base.subdev, "Tegra support not compiled in\n");
177 gm20b_secboot_init(struct nvkm_secboot *sb)
179 struct gm200_secboot *gsb = gm200_secboot(sb);
182 ret = gm20b_tegra_read_wpr(gsb);
186 return gm200_secboot_init(sb);
189 static const struct nvkm_secboot_func
191 .dtor = gm200_secboot_dtor,
192 .init = gm20b_secboot_init,
193 .reset = gm200_secboot_reset,
194 .start = gm200_secboot_start,
195 .managed_falcons = BIT(NVKM_SECBOOT_FALCON_FECS),
196 .boot_falcon = NVKM_SECBOOT_FALCON_PMU,
200 gm20b_secboot_new(struct nvkm_device *device, int index,
201 struct nvkm_secboot **psb)
204 struct gm200_secboot *gsb;
206 gsb = kzalloc(sizeof(*gsb), GFP_KERNEL);
213 ret = nvkm_secboot_ctor(&gm20b_secboot, device, index, &gsb->base);
217 gsb->func = &gm20b_secboot_func;