2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 * DEALINGS IN THE SOFTWARE.
27 #include <core/gpuobj.h>
28 #include <subdev/fb.h>
29 #include <engine/falcon.h>
30 #include <subdev/mc.h>
33 * gm200_secboot_run_blob() - run the given high-secure blob
37 gm200_secboot_run_blob(struct nvkm_secboot *sb, struct nvkm_gpuobj *blob,
38 struct nvkm_falcon *falcon)
40 struct gm200_secboot *gsb = gm200_secboot(sb);
41 struct nvkm_subdev *subdev = &gsb->base.subdev;
46 ret = nvkm_falcon_get(falcon, subdev);
50 /* Map the HS firmware so the HS bootloader can see it */
51 ret = nvkm_gpuobj_map(blob, gsb->vm, NV_MEM_ACCESS_RW, &vma);
53 nvkm_falcon_put(falcon, subdev);
57 /* Reset and set the falcon up */
58 ret = nvkm_falcon_reset(falcon);
61 nvkm_falcon_bind_context(falcon, gsb->inst);
63 /* Load the HS bootloader into the falcon's IMEM/DMEM */
64 ret = sb->acr->func->load(sb->acr, falcon, blob, vma.offset);
70 /* Disable interrupts as we will poll for the HALT bit */
71 nvkm_mc_intr_mask(sb->subdev.device, falcon->owner->index, false);
73 /* Set default error value in mailbox register */
74 nvkm_falcon_wr32(falcon, 0x040, 0xdeada5a5);
76 /* Start the HS bootloader */
77 nvkm_falcon_set_start_addr(falcon, start_address);
78 nvkm_falcon_start(falcon);
79 ret = nvkm_falcon_wait_for_halt(falcon, 100);
84 * The mailbox register contains the (positive) error code - return this
87 ret = nvkm_falcon_rd32(falcon, 0x040);
90 /* Reenable interrupts */
91 nvkm_mc_intr_mask(sb->subdev.device, falcon->owner->index, true);
93 /* We don't need the ACR firmware anymore */
94 nvkm_gpuobj_unmap(&vma);
95 nvkm_falcon_put(falcon, subdev);
101 gm200_secboot_oneinit(struct nvkm_secboot *sb)
103 struct gm200_secboot *gsb = gm200_secboot(sb);
104 struct nvkm_device *device = sb->subdev.device;
106 const u64 vm_area_len = 600 * 1024;
109 /* Allocate instance block and VM */
110 ret = nvkm_gpuobj_new(device, 0x1000, 0, true, NULL, &gsb->inst);
114 ret = nvkm_gpuobj_new(device, 0x8000, 0, true, NULL, &gsb->pgd);
118 ret = nvkm_vm_new(device, 0, vm_area_len, 0, NULL, &vm);
122 atomic_inc(&vm->engref[NVKM_SUBDEV_PMU]);
124 ret = nvkm_vm_ref(vm, &gsb->vm, gsb->pgd);
125 nvkm_vm_ref(NULL, &vm, NULL);
129 nvkm_kmap(gsb->inst);
130 nvkm_wo32(gsb->inst, 0x200, lower_32_bits(gsb->pgd->addr));
131 nvkm_wo32(gsb->inst, 0x204, upper_32_bits(gsb->pgd->addr));
132 nvkm_wo32(gsb->inst, 0x208, lower_32_bits(vm_area_len - 1));
133 nvkm_wo32(gsb->inst, 0x20c, upper_32_bits(vm_area_len - 1));
134 nvkm_done(gsb->inst);
136 if (sb->acr->func->oneinit) {
137 ret = sb->acr->func->oneinit(sb->acr, sb);
146 gm200_secboot_fini(struct nvkm_secboot *sb, bool suspend)
150 if (sb->acr->func->fini)
151 ret = sb->acr->func->fini(sb->acr, sb, suspend);
157 gm200_secboot_dtor(struct nvkm_secboot *sb)
159 struct gm200_secboot *gsb = gm200_secboot(sb);
161 sb->acr->func->dtor(sb->acr);
163 nvkm_vm_ref(NULL, &gsb->vm, gsb->pgd);
164 nvkm_gpuobj_del(&gsb->pgd);
165 nvkm_gpuobj_del(&gsb->inst);
171 static const struct nvkm_secboot_func
173 .dtor = gm200_secboot_dtor,
174 .oneinit = gm200_secboot_oneinit,
175 .fini = gm200_secboot_fini,
176 .run_blob = gm200_secboot_run_blob,
180 gm200_secboot_new(struct nvkm_device *device, int index,
181 struct nvkm_secboot **psb)
184 struct gm200_secboot *gsb;
185 struct nvkm_acr *acr;
187 acr = acr_r361_new(BIT(NVKM_SECBOOT_FALCON_FECS) |
188 BIT(NVKM_SECBOOT_FALCON_GPCCS));
192 gsb = kzalloc(sizeof(*gsb), GFP_KERNEL);
199 ret = nvkm_secboot_ctor(&gm200_secboot, acr, device, index, &gsb->base);