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26 static const struct nvkm_mc_map
28 { 0x04008000, NVKM_ENGINE_MSVLD },
29 { 0x01020000, NVKM_ENGINE_MSPDEC },
30 { 0x00802000, NVKM_ENGINE_CE0 },
31 { 0x00400002, NVKM_ENGINE_MSPPP },
32 { 0x00201000, NVKM_ENGINE_GR },
33 { 0x00000100, NVKM_ENGINE_FIFO },
37 static const struct nvkm_mc_map
39 { 0x04000000, NVKM_ENGINE_DISP },
40 { 0x00400000, NVKM_ENGINE_CE0 },
41 { 0x00020000, NVKM_ENGINE_MSPDEC },
42 { 0x00008000, NVKM_ENGINE_MSVLD },
43 { 0x00001000, NVKM_ENGINE_GR },
44 { 0x00000100, NVKM_ENGINE_FIFO },
45 { 0x00000001, NVKM_ENGINE_MSPPP },
46 { 0x00429101, NVKM_SUBDEV_FB },
47 { 0x10000000, NVKM_SUBDEV_BUS },
48 { 0x00200000, NVKM_SUBDEV_GPIO },
49 { 0x00200000, NVKM_SUBDEV_I2C },
50 { 0x00100000, NVKM_SUBDEV_TIMER },
51 { 0x00080000, NVKM_SUBDEV_THERM },
52 { 0x00040000, NVKM_SUBDEV_PMU },
57 gt215_mc_intr_mask(struct nvkm_mc *mc, u32 mask, u32 stat)
59 nvkm_mask(mc->subdev.device, 0x000640, mask, stat);
62 static const struct nvkm_mc_func
65 .intr = gt215_mc_intr,
66 .intr_unarm = nv04_mc_intr_unarm,
67 .intr_rearm = nv04_mc_intr_rearm,
68 .intr_mask = gt215_mc_intr_mask,
69 .intr_stat = nv04_mc_intr_stat,
70 .reset = gt215_mc_reset,
74 gt215_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc)
76 return nvkm_mc_new_(>215_mc, device, index, pmc);