2 * Copyright 2012 Nouveau Community
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Martin Peres
24 #include <subdev/bios.h>
25 #include <subdev/bios/bit.h>
26 #include <subdev/bios/perf.h>
27 #include <subdev/pci.h>
30 nvbios_perf_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr,
31 u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
33 struct bit_entry bit_P;
36 if (!bit_entry(bios, 'P', &bit_P)) {
37 if (bit_P.version <= 2) {
38 perf = nvbios_rd16(bios, bit_P.offset + 0);
40 *ver = nvbios_rd08(bios, perf + 0);
41 *hdr = nvbios_rd08(bios, perf + 1);
42 if (*ver >= 0x40 && *ver < 0x41) {
43 *cnt = nvbios_rd08(bios, perf + 5);
44 *len = nvbios_rd08(bios, perf + 2);
45 *snr = nvbios_rd08(bios, perf + 4);
46 *ssz = nvbios_rd08(bios, perf + 3);
49 if (*ver >= 0x20 && *ver < 0x40) {
50 *cnt = nvbios_rd08(bios, perf + 2);
51 *len = nvbios_rd08(bios, perf + 3);
52 *snr = nvbios_rd08(bios, perf + 4);
53 *ssz = nvbios_rd08(bios, perf + 5);
60 if (bios->bmp_offset) {
61 if (nvbios_rd08(bios, bios->bmp_offset + 6) >= 0x25) {
62 perf = nvbios_rd16(bios, bios->bmp_offset + 0x94);
64 *hdr = nvbios_rd08(bios, perf + 0);
65 *ver = nvbios_rd08(bios, perf + 1);
66 *cnt = nvbios_rd08(bios, perf + 2);
67 *len = nvbios_rd08(bios, perf + 3);
79 nvbios_perf_entry(struct nvkm_bios *bios, int idx,
80 u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
83 u16 perf = nvbios_perf_table(bios, ver, hdr, cnt, len, &snr, &ssz);
84 if (perf && idx < *cnt) {
85 perf = perf + *hdr + (idx * (*len + (snr * ssz)));
95 nvbios_perfEp(struct nvkm_bios *bios, int idx,
96 u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_perfE *info)
98 u16 perf = nvbios_perf_entry(bios, idx, ver, hdr, cnt, len);
99 memset(info, 0x00, sizeof(*info));
100 info->pstate = nvbios_rd08(bios, perf + 0x00);
101 switch (!!perf * *ver) {
105 info->core = nvbios_rd32(bios, perf + 0x01) * 10;
106 info->memory = nvbios_rd32(bios, perf + 0x05) * 20;
107 info->fanspeed = nvbios_rd08(bios, perf + 0x37);
109 info->voltage = nvbios_rd08(bios, perf + 0x38);
114 info->fanspeed = nvbios_rd08(bios, perf + 0x04);
115 info->voltage = nvbios_rd08(bios, perf + 0x05);
116 info->shader = nvbios_rd16(bios, perf + 0x06) * 1000;
117 info->core = info->shader + (signed char)
118 nvbios_rd08(bios, perf + 0x08) * 1000;
119 switch (bios->subdev.device->chipset) {
122 info->memory = nvbios_rd16(bios, perf + 0x0b) * 1000;
125 info->memory = nvbios_rd16(bios, perf + 0x0b) * 2000;
130 info->fanspeed = nvbios_rd08(bios, perf + 0x04);
131 info->voltage = nvbios_rd08(bios, perf + 0x05);
132 info->core = nvbios_rd16(bios, perf + 0x06) * 1000;
133 info->shader = nvbios_rd16(bios, perf + 0x0a) * 1000;
134 info->memory = nvbios_rd16(bios, perf + 0x0c) * 1000;
137 info->script = nvbios_rd16(bios, perf + 0x02);
139 info->fanspeed = nvbios_rd08(bios, perf + 0x06);
140 info->voltage = nvbios_rd08(bios, perf + 0x07);
141 info->core = nvbios_rd16(bios, perf + 0x08) * 1000;
142 info->shader = nvbios_rd16(bios, perf + 0x0a) * 1000;
143 info->memory = nvbios_rd16(bios, perf + 0x0c) * 1000;
144 info->vdec = nvbios_rd16(bios, perf + 0x10) * 1000;
145 info->disp = nvbios_rd16(bios, perf + 0x14) * 1000;
148 info->voltage = nvbios_rd08(bios, perf + 0x02);
149 switch (nvbios_rd08(bios, perf + 0xb) & 0x3) {
151 info->pcie_speed = NVKM_PCIE_SPEED_5_0;
155 info->pcie_speed = NVKM_PCIE_SPEED_2_5;
158 info->pcie_speed = NVKM_PCIE_SPEED_8_0;
163 info->pcie_width = 0xff;
172 nvbios_perfSe(struct nvkm_bios *bios, u32 perfE, int idx,
173 u8 *ver, u8 *hdr, u8 cnt, u8 len)
175 u32 data = 0x00000000;
177 data = perfE + *hdr + (idx * len);
184 nvbios_perfSp(struct nvkm_bios *bios, u32 perfE, int idx,
185 u8 *ver, u8 *hdr, u8 cnt, u8 len,
186 struct nvbios_perfS *info)
188 u32 data = nvbios_perfSe(bios, perfE, idx, ver, hdr, cnt, len);
189 memset(info, 0x00, sizeof(*info));
190 switch (!!data * *ver) {
192 info->v40.freq = (nvbios_rd16(bios, data + 0x00) & 0x3fff) * 1000;
201 nvbios_perf_fan_parse(struct nvkm_bios *bios,
202 struct nvbios_perf_fan *fan)
204 u8 ver, hdr, cnt, len, snr, ssz;
205 u16 perf = nvbios_perf_table(bios, &ver, &hdr, &cnt, &len, &snr, &ssz);
209 if (ver >= 0x20 && ver < 0x40 && hdr > 6)
210 fan->pwm_divisor = nvbios_rd16(bios, perf + 6);
212 fan->pwm_divisor = 0;