2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <core/gpuobj.h>
27 #include <core/option.h>
28 #include <subdev/fb.h>
29 #include <subdev/mmu.h>
31 static struct nvkm_vm *
32 gf100_bar_kmap(struct nvkm_bar *base)
34 return gf100_bar(base)->bar[0].vm;
38 gf100_bar_umap(struct nvkm_bar *base, u64 size, int type, struct nvkm_vma *vma)
40 struct gf100_bar *bar = gf100_bar(base);
41 return nvkm_vm_get(bar->bar[1].vm, size, type, NV_MEM_ACCESS_RW, vma);
45 gf100_bar_ctor_vm(struct gf100_bar *bar, struct gf100_bar_vm *bar_vm,
46 struct lock_class_key *key, int bar_nr)
48 struct nvkm_device *device = bar->base.subdev.device;
50 resource_size_t bar_len;
53 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0, false,
58 ret = nvkm_gpuobj_new(device, 0x8000, 0, false, NULL, &bar_vm->pgd);
62 bar_len = device->func->resource_size(device, bar_nr);
63 if (bar_nr == 3 && bar->bar2_halve)
66 ret = nvkm_vm_new(device, 0, bar_len, 0, key, &vm);
70 atomic_inc(&vm->engref[NVKM_SUBDEV_BAR]);
73 * Bootstrap page table lookup.
76 ret = nvkm_vm_boot(vm, bar_len);
78 nvkm_vm_ref(NULL, &vm, NULL);
83 ret = nvkm_vm_ref(vm, &bar_vm->vm, bar_vm->pgd);
84 nvkm_vm_ref(NULL, &vm, NULL);
88 nvkm_kmap(bar_vm->mem);
89 nvkm_wo32(bar_vm->mem, 0x0200, lower_32_bits(bar_vm->pgd->addr));
90 nvkm_wo32(bar_vm->mem, 0x0204, upper_32_bits(bar_vm->pgd->addr));
91 nvkm_wo32(bar_vm->mem, 0x0208, lower_32_bits(bar_len - 1));
92 nvkm_wo32(bar_vm->mem, 0x020c, upper_32_bits(bar_len - 1));
93 nvkm_done(bar_vm->mem);
98 gf100_bar_oneinit(struct nvkm_bar *base)
100 static struct lock_class_key bar1_lock;
101 static struct lock_class_key bar3_lock;
102 struct gf100_bar *bar = gf100_bar(base);
106 if (bar->base.func->kmap) {
107 ret = gf100_bar_ctor_vm(bar, &bar->bar[0], &bar3_lock, 3);
113 ret = gf100_bar_ctor_vm(bar, &bar->bar[1], &bar1_lock, 1);
121 gf100_bar_init(struct nvkm_bar *base)
123 struct gf100_bar *bar = gf100_bar(base);
124 struct nvkm_device *device = bar->base.subdev.device;
127 nvkm_mask(device, 0x000200, 0x00000100, 0x00000000);
128 nvkm_mask(device, 0x000200, 0x00000100, 0x00000100);
130 addr = nvkm_memory_addr(bar->bar[1].mem) >> 12;
131 nvkm_wr32(device, 0x001704, 0x80000000 | addr);
133 if (bar->bar[0].mem) {
134 addr = nvkm_memory_addr(bar->bar[0].mem) >> 12;
137 nvkm_wr32(device, 0x001714, 0x80000000 | addr);
144 gf100_bar_dtor(struct nvkm_bar *base)
146 struct gf100_bar *bar = gf100_bar(base);
148 nvkm_vm_ref(NULL, &bar->bar[1].vm, bar->bar[1].pgd);
149 nvkm_gpuobj_del(&bar->bar[1].pgd);
150 nvkm_memory_del(&bar->bar[1].mem);
152 if (bar->bar[0].vm) {
153 nvkm_memory_del(&bar->bar[0].vm->pgt[0].mem[0]);
154 nvkm_vm_ref(NULL, &bar->bar[0].vm, bar->bar[0].pgd);
156 nvkm_gpuobj_del(&bar->bar[0].pgd);
157 nvkm_memory_del(&bar->bar[0].mem);
162 gf100_bar_new_(const struct nvkm_bar_func *func, struct nvkm_device *device,
163 int index, struct nvkm_bar **pbar)
165 struct gf100_bar *bar;
166 if (!(bar = kzalloc(sizeof(*bar), GFP_KERNEL)))
168 nvkm_bar_ctor(func, device, index, &bar->base);
169 bar->bar2_halve = nvkm_boolopt(device->cfgopt, "NvBar2Halve", false);
174 static const struct nvkm_bar_func
176 .dtor = gf100_bar_dtor,
177 .oneinit = gf100_bar_oneinit,
178 .init = gf100_bar_init,
179 .kmap = gf100_bar_kmap,
180 .umap = gf100_bar_umap,
181 .flush = g84_bar_flush,
185 gf100_bar_new(struct nvkm_device *device, int index, struct nvkm_bar **pbar)
187 return gf100_bar_new_(&gf100_bar_func, device, index, pbar);