2 * Copyright 2007 Matthieu CASTET <castet.matthieu@free.fr>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragr) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
27 #include <core/client.h>
28 #include <core/gpuobj.h>
29 #include <engine/fifo.h>
30 #include <engine/fifo/chan.h>
31 #include <subdev/fb.h>
34 u32 pipe_0x0000[0x040/4];
35 u32 pipe_0x0040[0x010/4];
36 u32 pipe_0x0200[0x0c0/4];
37 u32 pipe_0x4400[0x080/4];
38 u32 pipe_0x6400[0x3b0/4];
39 u32 pipe_0x6800[0x2f0/4];
40 u32 pipe_0x6c00[0x030/4];
41 u32 pipe_0x7000[0x130/4];
42 u32 pipe_0x7400[0x0c0/4];
43 u32 pipe_0x7800[0x0c0/4];
46 static int nv10_gr_ctx_regs[] = {
47 NV10_PGRAPH_CTX_SWITCH(0),
48 NV10_PGRAPH_CTX_SWITCH(1),
49 NV10_PGRAPH_CTX_SWITCH(2),
50 NV10_PGRAPH_CTX_SWITCH(3),
51 NV10_PGRAPH_CTX_SWITCH(4),
52 NV10_PGRAPH_CTX_CACHE(0, 0),
53 NV10_PGRAPH_CTX_CACHE(0, 1),
54 NV10_PGRAPH_CTX_CACHE(0, 2),
55 NV10_PGRAPH_CTX_CACHE(0, 3),
56 NV10_PGRAPH_CTX_CACHE(0, 4),
57 NV10_PGRAPH_CTX_CACHE(1, 0),
58 NV10_PGRAPH_CTX_CACHE(1, 1),
59 NV10_PGRAPH_CTX_CACHE(1, 2),
60 NV10_PGRAPH_CTX_CACHE(1, 3),
61 NV10_PGRAPH_CTX_CACHE(1, 4),
62 NV10_PGRAPH_CTX_CACHE(2, 0),
63 NV10_PGRAPH_CTX_CACHE(2, 1),
64 NV10_PGRAPH_CTX_CACHE(2, 2),
65 NV10_PGRAPH_CTX_CACHE(2, 3),
66 NV10_PGRAPH_CTX_CACHE(2, 4),
67 NV10_PGRAPH_CTX_CACHE(3, 0),
68 NV10_PGRAPH_CTX_CACHE(3, 1),
69 NV10_PGRAPH_CTX_CACHE(3, 2),
70 NV10_PGRAPH_CTX_CACHE(3, 3),
71 NV10_PGRAPH_CTX_CACHE(3, 4),
72 NV10_PGRAPH_CTX_CACHE(4, 0),
73 NV10_PGRAPH_CTX_CACHE(4, 1),
74 NV10_PGRAPH_CTX_CACHE(4, 2),
75 NV10_PGRAPH_CTX_CACHE(4, 3),
76 NV10_PGRAPH_CTX_CACHE(4, 4),
77 NV10_PGRAPH_CTX_CACHE(5, 0),
78 NV10_PGRAPH_CTX_CACHE(5, 1),
79 NV10_PGRAPH_CTX_CACHE(5, 2),
80 NV10_PGRAPH_CTX_CACHE(5, 3),
81 NV10_PGRAPH_CTX_CACHE(5, 4),
82 NV10_PGRAPH_CTX_CACHE(6, 0),
83 NV10_PGRAPH_CTX_CACHE(6, 1),
84 NV10_PGRAPH_CTX_CACHE(6, 2),
85 NV10_PGRAPH_CTX_CACHE(6, 3),
86 NV10_PGRAPH_CTX_CACHE(6, 4),
87 NV10_PGRAPH_CTX_CACHE(7, 0),
88 NV10_PGRAPH_CTX_CACHE(7, 1),
89 NV10_PGRAPH_CTX_CACHE(7, 2),
90 NV10_PGRAPH_CTX_CACHE(7, 3),
91 NV10_PGRAPH_CTX_CACHE(7, 4),
93 NV04_PGRAPH_DMA_START_0,
94 NV04_PGRAPH_DMA_START_1,
95 NV04_PGRAPH_DMA_LENGTH,
97 NV10_PGRAPH_DMA_PITCH,
101 NV04_PGRAPH_BOFFSET1,
104 NV04_PGRAPH_BOFFSET2,
107 NV04_PGRAPH_BOFFSET3,
110 NV04_PGRAPH_BOFFSET4,
113 NV04_PGRAPH_BOFFSET5,
123 NV04_PGRAPH_BSWIZZLE2,
124 NV04_PGRAPH_BSWIZZLE5,
127 NV04_PGRAPH_PATT_COLOR0,
128 NV04_PGRAPH_PATT_COLOR1,
129 NV04_PGRAPH_PATT_COLORRAM, /* 64 values from 0x400900 to 0x4009fc */
193 NV04_PGRAPH_PATTERN, /* 2 values from 0x400808 to 0x40080c */
195 NV04_PGRAPH_PATTERN_SHAPE,
196 NV03_PGRAPH_MONO_COLOR0,
199 NV04_PGRAPH_BETA_AND,
200 NV04_PGRAPH_BETA_PREMULT,
216 NV10_PGRAPH_WINDOWCLIP_HORIZONTAL, /* 8 values from 0x400f00-0x400f1c */
217 NV10_PGRAPH_WINDOWCLIP_VERTICAL, /* 8 values from 0x400f20-0x400f3c */
234 NV10_PGRAPH_GLOBALSTATE0,
235 NV10_PGRAPH_GLOBALSTATE1,
236 NV04_PGRAPH_STORED_FMT,
237 NV04_PGRAPH_SOURCE_COLOR,
238 NV03_PGRAPH_ABS_X_RAM, /* 32 values from 0x400400 to 0x40047c */
239 NV03_PGRAPH_ABS_Y_RAM, /* 32 values from 0x400480 to 0x4004fc */
302 NV03_PGRAPH_ABS_UCLIP_XMIN,
303 NV03_PGRAPH_ABS_UCLIP_XMAX,
304 NV03_PGRAPH_ABS_UCLIP_YMIN,
305 NV03_PGRAPH_ABS_UCLIP_YMAX,
310 NV03_PGRAPH_ABS_UCLIPA_XMIN,
311 NV03_PGRAPH_ABS_UCLIPA_XMAX,
312 NV03_PGRAPH_ABS_UCLIPA_YMIN,
313 NV03_PGRAPH_ABS_UCLIPA_YMAX,
314 NV03_PGRAPH_ABS_ICLIP_XMAX,
315 NV03_PGRAPH_ABS_ICLIP_YMAX,
316 NV03_PGRAPH_XY_LOGIC_MISC0,
317 NV03_PGRAPH_XY_LOGIC_MISC1,
318 NV03_PGRAPH_XY_LOGIC_MISC2,
319 NV03_PGRAPH_XY_LOGIC_MISC3,
324 NV10_PGRAPH_COMBINER0_IN_ALPHA,
325 NV10_PGRAPH_COMBINER1_IN_ALPHA,
326 NV10_PGRAPH_COMBINER0_IN_RGB,
327 NV10_PGRAPH_COMBINER1_IN_RGB,
328 NV10_PGRAPH_COMBINER_COLOR0,
329 NV10_PGRAPH_COMBINER_COLOR1,
330 NV10_PGRAPH_COMBINER0_OUT_ALPHA,
331 NV10_PGRAPH_COMBINER1_OUT_ALPHA,
332 NV10_PGRAPH_COMBINER0_OUT_RGB,
333 NV10_PGRAPH_COMBINER1_OUT_RGB,
334 NV10_PGRAPH_COMBINER_FINAL0,
335 NV10_PGRAPH_COMBINER_FINAL1,
352 NV04_PGRAPH_PASSTHRU_0,
353 NV04_PGRAPH_PASSTHRU_1,
354 NV04_PGRAPH_PASSTHRU_2,
355 NV10_PGRAPH_DIMX_TEXTURE,
356 NV10_PGRAPH_WDIMX_TEXTURE,
357 NV10_PGRAPH_DVD_COLORFMT,
358 NV10_PGRAPH_SCALED_FORMAT,
359 NV04_PGRAPH_MISC24_0,
360 NV04_PGRAPH_MISC24_1,
361 NV04_PGRAPH_MISC24_2,
368 static int nv17_gr_ctx_regs[] = {
389 #define nv10_gr(p) container_of((p), struct nv10_gr, base)
393 struct nv10_gr_chan *chan[32];
397 #define nv10_gr_chan(p) container_of((p), struct nv10_gr_chan, object)
399 struct nv10_gr_chan {
400 struct nvkm_object object;
403 int nv10[ARRAY_SIZE(nv10_gr_ctx_regs)];
404 int nv17[ARRAY_SIZE(nv17_gr_ctx_regs)];
405 struct pipe_state pipe_state;
410 /*******************************************************************************
411 * Graphics object classes
412 ******************************************************************************/
414 #define PIPE_SAVE(gr, state, addr) \
417 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, addr); \
418 for (__i = 0; __i < ARRAY_SIZE(state); __i++) \
419 state[__i] = nvkm_rd32(device, NV10_PGRAPH_PIPE_DATA); \
422 #define PIPE_RESTORE(gr, state, addr) \
425 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, addr); \
426 for (__i = 0; __i < ARRAY_SIZE(state); __i++) \
427 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, state[__i]); \
431 nv17_gr_mthd_lma_window(struct nv10_gr_chan *chan, u32 mthd, u32 data)
433 struct nvkm_device *device = chan->object.engine->subdev.device;
434 struct nvkm_gr *gr = &chan->gr->base;
435 struct pipe_state *pipe = &chan->pipe_state;
436 u32 pipe_0x0040[1], pipe_0x64c0[8], pipe_0x6a80[3], pipe_0x6ab0[3];
437 u32 xfmode0, xfmode1;
440 chan->lma_window[(mthd - 0x1638) / 4] = data;
447 PIPE_SAVE(device, pipe_0x0040, 0x0040);
448 PIPE_SAVE(device, pipe->pipe_0x0200, 0x0200);
450 PIPE_RESTORE(device, chan->lma_window, 0x6790);
454 xfmode0 = nvkm_rd32(device, NV10_PGRAPH_XFMODE0);
455 xfmode1 = nvkm_rd32(device, NV10_PGRAPH_XFMODE1);
457 PIPE_SAVE(device, pipe->pipe_0x4400, 0x4400);
458 PIPE_SAVE(device, pipe_0x64c0, 0x64c0);
459 PIPE_SAVE(device, pipe_0x6ab0, 0x6ab0);
460 PIPE_SAVE(device, pipe_0x6a80, 0x6a80);
464 nvkm_wr32(device, NV10_PGRAPH_XFMODE0, 0x10000000);
465 nvkm_wr32(device, NV10_PGRAPH_XFMODE1, 0x00000000);
466 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0);
467 for (i = 0; i < 4; i++)
468 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x3f800000);
469 for (i = 0; i < 4; i++)
470 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000);
472 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0);
473 for (i = 0; i < 3; i++)
474 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x3f800000);
476 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80);
477 for (i = 0; i < 3; i++)
478 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000);
480 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040);
481 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000008);
483 PIPE_RESTORE(device, pipe->pipe_0x0200, 0x0200);
487 PIPE_RESTORE(device, pipe_0x0040, 0x0040);
489 nvkm_wr32(device, NV10_PGRAPH_XFMODE0, xfmode0);
490 nvkm_wr32(device, NV10_PGRAPH_XFMODE1, xfmode1);
492 PIPE_RESTORE(device, pipe_0x64c0, 0x64c0);
493 PIPE_RESTORE(device, pipe_0x6ab0, 0x6ab0);
494 PIPE_RESTORE(device, pipe_0x6a80, 0x6a80);
495 PIPE_RESTORE(device, pipe->pipe_0x4400, 0x4400);
497 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x000000c0);
498 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000);
504 nv17_gr_mthd_lma_enable(struct nv10_gr_chan *chan, u32 mthd, u32 data)
506 struct nvkm_device *device = chan->object.engine->subdev.device;
507 struct nvkm_gr *gr = &chan->gr->base;
511 nvkm_mask(device, NV10_PGRAPH_DEBUG_4, 0x00000100, 0x00000100);
512 nvkm_mask(device, 0x4006b0, 0x08000000, 0x08000000);
516 nv17_gr_mthd_celcius(struct nv10_gr_chan *chan, u32 mthd, u32 data)
518 void (*func)(struct nv10_gr_chan *, u32, u32);
520 case 0x1638 ... 0x1644:
521 func = nv17_gr_mthd_lma_window; break;
522 case 0x1658: func = nv17_gr_mthd_lma_enable; break;
526 func(chan, mthd, data);
531 nv10_gr_mthd(struct nv10_gr_chan *chan, u8 class, u32 mthd, u32 data)
533 bool (*func)(struct nv10_gr_chan *, u32, u32);
535 case 0x99: func = nv17_gr_mthd_celcius; break;
539 return func(chan, mthd, data);
542 /*******************************************************************************
544 ******************************************************************************/
546 static struct nv10_gr_chan *
547 nv10_gr_channel(struct nv10_gr *gr)
549 struct nvkm_device *device = gr->base.engine.subdev.device;
550 struct nv10_gr_chan *chan = NULL;
551 if (nvkm_rd32(device, 0x400144) & 0x00010000) {
552 int chid = nvkm_rd32(device, 0x400148) >> 24;
553 if (chid < ARRAY_SIZE(gr->chan))
554 chan = gr->chan[chid];
560 nv10_gr_save_pipe(struct nv10_gr_chan *chan)
562 struct nv10_gr *gr = chan->gr;
563 struct pipe_state *pipe = &chan->pipe_state;
564 struct nvkm_device *device = gr->base.engine.subdev.device;
566 PIPE_SAVE(gr, pipe->pipe_0x4400, 0x4400);
567 PIPE_SAVE(gr, pipe->pipe_0x0200, 0x0200);
568 PIPE_SAVE(gr, pipe->pipe_0x6400, 0x6400);
569 PIPE_SAVE(gr, pipe->pipe_0x6800, 0x6800);
570 PIPE_SAVE(gr, pipe->pipe_0x6c00, 0x6c00);
571 PIPE_SAVE(gr, pipe->pipe_0x7000, 0x7000);
572 PIPE_SAVE(gr, pipe->pipe_0x7400, 0x7400);
573 PIPE_SAVE(gr, pipe->pipe_0x7800, 0x7800);
574 PIPE_SAVE(gr, pipe->pipe_0x0040, 0x0040);
575 PIPE_SAVE(gr, pipe->pipe_0x0000, 0x0000);
579 nv10_gr_load_pipe(struct nv10_gr_chan *chan)
581 struct nv10_gr *gr = chan->gr;
582 struct pipe_state *pipe = &chan->pipe_state;
583 struct nvkm_device *device = gr->base.engine.subdev.device;
584 u32 xfmode0, xfmode1;
587 nv04_gr_idle(&gr->base);
588 /* XXX check haiku comments */
589 xfmode0 = nvkm_rd32(device, NV10_PGRAPH_XFMODE0);
590 xfmode1 = nvkm_rd32(device, NV10_PGRAPH_XFMODE1);
591 nvkm_wr32(device, NV10_PGRAPH_XFMODE0, 0x10000000);
592 nvkm_wr32(device, NV10_PGRAPH_XFMODE1, 0x00000000);
593 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0);
594 for (i = 0; i < 4; i++)
595 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x3f800000);
596 for (i = 0; i < 4; i++)
597 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000);
599 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0);
600 for (i = 0; i < 3; i++)
601 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x3f800000);
603 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80);
604 for (i = 0; i < 3; i++)
605 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000);
607 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040);
608 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000008);
611 PIPE_RESTORE(gr, pipe->pipe_0x0200, 0x0200);
612 nv04_gr_idle(&gr->base);
615 nvkm_wr32(device, NV10_PGRAPH_XFMODE0, xfmode0);
616 nvkm_wr32(device, NV10_PGRAPH_XFMODE1, xfmode1);
617 PIPE_RESTORE(gr, pipe->pipe_0x6400, 0x6400);
618 PIPE_RESTORE(gr, pipe->pipe_0x6800, 0x6800);
619 PIPE_RESTORE(gr, pipe->pipe_0x6c00, 0x6c00);
620 PIPE_RESTORE(gr, pipe->pipe_0x7000, 0x7000);
621 PIPE_RESTORE(gr, pipe->pipe_0x7400, 0x7400);
622 PIPE_RESTORE(gr, pipe->pipe_0x7800, 0x7800);
623 PIPE_RESTORE(gr, pipe->pipe_0x4400, 0x4400);
624 PIPE_RESTORE(gr, pipe->pipe_0x0000, 0x0000);
625 PIPE_RESTORE(gr, pipe->pipe_0x0040, 0x0040);
626 nv04_gr_idle(&gr->base);
630 nv10_gr_create_pipe(struct nv10_gr_chan *chan)
632 struct nv10_gr *gr = chan->gr;
633 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
634 struct pipe_state *pipe_state = &chan->pipe_state;
635 u32 *pipe_state_addr;
637 #define PIPE_INIT(addr) \
639 pipe_state_addr = pipe_state->pipe_##addr; \
641 #define PIPE_INIT_END(addr) \
643 u32 *__end_addr = pipe_state->pipe_##addr + \
644 ARRAY_SIZE(pipe_state->pipe_##addr); \
645 if (pipe_state_addr != __end_addr) \
646 nvkm_error(subdev, "incomplete pipe init for 0x%x : %p/%p\n", \
647 addr, pipe_state_addr, __end_addr); \
649 #define NV_WRITE_PIPE_INIT(value) *(pipe_state_addr++) = value
652 for (i = 0; i < 48; i++)
653 NV_WRITE_PIPE_INIT(0x00000000);
654 PIPE_INIT_END(0x0200);
657 for (i = 0; i < 211; i++)
658 NV_WRITE_PIPE_INIT(0x00000000);
659 NV_WRITE_PIPE_INIT(0x3f800000);
660 NV_WRITE_PIPE_INIT(0x40000000);
661 NV_WRITE_PIPE_INIT(0x40000000);
662 NV_WRITE_PIPE_INIT(0x40000000);
663 NV_WRITE_PIPE_INIT(0x40000000);
664 NV_WRITE_PIPE_INIT(0x00000000);
665 NV_WRITE_PIPE_INIT(0x00000000);
666 NV_WRITE_PIPE_INIT(0x3f800000);
667 NV_WRITE_PIPE_INIT(0x00000000);
668 NV_WRITE_PIPE_INIT(0x3f000000);
669 NV_WRITE_PIPE_INIT(0x3f000000);
670 NV_WRITE_PIPE_INIT(0x00000000);
671 NV_WRITE_PIPE_INIT(0x00000000);
672 NV_WRITE_PIPE_INIT(0x00000000);
673 NV_WRITE_PIPE_INIT(0x00000000);
674 NV_WRITE_PIPE_INIT(0x3f800000);
675 NV_WRITE_PIPE_INIT(0x00000000);
676 NV_WRITE_PIPE_INIT(0x00000000);
677 NV_WRITE_PIPE_INIT(0x00000000);
678 NV_WRITE_PIPE_INIT(0x00000000);
679 NV_WRITE_PIPE_INIT(0x00000000);
680 NV_WRITE_PIPE_INIT(0x3f800000);
681 NV_WRITE_PIPE_INIT(0x3f800000);
682 NV_WRITE_PIPE_INIT(0x3f800000);
683 NV_WRITE_PIPE_INIT(0x3f800000);
684 PIPE_INIT_END(0x6400);
687 for (i = 0; i < 162; i++)
688 NV_WRITE_PIPE_INIT(0x00000000);
689 NV_WRITE_PIPE_INIT(0x3f800000);
690 for (i = 0; i < 25; i++)
691 NV_WRITE_PIPE_INIT(0x00000000);
692 PIPE_INIT_END(0x6800);
695 NV_WRITE_PIPE_INIT(0x00000000);
696 NV_WRITE_PIPE_INIT(0x00000000);
697 NV_WRITE_PIPE_INIT(0x00000000);
698 NV_WRITE_PIPE_INIT(0x00000000);
699 NV_WRITE_PIPE_INIT(0xbf800000);
700 NV_WRITE_PIPE_INIT(0x00000000);
701 NV_WRITE_PIPE_INIT(0x00000000);
702 NV_WRITE_PIPE_INIT(0x00000000);
703 NV_WRITE_PIPE_INIT(0x00000000);
704 NV_WRITE_PIPE_INIT(0x00000000);
705 NV_WRITE_PIPE_INIT(0x00000000);
706 NV_WRITE_PIPE_INIT(0x00000000);
707 PIPE_INIT_END(0x6c00);
710 NV_WRITE_PIPE_INIT(0x00000000);
711 NV_WRITE_PIPE_INIT(0x00000000);
712 NV_WRITE_PIPE_INIT(0x00000000);
713 NV_WRITE_PIPE_INIT(0x00000000);
714 NV_WRITE_PIPE_INIT(0x00000000);
715 NV_WRITE_PIPE_INIT(0x00000000);
716 NV_WRITE_PIPE_INIT(0x00000000);
717 NV_WRITE_PIPE_INIT(0x00000000);
718 NV_WRITE_PIPE_INIT(0x00000000);
719 NV_WRITE_PIPE_INIT(0x00000000);
720 NV_WRITE_PIPE_INIT(0x00000000);
721 NV_WRITE_PIPE_INIT(0x00000000);
722 NV_WRITE_PIPE_INIT(0x7149f2ca);
723 NV_WRITE_PIPE_INIT(0x00000000);
724 NV_WRITE_PIPE_INIT(0x00000000);
725 NV_WRITE_PIPE_INIT(0x00000000);
726 NV_WRITE_PIPE_INIT(0x7149f2ca);
727 NV_WRITE_PIPE_INIT(0x00000000);
728 NV_WRITE_PIPE_INIT(0x00000000);
729 NV_WRITE_PIPE_INIT(0x00000000);
730 NV_WRITE_PIPE_INIT(0x7149f2ca);
731 NV_WRITE_PIPE_INIT(0x00000000);
732 NV_WRITE_PIPE_INIT(0x00000000);
733 NV_WRITE_PIPE_INIT(0x00000000);
734 NV_WRITE_PIPE_INIT(0x7149f2ca);
735 NV_WRITE_PIPE_INIT(0x00000000);
736 NV_WRITE_PIPE_INIT(0x00000000);
737 NV_WRITE_PIPE_INIT(0x00000000);
738 NV_WRITE_PIPE_INIT(0x7149f2ca);
739 NV_WRITE_PIPE_INIT(0x00000000);
740 NV_WRITE_PIPE_INIT(0x00000000);
741 NV_WRITE_PIPE_INIT(0x00000000);
742 NV_WRITE_PIPE_INIT(0x7149f2ca);
743 NV_WRITE_PIPE_INIT(0x00000000);
744 NV_WRITE_PIPE_INIT(0x00000000);
745 NV_WRITE_PIPE_INIT(0x00000000);
746 NV_WRITE_PIPE_INIT(0x7149f2ca);
747 NV_WRITE_PIPE_INIT(0x00000000);
748 NV_WRITE_PIPE_INIT(0x00000000);
749 NV_WRITE_PIPE_INIT(0x00000000);
750 NV_WRITE_PIPE_INIT(0x7149f2ca);
751 for (i = 0; i < 35; i++)
752 NV_WRITE_PIPE_INIT(0x00000000);
753 PIPE_INIT_END(0x7000);
756 for (i = 0; i < 48; i++)
757 NV_WRITE_PIPE_INIT(0x00000000);
758 PIPE_INIT_END(0x7400);
761 for (i = 0; i < 48; i++)
762 NV_WRITE_PIPE_INIT(0x00000000);
763 PIPE_INIT_END(0x7800);
766 for (i = 0; i < 32; i++)
767 NV_WRITE_PIPE_INIT(0x00000000);
768 PIPE_INIT_END(0x4400);
771 for (i = 0; i < 16; i++)
772 NV_WRITE_PIPE_INIT(0x00000000);
773 PIPE_INIT_END(0x0000);
776 for (i = 0; i < 4; i++)
777 NV_WRITE_PIPE_INIT(0x00000000);
778 PIPE_INIT_END(0x0040);
782 #undef NV_WRITE_PIPE_INIT
786 nv10_gr_ctx_regs_find_offset(struct nv10_gr *gr, int reg)
788 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
790 for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++) {
791 if (nv10_gr_ctx_regs[i] == reg)
794 nvkm_error(subdev, "unknown offset nv10_ctx_regs %d\n", reg);
799 nv17_gr_ctx_regs_find_offset(struct nv10_gr *gr, int reg)
801 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
803 for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++) {
804 if (nv17_gr_ctx_regs[i] == reg)
807 nvkm_error(subdev, "unknown offset nv17_ctx_regs %d\n", reg);
812 nv10_gr_load_dma_vtxbuf(struct nv10_gr_chan *chan, int chid, u32 inst)
814 struct nv10_gr *gr = chan->gr;
815 struct nvkm_device *device = gr->base.engine.subdev.device;
816 u32 st2, st2_dl, st2_dh, fifo_ptr, fifo[0x60/4];
817 u32 ctx_user, ctx_switch[5];
820 /* NV10TCL_DMA_VTXBUF (method 0x18c) modifies hidden state
821 * that cannot be restored via MMIO. Do it through the FIFO
825 /* Look for a celsius object */
826 for (i = 0; i < 8; i++) {
827 int class = nvkm_rd32(device, NV10_PGRAPH_CTX_CACHE(i, 0)) & 0xfff;
829 if (class == 0x56 || class == 0x96 || class == 0x99) {
835 if (subchan < 0 || !inst)
838 /* Save the current ctx object */
839 ctx_user = nvkm_rd32(device, NV10_PGRAPH_CTX_USER);
840 for (i = 0; i < 5; i++)
841 ctx_switch[i] = nvkm_rd32(device, NV10_PGRAPH_CTX_SWITCH(i));
843 /* Save the FIFO state */
844 st2 = nvkm_rd32(device, NV10_PGRAPH_FFINTFC_ST2);
845 st2_dl = nvkm_rd32(device, NV10_PGRAPH_FFINTFC_ST2_DL);
846 st2_dh = nvkm_rd32(device, NV10_PGRAPH_FFINTFC_ST2_DH);
847 fifo_ptr = nvkm_rd32(device, NV10_PGRAPH_FFINTFC_FIFO_PTR);
849 for (i = 0; i < ARRAY_SIZE(fifo); i++)
850 fifo[i] = nvkm_rd32(device, 0x4007a0 + 4 * i);
852 /* Switch to the celsius subchannel */
853 for (i = 0; i < 5; i++)
854 nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(i),
855 nvkm_rd32(device, NV10_PGRAPH_CTX_CACHE(subchan, i)));
856 nvkm_mask(device, NV10_PGRAPH_CTX_USER, 0xe000, subchan << 13);
858 /* Inject NV10TCL_DMA_VTXBUF */
859 nvkm_wr32(device, NV10_PGRAPH_FFINTFC_FIFO_PTR, 0);
860 nvkm_wr32(device, NV10_PGRAPH_FFINTFC_ST2,
861 0x2c000000 | chid << 20 | subchan << 16 | 0x18c);
862 nvkm_wr32(device, NV10_PGRAPH_FFINTFC_ST2_DL, inst);
863 nvkm_mask(device, NV10_PGRAPH_CTX_CONTROL, 0, 0x10000);
864 nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
865 nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
867 /* Restore the FIFO state */
868 for (i = 0; i < ARRAY_SIZE(fifo); i++)
869 nvkm_wr32(device, 0x4007a0 + 4 * i, fifo[i]);
871 nvkm_wr32(device, NV10_PGRAPH_FFINTFC_FIFO_PTR, fifo_ptr);
872 nvkm_wr32(device, NV10_PGRAPH_FFINTFC_ST2, st2);
873 nvkm_wr32(device, NV10_PGRAPH_FFINTFC_ST2_DL, st2_dl);
874 nvkm_wr32(device, NV10_PGRAPH_FFINTFC_ST2_DH, st2_dh);
876 /* Restore the current ctx object */
877 for (i = 0; i < 5; i++)
878 nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(i), ctx_switch[i]);
879 nvkm_wr32(device, NV10_PGRAPH_CTX_USER, ctx_user);
883 nv10_gr_load_context(struct nv10_gr_chan *chan, int chid)
885 struct nv10_gr *gr = chan->gr;
886 struct nvkm_device *device = gr->base.engine.subdev.device;
890 for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++)
891 nvkm_wr32(device, nv10_gr_ctx_regs[i], chan->nv10[i]);
893 if (device->card_type >= NV_11 && device->chipset >= 0x17) {
894 for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++)
895 nvkm_wr32(device, nv17_gr_ctx_regs[i], chan->nv17[i]);
898 nv10_gr_load_pipe(chan);
900 inst = nvkm_rd32(device, NV10_PGRAPH_GLOBALSTATE1) & 0xffff;
901 nv10_gr_load_dma_vtxbuf(chan, chid, inst);
903 nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
904 nvkm_mask(device, NV10_PGRAPH_CTX_USER, 0xff000000, chid << 24);
905 nvkm_mask(device, NV10_PGRAPH_FFINTFC_ST2, 0x30000000, 0x00000000);
910 nv10_gr_unload_context(struct nv10_gr_chan *chan)
912 struct nv10_gr *gr = chan->gr;
913 struct nvkm_device *device = gr->base.engine.subdev.device;
916 for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++)
917 chan->nv10[i] = nvkm_rd32(device, nv10_gr_ctx_regs[i]);
919 if (device->card_type >= NV_11 && device->chipset >= 0x17) {
920 for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++)
921 chan->nv17[i] = nvkm_rd32(device, nv17_gr_ctx_regs[i]);
924 nv10_gr_save_pipe(chan);
926 nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000000);
927 nvkm_mask(device, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000);
932 nv10_gr_context_switch(struct nv10_gr *gr)
934 struct nvkm_device *device = gr->base.engine.subdev.device;
935 struct nv10_gr_chan *prev = NULL;
936 struct nv10_gr_chan *next = NULL;
939 nv04_gr_idle(&gr->base);
941 /* If previous context is valid, we need to save it */
942 prev = nv10_gr_channel(gr);
944 nv10_gr_unload_context(prev);
946 /* load context for next channel */
947 chid = (nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f;
948 next = gr->chan[chid];
950 nv10_gr_load_context(next, chid);
954 nv10_gr_chan_fini(struct nvkm_object *object, bool suspend)
956 struct nv10_gr_chan *chan = nv10_gr_chan(object);
957 struct nv10_gr *gr = chan->gr;
958 struct nvkm_device *device = gr->base.engine.subdev.device;
961 spin_lock_irqsave(&gr->lock, flags);
962 nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
963 if (nv10_gr_channel(gr) == chan)
964 nv10_gr_unload_context(chan);
965 nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
966 spin_unlock_irqrestore(&gr->lock, flags);
971 nv10_gr_chan_dtor(struct nvkm_object *object)
973 struct nv10_gr_chan *chan = nv10_gr_chan(object);
974 struct nv10_gr *gr = chan->gr;
977 spin_lock_irqsave(&gr->lock, flags);
978 gr->chan[chan->chid] = NULL;
979 spin_unlock_irqrestore(&gr->lock, flags);
983 static const struct nvkm_object_func
985 .dtor = nv10_gr_chan_dtor,
986 .fini = nv10_gr_chan_fini,
989 #define NV_WRITE_CTX(reg, val) do { \
990 int offset = nv10_gr_ctx_regs_find_offset(gr, reg); \
992 chan->nv10[offset] = val; \
995 #define NV17_WRITE_CTX(reg, val) do { \
996 int offset = nv17_gr_ctx_regs_find_offset(gr, reg); \
998 chan->nv17[offset] = val; \
1002 nv10_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch,
1003 const struct nvkm_oclass *oclass, struct nvkm_object **pobject)
1005 struct nv10_gr *gr = nv10_gr(base);
1006 struct nv10_gr_chan *chan;
1007 struct nvkm_device *device = gr->base.engine.subdev.device;
1008 unsigned long flags;
1010 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
1012 nvkm_object_ctor(&nv10_gr_chan, oclass, &chan->object);
1014 chan->chid = fifoch->chid;
1015 *pobject = &chan->object;
1017 NV_WRITE_CTX(0x00400e88, 0x08000000);
1018 NV_WRITE_CTX(0x00400e9c, 0x4b7fffff);
1019 NV_WRITE_CTX(NV03_PGRAPH_XY_LOGIC_MISC0, 0x0001ffff);
1020 NV_WRITE_CTX(0x00400e10, 0x00001000);
1021 NV_WRITE_CTX(0x00400e14, 0x00001000);
1022 NV_WRITE_CTX(0x00400e30, 0x00080008);
1023 NV_WRITE_CTX(0x00400e34, 0x00080008);
1024 if (device->card_type >= NV_11 && device->chipset >= 0x17) {
1025 /* is it really needed ??? */
1026 NV17_WRITE_CTX(NV10_PGRAPH_DEBUG_4,
1027 nvkm_rd32(device, NV10_PGRAPH_DEBUG_4));
1028 NV17_WRITE_CTX(0x004006b0, nvkm_rd32(device, 0x004006b0));
1029 NV17_WRITE_CTX(0x00400eac, 0x0fff0000);
1030 NV17_WRITE_CTX(0x00400eb0, 0x0fff0000);
1031 NV17_WRITE_CTX(0x00400ec0, 0x00000080);
1032 NV17_WRITE_CTX(0x00400ed0, 0x00000080);
1034 NV_WRITE_CTX(NV10_PGRAPH_CTX_USER, chan->chid << 24);
1036 nv10_gr_create_pipe(chan);
1038 spin_lock_irqsave(&gr->lock, flags);
1039 gr->chan[chan->chid] = chan;
1040 spin_unlock_irqrestore(&gr->lock, flags);
1044 /*******************************************************************************
1045 * PGRAPH engine/subdev functions
1046 ******************************************************************************/
1049 nv10_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile)
1051 struct nv10_gr *gr = nv10_gr(base);
1052 struct nvkm_device *device = gr->base.engine.subdev.device;
1053 struct nvkm_fifo *fifo = device->fifo;
1054 unsigned long flags;
1056 nvkm_fifo_pause(fifo, &flags);
1057 nv04_gr_idle(&gr->base);
1059 nvkm_wr32(device, NV10_PGRAPH_TLIMIT(i), tile->limit);
1060 nvkm_wr32(device, NV10_PGRAPH_TSIZE(i), tile->pitch);
1061 nvkm_wr32(device, NV10_PGRAPH_TILE(i), tile->addr);
1063 nvkm_fifo_start(fifo, &flags);
1066 const struct nvkm_bitfield nv10_gr_intr_name[] = {
1067 { NV_PGRAPH_INTR_NOTIFY, "NOTIFY" },
1068 { NV_PGRAPH_INTR_ERROR, "ERROR" },
1072 const struct nvkm_bitfield nv10_gr_nstatus[] = {
1073 { NV10_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" },
1074 { NV10_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" },
1075 { NV10_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" },
1076 { NV10_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" },
1081 nv10_gr_intr(struct nvkm_gr *base)
1083 struct nv10_gr *gr = nv10_gr(base);
1084 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1085 struct nvkm_device *device = subdev->device;
1086 u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR);
1087 u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE);
1088 u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS);
1089 u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR);
1090 u32 chid = (addr & 0x01f00000) >> 20;
1091 u32 subc = (addr & 0x00070000) >> 16;
1092 u32 mthd = (addr & 0x00001ffc);
1093 u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA);
1094 u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff;
1096 char msg[128], src[128], sta[128];
1097 struct nv10_gr_chan *chan;
1098 unsigned long flags;
1100 spin_lock_irqsave(&gr->lock, flags);
1101 chan = gr->chan[chid];
1103 if (stat & NV_PGRAPH_INTR_ERROR) {
1104 if (chan && (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD)) {
1105 if (!nv10_gr_mthd(chan, class, mthd, data))
1106 show &= ~NV_PGRAPH_INTR_ERROR;
1110 if (stat & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
1111 nvkm_wr32(device, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
1112 stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
1113 show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
1114 nv10_gr_context_switch(gr);
1117 nvkm_wr32(device, NV03_PGRAPH_INTR, stat);
1118 nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001);
1121 nvkm_snprintbf(msg, sizeof(msg), nv10_gr_intr_name, show);
1122 nvkm_snprintbf(src, sizeof(src), nv04_gr_nsource, nsource);
1123 nvkm_snprintbf(sta, sizeof(sta), nv10_gr_nstatus, nstatus);
1124 nvkm_error(subdev, "intr %08x [%s] nsource %08x [%s] "
1125 "nstatus %08x [%s] ch %d [%s] subc %d "
1126 "class %04x mthd %04x data %08x\n",
1127 show, msg, nsource, src, nstatus, sta, chid,
1128 chan ? chan->object.client->name : "unknown",
1129 subc, class, mthd, data);
1132 spin_unlock_irqrestore(&gr->lock, flags);
1136 nv10_gr_init(struct nvkm_gr *base)
1138 struct nv10_gr *gr = nv10_gr(base);
1139 struct nvkm_device *device = gr->base.engine.subdev.device;
1141 nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF);
1142 nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
1144 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
1145 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000);
1146 nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x00118700);
1147 /* nvkm_wr32(device, NV04_PGRAPH_DEBUG_2, 0x24E00810); */ /* 0x25f92ad9 */
1148 nvkm_wr32(device, NV04_PGRAPH_DEBUG_2, 0x25f92ad9);
1149 nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0x55DE0830 | (1 << 29) | (1 << 31));
1151 if (device->card_type >= NV_11 && device->chipset >= 0x17) {
1152 nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x1f000000);
1153 nvkm_wr32(device, 0x400a10, 0x03ff3fb6);
1154 nvkm_wr32(device, 0x400838, 0x002f8684);
1155 nvkm_wr32(device, 0x40083c, 0x00115f3f);
1156 nvkm_wr32(device, 0x4006b0, 0x40000020);
1158 nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00000000);
1161 nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(0), 0x00000000);
1162 nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(1), 0x00000000);
1163 nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(2), 0x00000000);
1164 nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(3), 0x00000000);
1165 nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(4), 0x00000000);
1166 nvkm_wr32(device, NV10_PGRAPH_STATE, 0xFFFFFFFF);
1168 nvkm_mask(device, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000);
1169 nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
1170 nvkm_wr32(device, NV10_PGRAPH_FFINTFC_ST2, 0x08000000);
1175 nv10_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device,
1176 int index, struct nvkm_gr **pgr)
1180 if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL)))
1182 spin_lock_init(&gr->lock);
1185 return nvkm_gr_ctor(func, device, index, 0x00001000, true, &gr->base);
1188 static const struct nvkm_gr_func
1190 .init = nv10_gr_init,
1191 .intr = nv10_gr_intr,
1192 .tile = nv10_gr_tile,
1193 .chan_new = nv10_gr_chan_new,
1195 { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
1196 { -1, -1, 0x0019, &nv04_gr_object }, /* clip */
1197 { -1, -1, 0x0030, &nv04_gr_object }, /* null */
1198 { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
1199 { -1, -1, 0x0043, &nv04_gr_object }, /* rop */
1200 { -1, -1, 0x0044, &nv04_gr_object }, /* pattern */
1201 { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */
1202 { -1, -1, 0x0052, &nv04_gr_object }, /* swzsurf */
1203 { -1, -1, 0x005f, &nv04_gr_object }, /* blit */
1204 { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */
1205 { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */
1206 { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */
1207 { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */
1208 { -1, -1, 0x009f, &nv04_gr_object }, /* blit */
1209 { -1, -1, 0x0093, &nv04_gr_object }, /* surf3d */
1210 { -1, -1, 0x0094, &nv04_gr_object }, /* ttri */
1211 { -1, -1, 0x0095, &nv04_gr_object }, /* mtri */
1212 { -1, -1, 0x0056, &nv04_gr_object }, /* celcius */
1218 nv10_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
1220 return nv10_gr_new_(&nv10_gr, device, index, pgr);