2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include "changk104.h"
26 #include <core/client.h>
27 #include <core/gpuobj.h>
28 #include <subdev/fb.h>
29 #include <subdev/mmu.h>
30 #include <subdev/timer.h>
32 #include <nvif/class.h>
33 #include <nvif/cla06f.h>
34 #include <nvif/unpack.h>
37 gk104_fifo_gpfifo_kick(struct gk104_fifo_chan *chan)
39 struct gk104_fifo *fifo = chan->fifo;
40 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
41 struct nvkm_device *device = subdev->device;
42 struct nvkm_client *client = chan->base.object.client;
45 mutex_lock(&subdev->mutex);
46 nvkm_wr32(device, 0x002634, chan->base.chid);
47 if (nvkm_msec(device, 2000,
48 if (!(nvkm_rd32(device, 0x002634) & 0x00100000))
51 nvkm_error(subdev, "channel %d [%s] kick timeout\n",
52 chan->base.chid, client->name);
55 mutex_unlock(&subdev->mutex);
60 gk104_fifo_gpfifo_engine_addr(struct nvkm_engine *engine)
62 switch (engine->subdev.index) {
64 case NVKM_ENGINE_CE0 :
65 case NVKM_ENGINE_CE1 :
66 case NVKM_ENGINE_CE2 : return 0x0000;
67 case NVKM_ENGINE_GR : return 0x0210;
68 case NVKM_ENGINE_SEC : return 0x0220;
69 case NVKM_ENGINE_MSPDEC: return 0x0250;
70 case NVKM_ENGINE_MSPPP : return 0x0260;
71 case NVKM_ENGINE_MSVLD : return 0x0270;
72 case NVKM_ENGINE_VIC : return 0x0280;
73 case NVKM_ENGINE_MSENC : return 0x0290;
74 case NVKM_ENGINE_NVDEC : return 0x02100270;
75 case NVKM_ENGINE_NVENC0: return 0x02100290;
76 case NVKM_ENGINE_NVENC1: return 0x0210;
84 gk104_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base,
85 struct nvkm_engine *engine, bool suspend)
87 struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
88 struct nvkm_gpuobj *inst = chan->base.inst;
89 u32 offset = gk104_fifo_gpfifo_engine_addr(engine);
92 ret = gk104_fifo_gpfifo_kick(chan);
98 nvkm_wo32(inst, (offset & 0xffff) + 0x00, 0x00000000);
99 nvkm_wo32(inst, (offset & 0xffff) + 0x04, 0x00000000);
100 if ((offset >>= 16)) {
101 nvkm_wo32(inst, offset + 0x00, 0x00000000);
102 nvkm_wo32(inst, offset + 0x04, 0x00000000);
111 gk104_fifo_gpfifo_engine_init(struct nvkm_fifo_chan *base,
112 struct nvkm_engine *engine)
114 struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
115 struct nvkm_gpuobj *inst = chan->base.inst;
116 u32 offset = gk104_fifo_gpfifo_engine_addr(engine);
119 u64 addr = chan->engn[engine->subdev.index].vma.offset;
120 u32 datalo = lower_32_bits(addr) | 0x00000004;
121 u32 datahi = upper_32_bits(addr);
123 nvkm_wo32(inst, (offset & 0xffff) + 0x00, datalo);
124 nvkm_wo32(inst, (offset & 0xffff) + 0x04, datahi);
125 if ((offset >>= 16)) {
126 nvkm_wo32(inst, offset + 0x00, datalo);
127 nvkm_wo32(inst, offset + 0x04, datahi);
136 gk104_fifo_gpfifo_engine_dtor(struct nvkm_fifo_chan *base,
137 struct nvkm_engine *engine)
139 struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
140 nvkm_gpuobj_unmap(&chan->engn[engine->subdev.index].vma);
141 nvkm_gpuobj_del(&chan->engn[engine->subdev.index].inst);
145 gk104_fifo_gpfifo_engine_ctor(struct nvkm_fifo_chan *base,
146 struct nvkm_engine *engine,
147 struct nvkm_object *object)
149 struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
150 int engn = engine->subdev.index;
153 if (!gk104_fifo_gpfifo_engine_addr(engine))
156 ret = nvkm_object_bind(object, NULL, 0, &chan->engn[engn].inst);
160 return nvkm_gpuobj_map(chan->engn[engn].inst, chan->vm,
161 NV_MEM_ACCESS_RW, &chan->engn[engn].vma);
165 gk104_fifo_gpfifo_fini(struct nvkm_fifo_chan *base)
167 struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
168 struct gk104_fifo *fifo = chan->fifo;
169 struct nvkm_device *device = fifo->base.engine.subdev.device;
170 u32 coff = chan->base.chid * 8;
172 if (!list_empty(&chan->head)) {
173 gk104_fifo_runlist_remove(fifo, chan);
174 nvkm_mask(device, 0x800004 + coff, 0x00000800, 0x00000800);
175 gk104_fifo_gpfifo_kick(chan);
176 gk104_fifo_runlist_commit(fifo, chan->runl);
179 nvkm_wr32(device, 0x800000 + coff, 0x00000000);
183 gk104_fifo_gpfifo_init(struct nvkm_fifo_chan *base)
185 struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
186 struct gk104_fifo *fifo = chan->fifo;
187 struct nvkm_device *device = fifo->base.engine.subdev.device;
188 u32 addr = chan->base.inst->addr >> 12;
189 u32 coff = chan->base.chid * 8;
191 nvkm_mask(device, 0x800004 + coff, 0x000f0000, chan->runl << 16);
192 nvkm_wr32(device, 0x800000 + coff, 0x80000000 | addr);
194 if (list_empty(&chan->head) && !chan->killed) {
195 gk104_fifo_runlist_insert(fifo, chan);
196 nvkm_mask(device, 0x800004 + coff, 0x00000400, 0x00000400);
197 gk104_fifo_runlist_commit(fifo, chan->runl);
198 nvkm_mask(device, 0x800004 + coff, 0x00000400, 0x00000400);
203 gk104_fifo_gpfifo_dtor(struct nvkm_fifo_chan *base)
205 struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
206 nvkm_vm_ref(NULL, &chan->vm, chan->pgd);
207 nvkm_gpuobj_del(&chan->pgd);
211 static const struct nvkm_fifo_chan_func
212 gk104_fifo_gpfifo_func = {
213 .dtor = gk104_fifo_gpfifo_dtor,
214 .init = gk104_fifo_gpfifo_init,
215 .fini = gk104_fifo_gpfifo_fini,
216 .ntfy = g84_fifo_chan_ntfy,
217 .engine_ctor = gk104_fifo_gpfifo_engine_ctor,
218 .engine_dtor = gk104_fifo_gpfifo_engine_dtor,
219 .engine_init = gk104_fifo_gpfifo_engine_init,
220 .engine_fini = gk104_fifo_gpfifo_engine_fini,
223 struct gk104_fifo_chan_func {
229 gk104_fifo_gpfifo_new_(const struct gk104_fifo_chan_func *func,
230 struct gk104_fifo *fifo, u32 *engmask, u16 *chid,
231 u64 vm, u64 ioffset, u64 ilength,
232 const struct nvkm_oclass *oclass,
233 struct nvkm_object **pobject)
235 struct nvkm_device *device = fifo->base.engine.subdev.device;
236 struct gk104_fifo_chan *chan;
237 int runlist = -1, ret = -ENOSYS, i, j;
238 u32 engines = 0, present = 0;
242 /* Determine which downstream engines are present */
243 for (i = 0; i < fifo->engine_nr; i++) {
244 struct nvkm_engine *engine = fifo->engine[i].engine;
246 u64 submask = BIT_ULL(engine->subdev.index);
247 for (j = 0; func[j].subdev; j++) {
248 if (func[j].subdev & submask) {
249 present |= func[j].engine;
257 if (runlist < 0 && (*engmask & present))
258 runlist = fifo->engine[i].runl;
259 if (runlist == fifo->engine[i].runl) {
260 engines |= func[j].engine;
261 subdevs |= func[j].subdev;
266 /* Just an engine mask query? All done here! */
269 return nvkm_object_new(oclass, NULL, 0, pobject);
272 /* No runlist? No supported engines. */
278 /* Allocate the channel. */
279 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
281 *pobject = &chan->base.object;
283 chan->runl = runlist;
284 INIT_LIST_HEAD(&chan->head);
286 ret = nvkm_fifo_chan_ctor(&gk104_fifo_gpfifo_func, &fifo->base,
287 0x1000, 0x1000, true, vm, 0, subdevs,
288 1, fifo->user.bar.offset, 0x200,
289 oclass, &chan->base);
293 *chid = chan->base.chid;
295 /* Page directory. */
296 ret = nvkm_gpuobj_new(device, 0x10000, 0x1000, false, NULL, &chan->pgd);
300 nvkm_kmap(chan->base.inst);
301 nvkm_wo32(chan->base.inst, 0x0200, lower_32_bits(chan->pgd->addr));
302 nvkm_wo32(chan->base.inst, 0x0204, upper_32_bits(chan->pgd->addr));
303 nvkm_wo32(chan->base.inst, 0x0208, 0xffffffff);
304 nvkm_wo32(chan->base.inst, 0x020c, 0x000000ff);
305 nvkm_done(chan->base.inst);
307 ret = nvkm_vm_ref(chan->base.vm, &chan->vm, chan->pgd);
311 /* Clear channel control registers. */
312 usermem = chan->base.chid * 0x200;
313 ilength = order_base_2(ilength / 8);
315 nvkm_kmap(fifo->user.mem);
316 for (i = 0; i < 0x200; i += 4)
317 nvkm_wo32(fifo->user.mem, usermem + i, 0x00000000);
318 nvkm_done(fifo->user.mem);
319 usermem = nvkm_memory_addr(fifo->user.mem) + usermem;
322 nvkm_kmap(chan->base.inst);
323 nvkm_wo32(chan->base.inst, 0x08, lower_32_bits(usermem));
324 nvkm_wo32(chan->base.inst, 0x0c, upper_32_bits(usermem));
325 nvkm_wo32(chan->base.inst, 0x10, 0x0000face);
326 nvkm_wo32(chan->base.inst, 0x30, 0xfffff902);
327 nvkm_wo32(chan->base.inst, 0x48, lower_32_bits(ioffset));
328 nvkm_wo32(chan->base.inst, 0x4c, upper_32_bits(ioffset) |
330 nvkm_wo32(chan->base.inst, 0x84, 0x20400000);
331 nvkm_wo32(chan->base.inst, 0x94, 0x30000001);
332 nvkm_wo32(chan->base.inst, 0x9c, 0x00000100);
333 nvkm_wo32(chan->base.inst, 0xac, 0x0000001f);
334 nvkm_wo32(chan->base.inst, 0xe8, chan->base.chid);
335 nvkm_wo32(chan->base.inst, 0xb8, 0xf8000000);
336 nvkm_wo32(chan->base.inst, 0xf8, 0x10003080); /* 0x002310 */
337 nvkm_wo32(chan->base.inst, 0xfc, 0x10000010); /* 0x002350 */
338 nvkm_done(chan->base.inst);
342 static const struct gk104_fifo_chan_func
343 gk104_fifo_gpfifo[] = {
344 { NVA06F_V0_ENGINE_SW | NVA06F_V0_ENGINE_GR,
345 BIT_ULL(NVKM_ENGINE_SW) | BIT_ULL(NVKM_ENGINE_GR)
347 { NVA06F_V0_ENGINE_SEC , BIT_ULL(NVKM_ENGINE_SEC ) },
348 { NVA06F_V0_ENGINE_MSVLD , BIT_ULL(NVKM_ENGINE_MSVLD ) },
349 { NVA06F_V0_ENGINE_MSPDEC, BIT_ULL(NVKM_ENGINE_MSPDEC) },
350 { NVA06F_V0_ENGINE_MSPPP , BIT_ULL(NVKM_ENGINE_MSPPP ) },
351 { NVA06F_V0_ENGINE_MSENC , BIT_ULL(NVKM_ENGINE_MSENC ) },
352 { NVA06F_V0_ENGINE_VIC , BIT_ULL(NVKM_ENGINE_VIC ) },
353 { NVA06F_V0_ENGINE_NVDEC , BIT_ULL(NVKM_ENGINE_NVDEC ) },
354 { NVA06F_V0_ENGINE_NVENC0, BIT_ULL(NVKM_ENGINE_NVENC0) },
355 { NVA06F_V0_ENGINE_NVENC1, BIT_ULL(NVKM_ENGINE_NVENC1) },
356 { NVA06F_V0_ENGINE_CE0 , BIT_ULL(NVKM_ENGINE_CE0 ) },
357 { NVA06F_V0_ENGINE_CE1 , BIT_ULL(NVKM_ENGINE_CE1 ) },
358 { NVA06F_V0_ENGINE_CE2 , BIT_ULL(NVKM_ENGINE_CE2 ) },
363 gk104_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
364 void *data, u32 size, struct nvkm_object **pobject)
366 struct nvkm_object *parent = oclass->parent;
368 struct kepler_channel_gpfifo_a_v0 v0;
370 struct gk104_fifo *fifo = gk104_fifo(base);
373 nvif_ioctl(parent, "create channel gpfifo size %d\n", size);
374 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
375 nvif_ioctl(parent, "create channel gpfifo vers %d vm %llx "
376 "ioffset %016llx ilength %08x engine %08x\n",
377 args->v0.version, args->v0.vm, args->v0.ioffset,
378 args->v0.ilength, args->v0.engines);
379 return gk104_fifo_gpfifo_new_(gk104_fifo_gpfifo, fifo,
392 const struct nvkm_fifo_chan_oclass
393 gk104_fifo_gpfifo_oclass = {
394 .base.oclass = KEPLER_CHANNEL_GPFIFO_A,
397 .ctor = gk104_fifo_gpfifo_new,