2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include "changk104.h"
26 #include <core/client.h>
27 #include <core/gpuobj.h>
28 #include <subdev/fb.h>
29 #include <subdev/mmu.h>
30 #include <subdev/timer.h>
32 #include <nvif/class.h>
33 #include <nvif/cla06f.h>
34 #include <nvif/unpack.h>
37 gk104_fifo_gpfifo_kick(struct gk104_fifo_chan *chan)
39 struct gk104_fifo *fifo = chan->fifo;
40 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
41 struct nvkm_device *device = subdev->device;
42 struct nvkm_client *client = chan->base.object.client;
45 mutex_lock(&subdev->mutex);
46 nvkm_wr32(device, 0x002634, chan->base.chid);
47 if (nvkm_msec(device, 2000,
48 if (!(nvkm_rd32(device, 0x002634) & 0x00100000))
51 nvkm_error(subdev, "channel %d [%s] kick timeout\n",
52 chan->base.chid, client->name);
53 nvkm_fifo_recover_chan(&fifo->base, chan->base.chid);
56 mutex_unlock(&subdev->mutex);
61 gk104_fifo_gpfifo_engine_addr(struct nvkm_engine *engine)
63 switch (engine->subdev.index) {
65 case NVKM_ENGINE_CE0 :
66 case NVKM_ENGINE_CE1 :
67 case NVKM_ENGINE_CE2 : return 0x0000;
68 case NVKM_ENGINE_GR : return 0x0210;
69 case NVKM_ENGINE_SEC : return 0x0220;
70 case NVKM_ENGINE_MSPDEC: return 0x0250;
71 case NVKM_ENGINE_MSPPP : return 0x0260;
72 case NVKM_ENGINE_MSVLD : return 0x0270;
73 case NVKM_ENGINE_VIC : return 0x0280;
74 case NVKM_ENGINE_MSENC : return 0x0290;
75 case NVKM_ENGINE_NVDEC : return 0x02100270;
76 case NVKM_ENGINE_NVENC0: return 0x02100290;
77 case NVKM_ENGINE_NVENC1: return 0x0210;
85 gk104_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base,
86 struct nvkm_engine *engine, bool suspend)
88 struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
89 struct nvkm_gpuobj *inst = chan->base.inst;
90 u32 offset = gk104_fifo_gpfifo_engine_addr(engine);
93 ret = gk104_fifo_gpfifo_kick(chan);
99 nvkm_wo32(inst, (offset & 0xffff) + 0x00, 0x00000000);
100 nvkm_wo32(inst, (offset & 0xffff) + 0x04, 0x00000000);
101 if ((offset >>= 16)) {
102 nvkm_wo32(inst, offset + 0x00, 0x00000000);
103 nvkm_wo32(inst, offset + 0x04, 0x00000000);
112 gk104_fifo_gpfifo_engine_init(struct nvkm_fifo_chan *base,
113 struct nvkm_engine *engine)
115 struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
116 struct nvkm_gpuobj *inst = chan->base.inst;
117 u32 offset = gk104_fifo_gpfifo_engine_addr(engine);
120 u64 addr = chan->engn[engine->subdev.index].vma.offset;
121 u32 datalo = lower_32_bits(addr) | 0x00000004;
122 u32 datahi = upper_32_bits(addr);
124 nvkm_wo32(inst, (offset & 0xffff) + 0x00, datalo);
125 nvkm_wo32(inst, (offset & 0xffff) + 0x04, datahi);
126 if ((offset >>= 16)) {
127 nvkm_wo32(inst, offset + 0x00, datalo);
128 nvkm_wo32(inst, offset + 0x04, datahi);
137 gk104_fifo_gpfifo_engine_dtor(struct nvkm_fifo_chan *base,
138 struct nvkm_engine *engine)
140 struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
141 nvkm_gpuobj_unmap(&chan->engn[engine->subdev.index].vma);
142 nvkm_gpuobj_del(&chan->engn[engine->subdev.index].inst);
146 gk104_fifo_gpfifo_engine_ctor(struct nvkm_fifo_chan *base,
147 struct nvkm_engine *engine,
148 struct nvkm_object *object)
150 struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
151 int engn = engine->subdev.index;
154 if (!gk104_fifo_gpfifo_engine_addr(engine))
157 ret = nvkm_object_bind(object, NULL, 0, &chan->engn[engn].inst);
161 return nvkm_gpuobj_map(chan->engn[engn].inst, chan->vm,
162 NV_MEM_ACCESS_RW, &chan->engn[engn].vma);
166 gk104_fifo_gpfifo_fini(struct nvkm_fifo_chan *base)
168 struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
169 struct gk104_fifo *fifo = chan->fifo;
170 struct nvkm_device *device = fifo->base.engine.subdev.device;
171 u32 coff = chan->base.chid * 8;
173 if (!list_empty(&chan->head)) {
174 gk104_fifo_runlist_remove(fifo, chan);
175 nvkm_mask(device, 0x800004 + coff, 0x00000800, 0x00000800);
176 gk104_fifo_gpfifo_kick(chan);
177 gk104_fifo_runlist_commit(fifo, chan->runl);
180 nvkm_wr32(device, 0x800000 + coff, 0x00000000);
184 gk104_fifo_gpfifo_init(struct nvkm_fifo_chan *base)
186 struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
187 struct gk104_fifo *fifo = chan->fifo;
188 struct nvkm_device *device = fifo->base.engine.subdev.device;
189 u32 addr = chan->base.inst->addr >> 12;
190 u32 coff = chan->base.chid * 8;
192 nvkm_mask(device, 0x800004 + coff, 0x000f0000, chan->runl << 16);
193 nvkm_wr32(device, 0x800000 + coff, 0x80000000 | addr);
195 if (list_empty(&chan->head) && !chan->killed) {
196 gk104_fifo_runlist_insert(fifo, chan);
197 nvkm_mask(device, 0x800004 + coff, 0x00000400, 0x00000400);
198 gk104_fifo_runlist_commit(fifo, chan->runl);
199 nvkm_mask(device, 0x800004 + coff, 0x00000400, 0x00000400);
204 gk104_fifo_gpfifo_dtor(struct nvkm_fifo_chan *base)
206 struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
207 nvkm_vm_ref(NULL, &chan->vm, chan->pgd);
208 nvkm_gpuobj_del(&chan->pgd);
212 static const struct nvkm_fifo_chan_func
213 gk104_fifo_gpfifo_func = {
214 .dtor = gk104_fifo_gpfifo_dtor,
215 .init = gk104_fifo_gpfifo_init,
216 .fini = gk104_fifo_gpfifo_fini,
217 .ntfy = gf100_fifo_chan_ntfy,
218 .engine_ctor = gk104_fifo_gpfifo_engine_ctor,
219 .engine_dtor = gk104_fifo_gpfifo_engine_dtor,
220 .engine_init = gk104_fifo_gpfifo_engine_init,
221 .engine_fini = gk104_fifo_gpfifo_engine_fini,
224 struct gk104_fifo_chan_func {
230 gk104_fifo_gpfifo_new_(const struct gk104_fifo_chan_func *func,
231 struct gk104_fifo *fifo, u32 *engmask, u16 *chid,
232 u64 vm, u64 ioffset, u64 ilength,
233 const struct nvkm_oclass *oclass,
234 struct nvkm_object **pobject)
236 struct nvkm_device *device = fifo->base.engine.subdev.device;
237 struct gk104_fifo_chan *chan;
238 int runlist = -1, ret = -ENOSYS, i, j;
239 u32 engines = 0, present = 0;
243 /* Determine which downstream engines are present */
244 for (i = 0; i < fifo->engine_nr; i++) {
245 struct nvkm_engine *engine = fifo->engine[i].engine;
247 u64 submask = BIT_ULL(engine->subdev.index);
248 for (j = 0; func[j].subdev; j++) {
249 if (func[j].subdev & submask) {
250 present |= func[j].engine;
258 if (runlist < 0 && (*engmask & present))
259 runlist = fifo->engine[i].runl;
260 if (runlist == fifo->engine[i].runl) {
261 engines |= func[j].engine;
262 subdevs |= func[j].subdev;
267 /* Just an engine mask query? All done here! */
270 return nvkm_object_new(oclass, NULL, 0, pobject);
273 /* No runlist? No supported engines. */
279 /* Allocate the channel. */
280 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
282 *pobject = &chan->base.object;
284 chan->runl = runlist;
285 INIT_LIST_HEAD(&chan->head);
287 ret = nvkm_fifo_chan_ctor(&gk104_fifo_gpfifo_func, &fifo->base,
288 0x1000, 0x1000, true, vm, 0, subdevs,
289 1, fifo->user.bar.offset, 0x200,
290 oclass, &chan->base);
294 *chid = chan->base.chid;
296 /* Page directory. */
297 ret = nvkm_gpuobj_new(device, 0x10000, 0x1000, false, NULL, &chan->pgd);
301 nvkm_kmap(chan->base.inst);
302 nvkm_wo32(chan->base.inst, 0x0200, lower_32_bits(chan->pgd->addr));
303 nvkm_wo32(chan->base.inst, 0x0204, upper_32_bits(chan->pgd->addr));
304 nvkm_wo32(chan->base.inst, 0x0208, 0xffffffff);
305 nvkm_wo32(chan->base.inst, 0x020c, 0x000000ff);
306 nvkm_done(chan->base.inst);
308 ret = nvkm_vm_ref(chan->base.vm, &chan->vm, chan->pgd);
312 /* Clear channel control registers. */
313 usermem = chan->base.chid * 0x200;
314 ilength = order_base_2(ilength / 8);
316 nvkm_kmap(fifo->user.mem);
317 for (i = 0; i < 0x200; i += 4)
318 nvkm_wo32(fifo->user.mem, usermem + i, 0x00000000);
319 nvkm_done(fifo->user.mem);
320 usermem = nvkm_memory_addr(fifo->user.mem) + usermem;
323 nvkm_kmap(chan->base.inst);
324 nvkm_wo32(chan->base.inst, 0x08, lower_32_bits(usermem));
325 nvkm_wo32(chan->base.inst, 0x0c, upper_32_bits(usermem));
326 nvkm_wo32(chan->base.inst, 0x10, 0x0000face);
327 nvkm_wo32(chan->base.inst, 0x30, 0xfffff902);
328 nvkm_wo32(chan->base.inst, 0x48, lower_32_bits(ioffset));
329 nvkm_wo32(chan->base.inst, 0x4c, upper_32_bits(ioffset) |
331 nvkm_wo32(chan->base.inst, 0x84, 0x20400000);
332 nvkm_wo32(chan->base.inst, 0x94, 0x30000001);
333 nvkm_wo32(chan->base.inst, 0x9c, 0x00000100);
334 nvkm_wo32(chan->base.inst, 0xac, 0x0000001f);
335 nvkm_wo32(chan->base.inst, 0xe8, chan->base.chid);
336 nvkm_wo32(chan->base.inst, 0xb8, 0xf8000000);
337 nvkm_wo32(chan->base.inst, 0xf8, 0x10003080); /* 0x002310 */
338 nvkm_wo32(chan->base.inst, 0xfc, 0x10000010); /* 0x002350 */
339 nvkm_done(chan->base.inst);
343 static const struct gk104_fifo_chan_func
344 gk104_fifo_gpfifo[] = {
345 { NVA06F_V0_ENGINE_SW | NVA06F_V0_ENGINE_GR,
346 BIT_ULL(NVKM_ENGINE_SW) | BIT_ULL(NVKM_ENGINE_GR)
348 { NVA06F_V0_ENGINE_SEC , BIT_ULL(NVKM_ENGINE_SEC ) },
349 { NVA06F_V0_ENGINE_MSVLD , BIT_ULL(NVKM_ENGINE_MSVLD ) },
350 { NVA06F_V0_ENGINE_MSPDEC, BIT_ULL(NVKM_ENGINE_MSPDEC) },
351 { NVA06F_V0_ENGINE_MSPPP , BIT_ULL(NVKM_ENGINE_MSPPP ) },
352 { NVA06F_V0_ENGINE_MSENC , BIT_ULL(NVKM_ENGINE_MSENC ) },
353 { NVA06F_V0_ENGINE_VIC , BIT_ULL(NVKM_ENGINE_VIC ) },
354 { NVA06F_V0_ENGINE_NVDEC , BIT_ULL(NVKM_ENGINE_NVDEC ) },
355 { NVA06F_V0_ENGINE_NVENC0, BIT_ULL(NVKM_ENGINE_NVENC0) },
356 { NVA06F_V0_ENGINE_NVENC1, BIT_ULL(NVKM_ENGINE_NVENC1) },
357 { NVA06F_V0_ENGINE_CE0 , BIT_ULL(NVKM_ENGINE_CE0 ) },
358 { NVA06F_V0_ENGINE_CE1 , BIT_ULL(NVKM_ENGINE_CE1 ) },
359 { NVA06F_V0_ENGINE_CE2 , BIT_ULL(NVKM_ENGINE_CE2 ) },
364 gk104_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
365 void *data, u32 size, struct nvkm_object **pobject)
367 struct nvkm_object *parent = oclass->parent;
369 struct kepler_channel_gpfifo_a_v0 v0;
371 struct gk104_fifo *fifo = gk104_fifo(base);
374 nvif_ioctl(parent, "create channel gpfifo size %d\n", size);
375 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
376 nvif_ioctl(parent, "create channel gpfifo vers %d vm %llx "
377 "ioffset %016llx ilength %08x engine %08x\n",
378 args->v0.version, args->v0.vm, args->v0.ioffset,
379 args->v0.ilength, args->v0.engines);
380 return gk104_fifo_gpfifo_new_(gk104_fifo_gpfifo, fifo,
393 const struct nvkm_fifo_chan_oclass
394 gk104_fifo_gpfifo_oclass = {
395 .base.oclass = KEPLER_CHANNEL_GPFIFO_A,
398 .ctor = gk104_fifo_gpfifo_new,