2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include "changf100.h"
26 #include <core/client.h>
27 #include <core/gpuobj.h>
28 #include <subdev/fb.h>
29 #include <subdev/timer.h>
31 #include <nvif/class.h>
32 #include <nvif/cl906f.h>
33 #include <nvif/unpack.h>
36 gf100_fifo_chan_ntfy(struct nvkm_fifo_chan *chan, u32 type,
37 struct nvkm_event **pevent)
40 case NV906F_V0_NTFY_NON_STALL_INTERRUPT:
41 *pevent = &chan->fifo->uevent;
43 case NV906F_V0_NTFY_KILLED:
44 *pevent = &chan->fifo->kevent;
53 gf100_fifo_gpfifo_engine_addr(struct nvkm_engine *engine)
55 switch (engine->subdev.index) {
56 case NVKM_ENGINE_SW : return 0;
57 case NVKM_ENGINE_GR : return 0x0210;
58 case NVKM_ENGINE_CE0 : return 0x0230;
59 case NVKM_ENGINE_CE1 : return 0x0240;
60 case NVKM_ENGINE_MSPDEC: return 0x0250;
61 case NVKM_ENGINE_MSPPP : return 0x0260;
62 case NVKM_ENGINE_MSVLD : return 0x0270;
70 gf100_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base,
71 struct nvkm_engine *engine, bool suspend)
73 const u32 offset = gf100_fifo_gpfifo_engine_addr(engine);
74 struct gf100_fifo_chan *chan = gf100_fifo_chan(base);
75 struct nvkm_subdev *subdev = &chan->fifo->base.engine.subdev;
76 struct nvkm_device *device = subdev->device;
77 struct nvkm_gpuobj *inst = chan->base.inst;
80 mutex_lock(&subdev->mutex);
81 nvkm_wr32(device, 0x002634, chan->base.chid);
82 if (nvkm_msec(device, 2000,
83 if (nvkm_rd32(device, 0x002634) == chan->base.chid)
86 nvkm_error(subdev, "channel %d [%s] kick timeout\n",
87 chan->base.chid, chan->base.object.client->name);
90 mutex_unlock(&subdev->mutex);
97 nvkm_wo32(inst, offset + 0x00, 0x00000000);
98 nvkm_wo32(inst, offset + 0x04, 0x00000000);
106 gf100_fifo_gpfifo_engine_init(struct nvkm_fifo_chan *base,
107 struct nvkm_engine *engine)
109 const u32 offset = gf100_fifo_gpfifo_engine_addr(engine);
110 struct gf100_fifo_chan *chan = gf100_fifo_chan(base);
111 struct nvkm_gpuobj *inst = chan->base.inst;
114 u64 addr = chan->engn[engine->subdev.index].vma.offset;
116 nvkm_wo32(inst, offset + 0x00, lower_32_bits(addr) | 4);
117 nvkm_wo32(inst, offset + 0x04, upper_32_bits(addr));
125 gf100_fifo_gpfifo_engine_dtor(struct nvkm_fifo_chan *base,
126 struct nvkm_engine *engine)
128 struct gf100_fifo_chan *chan = gf100_fifo_chan(base);
129 nvkm_gpuobj_unmap(&chan->engn[engine->subdev.index].vma);
130 nvkm_gpuobj_del(&chan->engn[engine->subdev.index].inst);
134 gf100_fifo_gpfifo_engine_ctor(struct nvkm_fifo_chan *base,
135 struct nvkm_engine *engine,
136 struct nvkm_object *object)
138 struct gf100_fifo_chan *chan = gf100_fifo_chan(base);
139 int engn = engine->subdev.index;
142 if (!gf100_fifo_gpfifo_engine_addr(engine))
145 ret = nvkm_object_bind(object, NULL, 0, &chan->engn[engn].inst);
149 return nvkm_gpuobj_map(chan->engn[engn].inst, chan->vm,
150 NV_MEM_ACCESS_RW, &chan->engn[engn].vma);
154 gf100_fifo_gpfifo_fini(struct nvkm_fifo_chan *base)
156 struct gf100_fifo_chan *chan = gf100_fifo_chan(base);
157 struct gf100_fifo *fifo = chan->fifo;
158 struct nvkm_device *device = fifo->base.engine.subdev.device;
159 u32 coff = chan->base.chid * 8;
161 if (!list_empty(&chan->head) && !chan->killed) {
162 gf100_fifo_runlist_remove(fifo, chan);
163 nvkm_mask(device, 0x003004 + coff, 0x00000001, 0x00000000);
164 gf100_fifo_runlist_commit(fifo);
167 gf100_fifo_intr_engine(fifo);
169 nvkm_wr32(device, 0x003000 + coff, 0x00000000);
173 gf100_fifo_gpfifo_init(struct nvkm_fifo_chan *base)
175 struct gf100_fifo_chan *chan = gf100_fifo_chan(base);
176 struct gf100_fifo *fifo = chan->fifo;
177 struct nvkm_device *device = fifo->base.engine.subdev.device;
178 u32 addr = chan->base.inst->addr >> 12;
179 u32 coff = chan->base.chid * 8;
181 nvkm_wr32(device, 0x003000 + coff, 0xc0000000 | addr);
183 if (list_empty(&chan->head) && !chan->killed) {
184 gf100_fifo_runlist_insert(fifo, chan);
185 nvkm_wr32(device, 0x003004 + coff, 0x001f0001);
186 gf100_fifo_runlist_commit(fifo);
191 gf100_fifo_gpfifo_dtor(struct nvkm_fifo_chan *base)
193 struct gf100_fifo_chan *chan = gf100_fifo_chan(base);
194 nvkm_vm_ref(NULL, &chan->vm, chan->pgd);
195 nvkm_gpuobj_del(&chan->pgd);
199 static const struct nvkm_fifo_chan_func
200 gf100_fifo_gpfifo_func = {
201 .dtor = gf100_fifo_gpfifo_dtor,
202 .init = gf100_fifo_gpfifo_init,
203 .fini = gf100_fifo_gpfifo_fini,
204 .ntfy = gf100_fifo_chan_ntfy,
205 .engine_ctor = gf100_fifo_gpfifo_engine_ctor,
206 .engine_dtor = gf100_fifo_gpfifo_engine_dtor,
207 .engine_init = gf100_fifo_gpfifo_engine_init,
208 .engine_fini = gf100_fifo_gpfifo_engine_fini,
212 gf100_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
213 void *data, u32 size, struct nvkm_object **pobject)
216 struct fermi_channel_gpfifo_v0 v0;
218 struct gf100_fifo *fifo = gf100_fifo(base);
219 struct nvkm_device *device = fifo->base.engine.subdev.device;
220 struct nvkm_object *parent = oclass->parent;
221 struct gf100_fifo_chan *chan;
222 u64 usermem, ioffset, ilength;
223 int ret = -ENOSYS, i;
225 nvif_ioctl(parent, "create channel gpfifo size %d\n", size);
226 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
227 nvif_ioctl(parent, "create channel gpfifo vers %d vm %llx "
228 "ioffset %016llx ilength %08x\n",
229 args->v0.version, args->v0.vm, args->v0.ioffset,
234 /* allocate channel */
235 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
237 *pobject = &chan->base.object;
239 INIT_LIST_HEAD(&chan->head);
241 ret = nvkm_fifo_chan_ctor(&gf100_fifo_gpfifo_func, &fifo->base,
242 0x1000, 0x1000, true, args->v0.vm, 0,
243 (1ULL << NVKM_ENGINE_CE0) |
244 (1ULL << NVKM_ENGINE_CE1) |
245 (1ULL << NVKM_ENGINE_GR) |
246 (1ULL << NVKM_ENGINE_MSPDEC) |
247 (1ULL << NVKM_ENGINE_MSPPP) |
248 (1ULL << NVKM_ENGINE_MSVLD) |
249 (1ULL << NVKM_ENGINE_SW),
250 1, fifo->user.bar.offset, 0x1000,
251 oclass, &chan->base);
255 args->v0.chid = chan->base.chid;
258 ret = nvkm_gpuobj_new(device, 0x10000, 0x1000, false, NULL, &chan->pgd);
262 nvkm_kmap(chan->base.inst);
263 nvkm_wo32(chan->base.inst, 0x0200, lower_32_bits(chan->pgd->addr));
264 nvkm_wo32(chan->base.inst, 0x0204, upper_32_bits(chan->pgd->addr));
265 nvkm_wo32(chan->base.inst, 0x0208, 0xffffffff);
266 nvkm_wo32(chan->base.inst, 0x020c, 0x000000ff);
267 nvkm_done(chan->base.inst);
269 ret = nvkm_vm_ref(chan->base.vm, &chan->vm, chan->pgd);
273 /* clear channel control registers */
275 usermem = chan->base.chid * 0x1000;
276 ioffset = args->v0.ioffset;
277 ilength = order_base_2(args->v0.ilength / 8);
279 nvkm_kmap(fifo->user.mem);
280 for (i = 0; i < 0x1000; i += 4)
281 nvkm_wo32(fifo->user.mem, usermem + i, 0x00000000);
282 nvkm_done(fifo->user.mem);
283 usermem = nvkm_memory_addr(fifo->user.mem) + usermem;
286 nvkm_kmap(chan->base.inst);
287 nvkm_wo32(chan->base.inst, 0x08, lower_32_bits(usermem));
288 nvkm_wo32(chan->base.inst, 0x0c, upper_32_bits(usermem));
289 nvkm_wo32(chan->base.inst, 0x10, 0x0000face);
290 nvkm_wo32(chan->base.inst, 0x30, 0xfffff902);
291 nvkm_wo32(chan->base.inst, 0x48, lower_32_bits(ioffset));
292 nvkm_wo32(chan->base.inst, 0x4c, upper_32_bits(ioffset) |
294 nvkm_wo32(chan->base.inst, 0x54, 0x00000002);
295 nvkm_wo32(chan->base.inst, 0x84, 0x20400000);
296 nvkm_wo32(chan->base.inst, 0x94, 0x30000001);
297 nvkm_wo32(chan->base.inst, 0x9c, 0x00000100);
298 nvkm_wo32(chan->base.inst, 0xa4, 0x1f1f1f1f);
299 nvkm_wo32(chan->base.inst, 0xa8, 0x1f1f1f1f);
300 nvkm_wo32(chan->base.inst, 0xac, 0x0000001f);
301 nvkm_wo32(chan->base.inst, 0xb8, 0xf8000000);
302 nvkm_wo32(chan->base.inst, 0xf8, 0x10003080); /* 0x002310 */
303 nvkm_wo32(chan->base.inst, 0xfc, 0x10000010); /* 0x002350 */
304 nvkm_done(chan->base.inst);
308 const struct nvkm_fifo_chan_oclass
309 gf100_fifo_gpfifo_oclass = {
310 .base.oclass = FERMI_CHANNEL_GPFIFO,
313 .ctor = gf100_fifo_gpfifo_new,