2 * Copyright 2012 Red Hat Inc.
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
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15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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24 #define nv04_dmaobj(p) container_of((p), struct nv04_dmaobj, base)
27 #include <core/gpuobj.h>
28 #include <subdev/fb.h>
29 #include <subdev/mmu/nv04.h>
31 #include <nvif/class.h>
34 struct nvkm_dmaobj base;
41 nv04_dmaobj_bind(struct nvkm_dmaobj *base, struct nvkm_gpuobj *parent,
42 int align, struct nvkm_gpuobj **pgpuobj)
44 struct nv04_dmaobj *dmaobj = nv04_dmaobj(base);
45 struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device;
46 u64 offset = dmaobj->base.start & 0xfffff000;
47 u64 adjust = dmaobj->base.start & 0x00000fff;
48 u32 length = dmaobj->base.limit - dmaobj->base.start;
52 struct nv04_mmu *mmu = nv04_mmu(device->mmu);
53 struct nvkm_memory *pgt = mmu->vm->pgt[0].mem[0];
54 if (!dmaobj->base.start)
55 return nvkm_gpuobj_wrap(pgt, pgpuobj);
57 offset = nvkm_ro32(pgt, 8 + (offset >> 10));
62 ret = nvkm_gpuobj_new(device, 16, align, false, parent, pgpuobj);
65 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0 | (adjust << 20));
66 nvkm_wo32(*pgpuobj, 0x04, length);
67 nvkm_wo32(*pgpuobj, 0x08, dmaobj->flags2 | offset);
68 nvkm_wo32(*pgpuobj, 0x0c, dmaobj->flags2 | offset);
75 static const struct nvkm_dmaobj_func
77 .bind = nv04_dmaobj_bind,
81 nv04_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass,
82 void *data, u32 size, struct nvkm_dmaobj **pdmaobj)
84 struct nvkm_device *device = dma->engine.subdev.device;
85 struct nv04_dmaobj *dmaobj;
88 if (!(dmaobj = kzalloc(sizeof(*dmaobj), GFP_KERNEL)))
90 *pdmaobj = &dmaobj->base;
92 ret = nvkm_dmaobj_ctor(&nv04_dmaobj_func, dma, oclass,
93 &data, &size, &dmaobj->base);
97 if (dmaobj->base.target == NV_MEM_TARGET_VM) {
98 if (device->mmu->func == &nv04_mmu)
100 dmaobj->base.target = NV_MEM_TARGET_PCI;
101 dmaobj->base.access = NV_MEM_ACCESS_RW;
104 dmaobj->flags0 = oclass->base.oclass;
105 switch (dmaobj->base.target) {
106 case NV_MEM_TARGET_VRAM:
107 dmaobj->flags0 |= 0x00003000;
109 case NV_MEM_TARGET_PCI:
110 dmaobj->flags0 |= 0x00023000;
112 case NV_MEM_TARGET_PCI_NOSNOOP:
113 dmaobj->flags0 |= 0x00033000;
119 switch (dmaobj->base.access) {
120 case NV_MEM_ACCESS_RO:
121 dmaobj->flags0 |= 0x00004000;
123 case NV_MEM_ACCESS_WO:
124 dmaobj->flags0 |= 0x00008000;
125 case NV_MEM_ACCESS_RW:
126 dmaobj->flags2 |= 0x00000002;