2 * Copyright 2012 Red Hat Inc.
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26 #include <subdev/timer.h>
29 nv50_sor_clock(struct nvkm_ior *sor)
31 struct nvkm_device *device = sor->disp->engine.subdev.device;
32 const int div = sor->asy.link == 3;
33 const u32 soff = nv50_ior_base(sor);
34 nvkm_mask(device, 0x614300 + soff, 0x00000707, (div << 8) | div);
38 nv50_sor_power_wait(struct nvkm_device *device, u32 soff)
40 nvkm_msec(device, 2000,
41 if (!(nvkm_rd32(device, 0x61c004 + soff) & 0x80000000))
47 nv50_sor_power(struct nvkm_ior *sor, bool normal, bool pu,
48 bool data, bool vsync, bool hsync)
50 struct nvkm_device *device = sor->disp->engine.subdev.device;
51 const u32 soff = nv50_ior_base(sor);
52 const u32 shift = normal ? 0 : 16;
53 const u32 state = 0x80000000 | (0x00000001 * !!pu) << shift;
54 const u32 field = 0x80000000 | (0x00000001 << shift);
56 nv50_sor_power_wait(device, soff);
57 nvkm_mask(device, 0x61c004 + soff, field, state);
58 nv50_sor_power_wait(device, soff);
60 nvkm_msec(device, 2000,
61 if (!(nvkm_rd32(device, 0x61c030 + soff) & 0x10000000))
67 nv50_sor_state(struct nvkm_ior *sor, struct nvkm_ior_state *state)
69 struct nvkm_device *device = sor->disp->engine.subdev.device;
70 const u32 coff = sor->id * 8 + (state == &sor->arm) * 4;
71 u32 ctrl = nvkm_rd32(device, 0x610b70 + coff);
73 state->proto_evo = (ctrl & 0x00000f00) >> 8;
74 switch (state->proto_evo) {
75 case 0: state->proto = LVDS; state->link = 1; break;
76 case 1: state->proto = TMDS; state->link = 1; break;
77 case 2: state->proto = TMDS; state->link = 2; break;
78 case 5: state->proto = TMDS; state->link = 3; break;
80 state->proto = UNKNOWN;
84 state->head = ctrl & 0x00000003;
87 static const struct nvkm_ior_func
89 .state = nv50_sor_state,
90 .power = nv50_sor_power,
91 .clock = nv50_sor_clock,
95 nv50_sor_new(struct nvkm_disp *disp, int id)
97 return nvkm_ior_new_(&nv50_sor, disp, SOR, id);
101 nv50_sor_cnt(struct nvkm_disp *disp, unsigned long *pmask)
103 struct nvkm_device *device = disp->engine.subdev.device;
104 *pmask = (nvkm_rd32(device, 0x610184) & 0x03000000) >> 24;