drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

   1 /*
   2  * Copyright 2014 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "dp.h"
  25 #include "conn.h"
  26 #include "head.h"
  27 #include "ior.h"
  28
  29 #include <subdev/bios.h>
  30 #include <subdev/bios/init.h>
  31 #include <subdev/i2c.h>
  32
  33 #include <nvif/event.h>
  34
  35 struct lt_state {
  36         struct nvkm_dp *dp;
  37         u8  stat[6];
  38         u8  conf[4];
  39         bool pc2;
  40         u8  pc2stat;
  41         u8  pc2conf[2];
  42 };
  43
  44 static int
  45 nvkm_dp_train_sense(struct lt_state *lt, bool pc, u32 delay)
  46 {
  47         struct nvkm_dp *dp = lt->dp;
  48         int ret;
  49
  50         if (dp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL])
  51                 mdelay(dp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL] * 4);
  52         else
  53                 udelay(delay);
  54
  55         ret = nvkm_rdaux(dp->aux, DPCD_LS02, lt->stat, 6);
  56         if (ret)
  57                 return ret;
  58
  59         if (pc) {
  60                 ret = nvkm_rdaux(dp->aux, DPCD_LS0C, &lt->pc2stat, 1);
  61                 if (ret)
  62                         lt->pc2stat = 0x00;
  63                 OUTP_TRACE(&dp->outp, "status %6ph pc2 %02x",
  64                            lt->stat, lt->pc2stat);
  65         } else {
  66                 OUTP_TRACE(&dp->outp, "status %6ph", lt->stat);
  67         }
  68
  69         return 0;
  70 }
  71
  72 static int
  73 nvkm_dp_train_drive(struct lt_state *lt, bool pc)
  74 {
  75         struct nvkm_dp *dp = lt->dp;
  76         struct nvkm_ior *ior = dp->outp.ior;
  77         struct nvkm_bios *bios = ior->disp->engine.subdev.device->bios;
  78         struct nvbios_dpout info;
  79         struct nvbios_dpcfg ocfg;
  80         u8  ver, hdr, cnt, len;
  81         u32 data;
  82         int ret, i;
  83
  84         for (i = 0; i < ior->dp.nr; i++) {
  85                 u8 lane = (lt->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
  86                 u8 lpc2 = (lt->pc2stat >> (i * 2)) & 0x3;
  87                 u8 lpre = (lane & 0x0c) >> 2;
  88                 u8 lvsw = (lane & 0x03) >> 0;
  89                 u8 hivs = 3 - lpre;
  90                 u8 hipe = 3;
  91                 u8 hipc = 3;
  92
  93                 if (lpc2 >= hipc)
  94                         lpc2 = hipc | DPCD_LC0F_LANE0_MAX_POST_CURSOR2_REACHED;
  95                 if (lpre >= hipe) {
  96                         lpre = hipe | DPCD_LC03_MAX_SWING_REACHED; /* yes. */
  97                         lvsw = hivs = 3 - (lpre & 3);
  98                 } else
  99                 if (lvsw >= hivs) {
 100                         lvsw = hivs | DPCD_LC03_MAX_SWING_REACHED;
 101                 }
 102
 103                 lt->conf[i] = (lpre << 3) | lvsw;
 104                 lt->pc2conf[i >> 1] |= lpc2 << ((i & 1) * 4);
 105
 106                 OUTP_TRACE(&dp->outp, "config lane %d %02x %02x",
 107                            i, lt->conf[i], lpc2);
 108
 109                 data = nvbios_dpout_match(bios, dp->outp.info.hasht,
 110                                                 dp->outp.info.hashm,
 111                                           &ver, &hdr, &cnt, &len, &info);
 112                 if (!data)
 113                         continue;
 114
 115                 data = nvbios_dpcfg_match(bios, data, lpc2 & 3, lvsw & 3,
 116                                           lpre & 3, &ver, &hdr, &cnt, &len,
 117                                           &ocfg);
 118                 if (!data)
 119                         continue;
 120
 121                 ior->func->dp.drive(ior, i, ocfg.pc, ocfg.dc,
 122                                             ocfg.pe, ocfg.tx_pu);
 123         }
 124
 125         ret = nvkm_wraux(dp->aux, DPCD_LC03(0), lt->conf, 4);
 126         if (ret)
 127                 return ret;
 128
 129         if (pc) {
 130                 ret = nvkm_wraux(dp->aux, DPCD_LC0F, lt->pc2conf, 2);
 131                 if (ret)
 132                         return ret;
 133         }
 134
 135         return 0;
 136 }
 137
 138 static void
 139 nvkm_dp_train_pattern(struct lt_state *lt, u8 pattern)
 140 {
 141         struct nvkm_dp *dp = lt->dp;
 142         u8 sink_tp;
 143
 144         OUTP_TRACE(&dp->outp, "training pattern %d", pattern);
 145         dp->outp.ior->func->dp.pattern(dp->outp.ior, pattern);
 146
 147         nvkm_rdaux(dp->aux, DPCD_LC02, &sink_tp, 1);
 148         sink_tp &= ~DPCD_LC02_TRAINING_PATTERN_SET;
 149         sink_tp |= pattern;
 150         nvkm_wraux(dp->aux, DPCD_LC02, &sink_tp, 1);
 151 }
 152
 153 static int
 154 nvkm_dp_train_eq(struct lt_state *lt)
 155 {
 156         bool eq_done = false, cr_done = true;
 157         int tries = 0, i;
 158
 159         if (lt->dp->dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED)
 160                 nvkm_dp_train_pattern(lt, 3);
 161         else
 162                 nvkm_dp_train_pattern(lt, 2);
 163
 164         do {
 165                 if ((tries &&
 166                     nvkm_dp_train_drive(lt, lt->pc2)) ||
 167                     nvkm_dp_train_sense(lt, lt->pc2, 400))
 168                         break;
 169
 170                 eq_done = !!(lt->stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE);
 171                 for (i = 0; i < lt->dp->outp.ior->dp.nr && eq_done; i++) {
 172                         u8 lane = (lt->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
 173                         if (!(lane & DPCD_LS02_LANE0_CR_DONE))
 174                                 cr_done = false;
 175                         if (!(lane & DPCD_LS02_LANE0_CHANNEL_EQ_DONE) ||
 176                             !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED))
 177                                 eq_done = false;
 178                 }
 179         } while (!eq_done && cr_done && ++tries <= 5);
 180
 181         return eq_done ? 0 : -1;
 182 }
 183
 184 static int
 185 nvkm_dp_train_cr(struct lt_state *lt)
 186 {
 187         bool cr_done = false, abort = false;
 188         int voltage = lt->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET;
 189         int tries = 0, i;
 190
 191         nvkm_dp_train_pattern(lt, 1);
 192
 193         do {
 194                 if (nvkm_dp_train_drive(lt, false) ||
 195                     nvkm_dp_train_sense(lt, false, 100))
 196                         break;
 197
 198                 cr_done = true;
 199                 for (i = 0; i < lt->dp->outp.ior->dp.nr; i++) {
 200                         u8 lane = (lt->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
 201                         if (!(lane & DPCD_LS02_LANE0_CR_DONE)) {
 202                                 cr_done = false;
 203                                 if (lt->conf[i] & DPCD_LC03_MAX_SWING_REACHED)
 204                                         abort = true;
 205                                 break;
 206                         }
 207                 }
 208
 209                 if ((lt->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET) != voltage) {
 210                         voltage = lt->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET;
 211                         tries = 0;
 212                 }
 213         } while (!cr_done && !abort && ++tries < 5);
 214
 215         return cr_done ? 0 : -1;
 216 }
 217
 218 static int
 219 nvkm_dp_train_links(struct nvkm_dp *dp)
 220 {
 221         struct nvkm_ior *ior = dp->outp.ior;
 222         struct nvkm_disp *disp = dp->outp.disp;
 223         struct nvkm_subdev *subdev = &disp->engine.subdev;
 224         struct nvkm_bios *bios = subdev->device->bios;
 225         struct lt_state lt = {
 226                 .dp = dp,
 227         };
 228         u32 lnkcmp;
 229         u8 sink[2];
 230         int ret;
 231
 232         OUTP_DBG(&dp->outp, "training %d x %d MB/s",
 233                  ior->dp.nr, ior->dp.bw * 27);
 234
 235         /* Intersect misc. capabilities of the OR and sink. */
 236         if (disp->engine.subdev.device->chipset < 0xd0)
 237                 dp->dpcd[DPCD_RC02] &= ~DPCD_RC02_TPS3_SUPPORTED;
 238         lt.pc2 = dp->dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED;
 239
 240         /* Set desired link configuration on the source. */
 241         if ((lnkcmp = lt.dp->info.lnkcmp)) {
 242                 if (dp->version < 0x30) {
 243                         while ((ior->dp.bw * 2700) < nvbios_rd16(bios, lnkcmp))
 244                                 lnkcmp += 4;
 245                         lnkcmp = nvbios_rd16(bios, lnkcmp + 2);
 246                 } else {
 247                         while (ior->dp.bw < nvbios_rd08(bios, lnkcmp))
 248                                 lnkcmp += 3;
 249                         lnkcmp = nvbios_rd16(bios, lnkcmp + 1);
 250                 }
 251
 252                 nvbios_init(subdev, lnkcmp,
 253                         init.outp = &dp->outp.info;
 254                         init.or   = ior->id;
 255                         init.link = ior->asy.link;
 256                 );
 257         }
 258
 259         ret = ior->func->dp.links(ior, dp->aux);
 260         if (ret) {
 261                 if (ret < 0) {
 262                         OUTP_ERR(&dp->outp, "train failed with %d", ret);
 263                         return ret;
 264                 }
 265                 return 0;
 266         }
 267
 268         ior->func->dp.power(ior, ior->dp.nr);
 269
 270         /* Set desired link configuration on the sink. */
 271         sink[0] = ior->dp.bw;
 272         sink[1] = ior->dp.nr;
 273         if (ior->dp.ef)
 274                 sink[1] |= DPCD_LC01_ENHANCED_FRAME_EN;
 275
 276         ret = nvkm_wraux(dp->aux, DPCD_LC00_LINK_BW_SET, sink, 2);
 277         if (ret)
 278                 return ret;
 279
 280         /* Attempt to train the link in this configuration. */
 281         memset(lt.stat, 0x00, sizeof(lt.stat));
 282         ret = nvkm_dp_train_cr(&lt);
 283         if (ret == 0)
 284                 ret = nvkm_dp_train_eq(&lt);
 285         nvkm_dp_train_pattern(&lt, 0);
 286         return ret;
 287 }
 288
 289 static void
 290 nvkm_dp_train_fini(struct nvkm_dp *dp)
 291 {
 292         /* Execute AfterLinkTraining script from DP Info table. */
 293         nvbios_init(&dp->outp.disp->engine.subdev, dp->info.script[1],
 294                 init.outp = &dp->outp.info;
 295                 init.or   = dp->outp.ior->id;
 296                 init.link = dp->outp.ior->asy.link;
 297         );
 298 }
 299
 300 static void
 301 nvkm_dp_train_init(struct nvkm_dp *dp)
 302 {
 303         /* Execute EnableSpread/DisableSpread script from DP Info table. */
 304         if (dp->dpcd[DPCD_RC03] & DPCD_RC03_MAX_DOWNSPREAD) {
 305                 nvbios_init(&dp->outp.disp->engine.subdev, dp->info.script[2],
 306                         init.outp = &dp->outp.info;
 307                         init.or   = dp->outp.ior->id;
 308                         init.link = dp->outp.ior->asy.link;
 309                 );
 310         } else {
 311                 nvbios_init(&dp->outp.disp->engine.subdev, dp->info.script[3],
 312                         init.outp = &dp->outp.info;
 313                         init.or   = dp->outp.ior->id;
 314                         init.link = dp->outp.ior->asy.link;
 315                 );
 316         }
 317
 318         /* Execute BeforeLinkTraining script from DP Info table. */
 319         nvbios_init(&dp->outp.disp->engine.subdev, dp->info.script[0],
 320                 init.outp = &dp->outp.info;
 321                 init.or   = dp->outp.ior->id;
 322                 init.link = dp->outp.ior->asy.link;
 323         );
 324 }
 325
 326 static const struct dp_rates {
 327         u32 rate;
 328         u8  bw;
 329         u8  nr;
 330 } nvkm_dp_rates[] = {
 331         { 2160000, 0x14, 4 },
 332         { 1080000, 0x0a, 4 },
 333         { 1080000, 0x14, 2 },
 334         {  648000, 0x06, 4 },
 335         {  540000, 0x0a, 2 },
 336         {  540000, 0x14, 1 },
 337         {  324000, 0x06, 2 },
 338         {  270000, 0x0a, 1 },
 339         {  162000, 0x06, 1 },
 340         {}
 341 };
 342
 343 static int
 344 nvkm_dp_train(struct nvkm_dp *dp, u32 dataKBps)
 345 {
 346         struct nvkm_ior *ior = dp->outp.ior;
 347         const u8 sink_nr = dp->dpcd[DPCD_RC02] & DPCD_RC02_MAX_LANE_COUNT;
 348         const u8 sink_bw = dp->dpcd[DPCD_RC01_MAX_LINK_RATE];
 349         const u8 outp_nr = dp->outp.info.dpconf.link_nr;
 350         const u8 outp_bw = dp->outp.info.dpconf.link_bw;
 351         const struct dp_rates *failsafe = NULL, *cfg;
 352         int ret = -EINVAL;
 353         u8  pwr;
 354
 355         /* Find the lowest configuration of the OR that can support
 356          * the required link rate.
 357          *
 358          * We will refuse to program the OR to lower rates, even if
 359          * link training fails at higher rates (or even if the sink
 360          * can't support the rate at all, though the DD is supposed
 361          * to prevent such situations from happening).
 362          *
 363          * Attempting to do so can cause the entire display to hang,
 364          * and it's better to have a failed modeset than that.
 365          */
 366         for (cfg = nvkm_dp_rates; cfg->rate; cfg++) {
 367                 if (cfg->nr <= outp_nr && cfg->nr <= outp_bw) {
 368                         /* Try to respect sink limits too when selecting
 369                          * lowest link configuration.
 370                          */
 371                         if (!failsafe ||
 372                             (cfg->nr <= sink_nr && cfg->bw <= sink_bw))
 373                                 failsafe = cfg;
 374                 }
 375
 376                 if (failsafe && cfg[1].rate < dataKBps)
 377                         break;
 378         }
 379
 380         if (WARN_ON(!failsafe))
 381                 return ret;
 382
 383         /* Ensure sink is not in a low-power state. */
 384         if (!nvkm_rdaux(dp->aux, DPCD_SC00, &pwr, 1)) {
 385                 if ((pwr & DPCD_SC00_SET_POWER) != DPCD_SC00_SET_POWER_D0) {
 386                         pwr &= ~DPCD_SC00_SET_POWER;
 387                         pwr |=  DPCD_SC00_SET_POWER_D0;
 388                         nvkm_wraux(dp->aux, DPCD_SC00, &pwr, 1);
 389                 }
 390         }
 391
 392         /* Link training. */
 393         OUTP_DBG(&dp->outp, "training (min: %d x %d MB/s)",
 394                  failsafe->nr, failsafe->bw * 27);
 395         nvkm_dp_train_init(dp);
 396         for (cfg = nvkm_dp_rates; ret < 0 && cfg <= failsafe; cfg++) {
 397                 /* Skip configurations not supported by both OR and sink. */
 398                 if ((cfg->nr > outp_nr || cfg->bw > outp_bw ||
 399                      cfg->nr > sink_nr || cfg->bw > sink_bw)) {
 400                         if (cfg != failsafe)
 401                                 continue;
 402                         OUTP_ERR(&dp->outp, "link rate unsupported by sink");
 403                 }
 404                 ior->dp.mst = dp->lt.mst;
 405                 ior->dp.ef = dp->dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP;
 406                 ior->dp.bw = cfg->bw;
 407                 ior->dp.nr = cfg->nr;
 408
 409                 /* Program selected link configuration. */
 410                 ret = nvkm_dp_train_links(dp);
 411         }
 412         nvkm_dp_train_fini(dp);
 413         if (ret < 0)
 414                 OUTP_ERR(&dp->outp, "training failed");
 415         else
 416                 OUTP_DBG(&dp->outp, "training done");
 417         atomic_set(&dp->lt.done, 1);
 418         return ret;
 419 }
 420
 421 void
 422 nvkm_dp_disable(struct nvkm_outp *outp, struct nvkm_ior *ior)
 423 {
 424         struct nvkm_dp *dp = nvkm_dp(outp);
 425
 426         /* Execute DisableLT script from DP Info Table. */
 427         nvbios_init(&ior->disp->engine.subdev, dp->info.script[4],
 428                 init.outp = &dp->outp.info;
 429                 init.or   = ior->id;
 430                 init.link = ior->arm.link;
 431         );
 432 }
 433
 434 static void
 435 nvkm_dp_release(struct nvkm_outp *outp)
 436 {
 437         struct nvkm_dp *dp = nvkm_dp(outp);
 438
 439         /* Prevent link from being retrained if sink sends an IRQ. */
 440         atomic_set(&dp->lt.done, 0);
 441         dp->outp.ior->dp.nr = 0;
 442 }
 443
 444 static int
 445 nvkm_dp_acquire(struct nvkm_outp *outp)
 446 {
 447         struct nvkm_dp *dp = nvkm_dp(outp);
 448         struct nvkm_ior *ior = dp->outp.ior;
 449         struct nvkm_head *head;
 450         bool retrain = true;
 451         u32 datakbps = 0;
 452         u32 dataKBps;
 453         u32 linkKBps;
 454         u8  stat[3];
 455         int ret, i;
 456
 457         mutex_lock(&dp->mutex);
 458
 459         /* Check that link configuration meets current requirements. */
 460         list_for_each_entry(head, &outp->disp->head, head) {
 461                 if (ior->asy.head & (1 << head->id)) {
 462                         u32 khz = (head->asy.hz >> ior->asy.rgdiv) / 1000;
 463                         datakbps += khz * head->asy.or.depth;
 464                 }
 465         }
 466
 467         linkKBps = ior->dp.bw * 27000 * ior->dp.nr;
 468         dataKBps = DIV_ROUND_UP(datakbps, 8);
 469         OUTP_DBG(&dp->outp, "data %d KB/s link %d KB/s mst %d->%d",
 470                  dataKBps, linkKBps, ior->dp.mst, dp->lt.mst);
 471         if (linkKBps < dataKBps || ior->dp.mst != dp->lt.mst) {
 472                 OUTP_DBG(&dp->outp, "link requirements changed");
 473                 goto done;
 474         }
 475
 476         /* Check that link is still trained. */
 477         ret = nvkm_rdaux(dp->aux, DPCD_LS02, stat, 3);
 478         if (ret) {
 479                 OUTP_DBG(&dp->outp,
 480                          "failed to read link status, assuming no sink");
 481                 goto done;
 482         }
 483
 484         if (stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE) {
 485                 for (i = 0; i < ior->dp.nr; i++) {
 486                         u8 lane = (stat[i >> 1] >> ((i & 1) * 4)) & 0x0f;
 487                         if (!(lane & DPCD_LS02_LANE0_CR_DONE) ||
 488                             !(lane & DPCD_LS02_LANE0_CHANNEL_EQ_DONE) ||
 489                             !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED)) {
 490                                 OUTP_DBG(&dp->outp,
 491                                          "lane %d not equalised", lane);
 492                                 goto done;
 493                         }
 494                 }
 495                 retrain = false;
 496         } else {
 497                 OUTP_DBG(&dp->outp, "no inter-lane alignment");
 498         }
 499
 500 done:
 501         if (retrain || !atomic_read(&dp->lt.done))
 502                 ret = nvkm_dp_train(dp, dataKBps);
 503         mutex_unlock(&dp->mutex);
 504         return ret;
 505 }
 506
 507 static void
 508 nvkm_dp_enable(struct nvkm_dp *dp, bool enable)
 509 {
 510         struct nvkm_i2c_aux *aux = dp->aux;
 511
 512         if (enable) {
 513                 if (!dp->present) {
 514                         OUTP_DBG(&dp->outp, "aux power -> always");
 515                         nvkm_i2c_aux_monitor(aux, true);
 516                         dp->present = true;
 517                 }
 518
 519                 if (!nvkm_rdaux(aux, DPCD_RC00_DPCD_REV, dp->dpcd,
 520                                 sizeof(dp->dpcd)))
 521                         return;
 522         }
 523
 524         if (dp->present) {
 525                 OUTP_DBG(&dp->outp, "aux power -> demand");
 526                 nvkm_i2c_aux_monitor(aux, false);
 527                 dp->present = false;
 528         }
 529
 530         atomic_set(&dp->lt.done, 0);
 531 }
 532
 533 static int
 534 nvkm_dp_hpd(struct nvkm_notify *notify)
 535 {
 536         const struct nvkm_i2c_ntfy_rep *line = notify->data;
 537         struct nvkm_dp *dp = container_of(notify, typeof(*dp), hpd);
 538         struct nvkm_conn *conn = dp->outp.conn;
 539         struct nvkm_disp *disp = dp->outp.disp;
 540         struct nvif_notify_conn_rep_v0 rep = {};
 541
 542         OUTP_DBG(&dp->outp, "HPD: %d", line->mask);
 543         if (line->mask & NVKM_I2C_IRQ) {
 544                 if (atomic_read(&dp->lt.done))
 545                         dp->outp.func->acquire(&dp->outp);
 546                 rep.mask |= NVIF_NOTIFY_CONN_V0_IRQ;
 547         } else {
 548                 nvkm_dp_enable(dp, true);
 549         }
 550
 551         if (line->mask & NVKM_I2C_UNPLUG)
 552                 rep.mask |= NVIF_NOTIFY_CONN_V0_UNPLUG;
 553         if (line->mask & NVKM_I2C_PLUG)
 554                 rep.mask |= NVIF_NOTIFY_CONN_V0_PLUG;
 555
 556         nvkm_event_send(&disp->hpd, rep.mask, conn->index, &rep, sizeof(rep));
 557         return NVKM_NOTIFY_KEEP;
 558 }
 559
 560 static void
 561 nvkm_dp_fini(struct nvkm_outp *outp)
 562 {
 563         struct nvkm_dp *dp = nvkm_dp(outp);
 564         nvkm_notify_put(&dp->hpd);
 565         nvkm_dp_enable(dp, false);
 566 }
 567
 568 static void
 569 nvkm_dp_init(struct nvkm_outp *outp)
 570 {
 571         struct nvkm_dp *dp = nvkm_dp(outp);
 572         nvkm_notify_put(&dp->outp.conn->hpd);
 573         nvkm_dp_enable(dp, true);
 574         nvkm_notify_get(&dp->hpd);
 575 }
 576
 577 static void *
 578 nvkm_dp_dtor(struct nvkm_outp *outp)
 579 {
 580         struct nvkm_dp *dp = nvkm_dp(outp);
 581         nvkm_notify_fini(&dp->hpd);
 582         return dp;
 583 }
 584
 585 static const struct nvkm_outp_func
 586 nvkm_dp_func = {
 587         .dtor = nvkm_dp_dtor,
 588         .init = nvkm_dp_init,
 589         .fini = nvkm_dp_fini,
 590         .acquire = nvkm_dp_acquire,
 591         .release = nvkm_dp_release,
 592         .disable = nvkm_dp_disable,
 593 };
 594
 595 static int
 596 nvkm_dp_ctor(struct nvkm_disp *disp, int index, struct dcb_output *dcbE,
 597              struct nvkm_i2c_aux *aux, struct nvkm_dp *dp)
 598 {
 599         struct nvkm_device *device = disp->engine.subdev.device;
 600         struct nvkm_bios *bios = device->bios;
 601         struct nvkm_i2c *i2c = device->i2c;
 602         u8  hdr, cnt, len;
 603         u32 data;
 604         int ret;
 605
 606         ret = nvkm_outp_ctor(&nvkm_dp_func, disp, index, dcbE, &dp->outp);
 607         if (ret)
 608                 return ret;
 609
 610         dp->aux = aux;
 611         if (!dp->aux) {
 612                 OUTP_ERR(&dp->outp, "no aux");
 613                 return -EINVAL;
 614         }
 615
 616         /* bios data is not optional */
 617         data = nvbios_dpout_match(bios, dp->outp.info.hasht,
 618                                   dp->outp.info.hashm, &dp->version,
 619                                   &hdr, &cnt, &len, &dp->info);
 620         if (!data) {
 621                 OUTP_ERR(&dp->outp, "no bios dp data");
 622                 return -EINVAL;
 623         }
 624
 625         OUTP_DBG(&dp->outp, "bios dp %02x %02x %02x %02x",
 626                  dp->version, hdr, cnt, len);
 627
 628         /* hotplug detect, replaces gpio-based mechanism with aux events */
 629         ret = nvkm_notify_init(NULL, &i2c->event, nvkm_dp_hpd, true,
 630                                &(struct nvkm_i2c_ntfy_req) {
 631                                 .mask = NVKM_I2C_PLUG | NVKM_I2C_UNPLUG |
 632                                         NVKM_I2C_IRQ,
 633                                 .port = dp->aux->id,
 634                                },
 635                                sizeof(struct nvkm_i2c_ntfy_req),
 636                                sizeof(struct nvkm_i2c_ntfy_rep),
 637                                &dp->hpd);
 638         if (ret) {
 639                 OUTP_ERR(&dp->outp, "error monitoring aux hpd: %d", ret);
 640                 return ret;
 641         }
 642
 643         mutex_init(&dp->mutex);
 644         atomic_set(&dp->lt.done, 0);
 645         return 0;
 646 }
 647
 648 int
 649 nvkm_dp_new(struct nvkm_disp *disp, int index, struct dcb_output *dcbE,
 650             struct nvkm_outp **poutp)
 651 {
 652         struct nvkm_i2c *i2c = disp->engine.subdev.device->i2c;
 653         struct nvkm_i2c_aux *aux;
 654         struct nvkm_dp *dp;
 655
 656         if (dcbE->location == 0)
 657                 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_CCB(dcbE->i2c_index));
 658         else
 659                 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbE->extdev));
 660
 661         if (!(dp = kzalloc(sizeof(*dp), GFP_KERNEL)))
 662                 return -ENOMEM;
 663         *poutp = &dp->outp;
 664
 665         return nvkm_dp_ctor(disp, index, dcbE, aux, dp);
 666 }