drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "dmacnv50.h"
  25 #include "rootnv50.h"
  26
  27 #include <core/client.h>
  28 #include <subdev/timer.h>
  29
  30 #include <nvif/class.h>
  31 #include <nvif/cl507d.h>
  32 #include <nvif/unpack.h>
  33
  34 int
  35 nv50_disp_core_new(const struct nv50_disp_dmac_func *func,
  36                    const struct nv50_disp_chan_mthd *mthd,
  37                    struct nv50_disp_root *root, int chid,
  38                    const struct nvkm_oclass *oclass, void *data, u32 size,
  39                    struct nvkm_object **pobject)
  40 {
  41         union {
  42                 struct nv50_disp_core_channel_dma_v0 v0;
  43         } *args = data;
  44         struct nvkm_object *parent = oclass->parent;
  45         u64 push;
  46         int ret = -ENOSYS;
  47
  48         nvif_ioctl(parent, "create disp core channel dma size %d\n", size);
  49         if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
  50                 nvif_ioctl(parent, "create disp core channel dma vers %d "
  51                                    "pushbuf %016llx\n",
  52                            args->v0.version, args->v0.pushbuf);
  53                 push = args->v0.pushbuf;
  54         } else
  55                 return ret;
  56
  57         return nv50_disp_dmac_new_(func, mthd, root, chid, 0,
  58                                    push, oclass, pobject);
  59 }
  60
  61 const struct nv50_disp_mthd_list
  62 nv50_disp_core_mthd_base = {
  63         .mthd = 0x0000,
  64         .addr = 0x000000,
  65         .data = {
  66                 { 0x0080, 0x000000 },
  67                 { 0x0084, 0x610bb8 },
  68                 { 0x0088, 0x610b9c },
  69                 { 0x008c, 0x000000 },
  70                 {}
  71         }
  72 };
  73
  74 static const struct nv50_disp_mthd_list
  75 nv50_disp_core_mthd_dac = {
  76         .mthd = 0x0080,
  77         .addr = 0x000008,
  78         .data = {
  79                 { 0x0400, 0x610b58 },
  80                 { 0x0404, 0x610bdc },
  81                 { 0x0420, 0x610828 },
  82                 {}
  83         }
  84 };
  85
  86 const struct nv50_disp_mthd_list
  87 nv50_disp_core_mthd_sor = {
  88         .mthd = 0x0040,
  89         .addr = 0x000008,
  90         .data = {
  91                 { 0x0600, 0x610b70 },
  92                 {}
  93         }
  94 };
  95
  96 const struct nv50_disp_mthd_list
  97 nv50_disp_core_mthd_pior = {
  98         .mthd = 0x0040,
  99         .addr = 0x000008,
 100         .data = {
 101                 { 0x0700, 0x610b80 },
 102                 {}
 103         }
 104 };
 105
 106 static const struct nv50_disp_mthd_list
 107 nv50_disp_core_mthd_head = {
 108         .mthd = 0x0400,
 109         .addr = 0x000540,
 110         .data = {
 111                 { 0x0800, 0x610ad8 },
 112                 { 0x0804, 0x610ad0 },
 113                 { 0x0808, 0x610a48 },
 114                 { 0x080c, 0x610a78 },
 115                 { 0x0810, 0x610ac0 },
 116                 { 0x0814, 0x610af8 },
 117                 { 0x0818, 0x610b00 },
 118                 { 0x081c, 0x610ae8 },
 119                 { 0x0820, 0x610af0 },
 120                 { 0x0824, 0x610b08 },
 121                 { 0x0828, 0x610b10 },
 122                 { 0x082c, 0x610a68 },
 123                 { 0x0830, 0x610a60 },
 124                 { 0x0834, 0x000000 },
 125                 { 0x0838, 0x610a40 },
 126                 { 0x0840, 0x610a24 },
 127                 { 0x0844, 0x610a2c },
 128                 { 0x0848, 0x610aa8 },
 129                 { 0x084c, 0x610ab0 },
 130                 { 0x0860, 0x610a84 },
 131                 { 0x0864, 0x610a90 },
 132                 { 0x0868, 0x610b18 },
 133                 { 0x086c, 0x610b20 },
 134                 { 0x0870, 0x610ac8 },
 135                 { 0x0874, 0x610a38 },
 136                 { 0x0880, 0x610a58 },
 137                 { 0x0884, 0x610a9c },
 138                 { 0x08a0, 0x610a70 },
 139                 { 0x08a4, 0x610a50 },
 140                 { 0x08a8, 0x610ae0 },
 141                 { 0x08c0, 0x610b28 },
 142                 { 0x08c4, 0x610b30 },
 143                 { 0x08c8, 0x610b40 },
 144                 { 0x08d4, 0x610b38 },
 145                 { 0x08d8, 0x610b48 },
 146                 { 0x08dc, 0x610b50 },
 147                 { 0x0900, 0x610a18 },
 148                 { 0x0904, 0x610ab8 },
 149                 {}
 150         }
 151 };
 152
 153 static const struct nv50_disp_chan_mthd
 154 nv50_disp_core_chan_mthd = {
 155         .name = "Core",
 156         .addr = 0x000000,
 157         .prev = 0x000004,
 158         .data = {
 159                 { "Global", 1, &nv50_disp_core_mthd_base },
 160                 {    "DAC", 3, &nv50_disp_core_mthd_dac  },
 161                 {    "SOR", 2, &nv50_disp_core_mthd_sor  },
 162                 {   "PIOR", 3, &nv50_disp_core_mthd_pior },
 163                 {   "HEAD", 2, &nv50_disp_core_mthd_head },
 164                 {}
 165         }
 166 };
 167
 168 static void
 169 nv50_disp_core_fini(struct nv50_disp_dmac *chan)
 170 {
 171         struct nv50_disp *disp = chan->base.root->disp;
 172         struct nvkm_subdev *subdev = &disp->base.engine.subdev;
 173         struct nvkm_device *device = subdev->device;
 174
 175         /* deactivate channel */
 176         nvkm_mask(device, 0x610200, 0x00000010, 0x00000000);
 177         nvkm_mask(device, 0x610200, 0x00000003, 0x00000000);
 178         if (nvkm_msec(device, 2000,
 179                 if (!(nvkm_rd32(device, 0x610200) & 0x001e0000))
 180                         break;
 181         ) < 0) {
 182                 nvkm_error(subdev, "core fini: %08x\n",
 183                            nvkm_rd32(device, 0x610200));
 184         }
 185
 186         /* disable error reporting and completion notifications */
 187         nvkm_mask(device, 0x610028, 0x00010001, 0x00000000);
 188 }
 189
 190 static int
 191 nv50_disp_core_init(struct nv50_disp_dmac *chan)
 192 {
 193         struct nv50_disp *disp = chan->base.root->disp;
 194         struct nvkm_subdev *subdev = &disp->base.engine.subdev;
 195         struct nvkm_device *device = subdev->device;
 196
 197         /* enable error reporting */
 198         nvkm_mask(device, 0x610028, 0x00010000, 0x00010000);
 199
 200         /* attempt to unstick channel from some unknown state */
 201         if ((nvkm_rd32(device, 0x610200) & 0x009f0000) == 0x00020000)
 202                 nvkm_mask(device, 0x610200, 0x00800000, 0x00800000);
 203         if ((nvkm_rd32(device, 0x610200) & 0x003f0000) == 0x00030000)
 204                 nvkm_mask(device, 0x610200, 0x00600000, 0x00600000);
 205
 206         /* initialise channel for dma command submission */
 207         nvkm_wr32(device, 0x610204, chan->push);
 208         nvkm_wr32(device, 0x610208, 0x00010000);
 209         nvkm_wr32(device, 0x61020c, 0x00000000);
 210         nvkm_mask(device, 0x610200, 0x00000010, 0x00000010);
 211         nvkm_wr32(device, 0x640000, 0x00000000);
 212         nvkm_wr32(device, 0x610200, 0x01000013);
 213
 214         /* wait for it to go inactive */
 215         if (nvkm_msec(device, 2000,
 216                 if (!(nvkm_rd32(device, 0x610200) & 0x80000000))
 217                         break;
 218         ) < 0) {
 219                 nvkm_error(subdev, "core init: %08x\n",
 220                            nvkm_rd32(device, 0x610200));
 221                 return -EBUSY;
 222         }
 223
 224         return 0;
 225 }
 226
 227 const struct nv50_disp_dmac_func
 228 nv50_disp_core_func = {
 229         .init = nv50_disp_core_init,
 230         .fini = nv50_disp_core_fini,
 231         .bind = nv50_disp_dmac_bind,
 232 };
 233
 234 const struct nv50_disp_dmac_oclass
 235 nv50_disp_core_oclass = {
 236         .base.oclass = NV50_DISP_CORE_CHANNEL_DMA,
 237         .base.minver = 0,
 238         .base.maxver = 0,
 239         .ctor = nv50_disp_core_new,
 240         .func = &nv50_disp_core_func,
 241         .mthd = &nv50_disp_core_chan_mthd,
 242         .chid = 0,
 243 };