drivers/gpu/drm/nouveau/nvkm/engine/disp/coregk104.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "dmacnv50.h"
  25 #include "rootnv50.h"
  26
  27 #include <nvif/class.h>
  28
  29 static const struct nv50_disp_mthd_list
  30 gk104_disp_core_mthd_head = {
  31         .mthd = 0x0300,
  32         .addr = 0x000300,
  33         .data = {
  34                 { 0x0400, 0x660400 },
  35                 { 0x0404, 0x660404 },
  36                 { 0x0408, 0x660408 },
  37                 { 0x040c, 0x66040c },
  38                 { 0x0410, 0x660410 },
  39                 { 0x0414, 0x660414 },
  40                 { 0x0418, 0x660418 },
  41                 { 0x041c, 0x66041c },
  42                 { 0x0420, 0x660420 },
  43                 { 0x0424, 0x660424 },
  44                 { 0x0428, 0x660428 },
  45                 { 0x042c, 0x66042c },
  46                 { 0x0430, 0x660430 },
  47                 { 0x0434, 0x660434 },
  48                 { 0x0438, 0x660438 },
  49                 { 0x0440, 0x660440 },
  50                 { 0x0444, 0x660444 },
  51                 { 0x0448, 0x660448 },
  52                 { 0x044c, 0x66044c },
  53                 { 0x0450, 0x660450 },
  54                 { 0x0454, 0x660454 },
  55                 { 0x0458, 0x660458 },
  56                 { 0x045c, 0x66045c },
  57                 { 0x0460, 0x660460 },
  58                 { 0x0468, 0x660468 },
  59                 { 0x046c, 0x66046c },
  60                 { 0x0470, 0x660470 },
  61                 { 0x0474, 0x660474 },
  62                 { 0x047c, 0x66047c },
  63                 { 0x0480, 0x660480 },
  64                 { 0x0484, 0x660484 },
  65                 { 0x0488, 0x660488 },
  66                 { 0x048c, 0x66048c },
  67                 { 0x0490, 0x660490 },
  68                 { 0x0494, 0x660494 },
  69                 { 0x0498, 0x660498 },
  70                 { 0x04a0, 0x6604a0 },
  71                 { 0x04b0, 0x6604b0 },
  72                 { 0x04b8, 0x6604b8 },
  73                 { 0x04bc, 0x6604bc },
  74                 { 0x04c0, 0x6604c0 },
  75                 { 0x04c4, 0x6604c4 },
  76                 { 0x04c8, 0x6604c8 },
  77                 { 0x04d0, 0x6604d0 },
  78                 { 0x04d4, 0x6604d4 },
  79                 { 0x04e0, 0x6604e0 },
  80                 { 0x04e4, 0x6604e4 },
  81                 { 0x04e8, 0x6604e8 },
  82                 { 0x04ec, 0x6604ec },
  83                 { 0x04f0, 0x6604f0 },
  84                 { 0x04f4, 0x6604f4 },
  85                 { 0x04f8, 0x6604f8 },
  86                 { 0x04fc, 0x6604fc },
  87                 { 0x0500, 0x660500 },
  88                 { 0x0504, 0x660504 },
  89                 { 0x0508, 0x660508 },
  90                 { 0x050c, 0x66050c },
  91                 { 0x0510, 0x660510 },
  92                 { 0x0514, 0x660514 },
  93                 { 0x0518, 0x660518 },
  94                 { 0x051c, 0x66051c },
  95                 { 0x0520, 0x660520 },
  96                 { 0x0524, 0x660524 },
  97                 { 0x052c, 0x66052c },
  98                 { 0x0530, 0x660530 },
  99                 { 0x054c, 0x66054c },
 100                 { 0x0550, 0x660550 },
 101                 { 0x0554, 0x660554 },
 102                 { 0x0558, 0x660558 },
 103                 { 0x055c, 0x66055c },
 104                 {}
 105         }
 106 };
 107
 108 const struct nv50_disp_chan_mthd
 109 gk104_disp_core_chan_mthd = {
 110         .name = "Core",
 111         .addr = 0x000000,
 112         .prev = -0x020000,
 113         .data = {
 114                 { "Global", 1, &gf119_disp_core_mthd_base },
 115                 {    "DAC", 3, &gf119_disp_core_mthd_dac  },
 116                 {    "SOR", 8, &gf119_disp_core_mthd_sor  },
 117                 {   "PIOR", 4, &gf119_disp_core_mthd_pior },
 118                 {   "HEAD", 4, &gk104_disp_core_mthd_head },
 119                 {}
 120         }
 121 };
 122
 123 const struct nv50_disp_dmac_oclass
 124 gk104_disp_core_oclass = {
 125         .base.oclass = GK104_DISP_CORE_CHANNEL_DMA,
 126         .base.minver = 0,
 127         .base.maxver = 0,
 128         .ctor = nv50_disp_core_new,
 129         .func = &gf119_disp_core_func,
 130         .mthd = &gk104_disp_core_chan_mthd,
 131         .chid = 0,
 132 };