GNU Linux-libre 4.9.288-gnu1
[releases.git] / drivers / gpu / drm / nouveau / nvkm / engine / disp / coreg84.c
1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 #include "dmacnv50.h"
25 #include "rootnv50.h"
26
27 #include <nvif/class.h>
28
29 const struct nv50_disp_mthd_list
30 g84_disp_core_mthd_dac = {
31         .mthd = 0x0080,
32         .addr = 0x000008,
33         .data = {
34                 { 0x0400, 0x610b58 },
35                 { 0x0404, 0x610bdc },
36                 { 0x0420, 0x610bc4 },
37                 {}
38         }
39 };
40
41 const struct nv50_disp_mthd_list
42 g84_disp_core_mthd_head = {
43         .mthd = 0x0400,
44         .addr = 0x000540,
45         .data = {
46                 { 0x0800, 0x610ad8 },
47                 { 0x0804, 0x610ad0 },
48                 { 0x0808, 0x610a48 },
49                 { 0x080c, 0x610a78 },
50                 { 0x0810, 0x610ac0 },
51                 { 0x0814, 0x610af8 },
52                 { 0x0818, 0x610b00 },
53                 { 0x081c, 0x610ae8 },
54                 { 0x0820, 0x610af0 },
55                 { 0x0824, 0x610b08 },
56                 { 0x0828, 0x610b10 },
57                 { 0x082c, 0x610a68 },
58                 { 0x0830, 0x610a60 },
59                 { 0x0834, 0x000000 },
60                 { 0x0838, 0x610a40 },
61                 { 0x0840, 0x610a24 },
62                 { 0x0844, 0x610a2c },
63                 { 0x0848, 0x610aa8 },
64                 { 0x084c, 0x610ab0 },
65                 { 0x085c, 0x610c5c },
66                 { 0x0860, 0x610a84 },
67                 { 0x0864, 0x610a90 },
68                 { 0x0868, 0x610b18 },
69                 { 0x086c, 0x610b20 },
70                 { 0x0870, 0x610ac8 },
71                 { 0x0874, 0x610a38 },
72                 { 0x0878, 0x610c50 },
73                 { 0x0880, 0x610a58 },
74                 { 0x0884, 0x610a9c },
75                 { 0x089c, 0x610c68 },
76                 { 0x08a0, 0x610a70 },
77                 { 0x08a4, 0x610a50 },
78                 { 0x08a8, 0x610ae0 },
79                 { 0x08c0, 0x610b28 },
80                 { 0x08c4, 0x610b30 },
81                 { 0x08c8, 0x610b40 },
82                 { 0x08d4, 0x610b38 },
83                 { 0x08d8, 0x610b48 },
84                 { 0x08dc, 0x610b50 },
85                 { 0x0900, 0x610a18 },
86                 { 0x0904, 0x610ab8 },
87                 { 0x0910, 0x610c70 },
88                 { 0x0914, 0x610c78 },
89                 {}
90         }
91 };
92
93 const struct nv50_disp_chan_mthd
94 g84_disp_core_chan_mthd = {
95         .name = "Core",
96         .addr = 0x000000,
97         .prev = 0x000004,
98         .data = {
99                 { "Global", 1, &nv50_disp_core_mthd_base },
100                 {    "DAC", 3, &g84_disp_core_mthd_dac  },
101                 {    "SOR", 2, &nv50_disp_core_mthd_sor  },
102                 {   "PIOR", 3, &nv50_disp_core_mthd_pior },
103                 {   "HEAD", 2, &g84_disp_core_mthd_head },
104                 {}
105         }
106 };
107
108 const struct nv50_disp_dmac_oclass
109 g84_disp_core_oclass = {
110         .base.oclass = G82_DISP_CORE_CHANNEL_DMA,
111         .base.minver = 0,
112         .base.maxver = 0,
113         .ctor = nv50_disp_core_new,
114         .func = &nv50_disp_core_func,
115         .mthd = &g84_disp_core_chan_mthd,
116         .chid = 0,
117 };