2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/delay.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/vga_switcheroo.h>
30 #include <linux/mmu_notifier.h>
32 #include <drm/drm_aperture.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_drv.h>
35 #include <drm/drm_gem_ttm_helper.h>
36 #include <drm/drm_ioctl.h>
37 #include <drm/drm_vblank.h>
39 #include <core/gpuobj.h>
40 #include <core/option.h>
42 #include <core/tegra.h>
44 #include <nvif/driver.h>
45 #include <nvif/fifo.h>
46 #include <nvif/push006c.h>
47 #include <nvif/user.h>
49 #include <nvif/class.h>
50 #include <nvif/cl0002.h>
51 #include <nvif/cla06f.h>
53 #include "nouveau_drv.h"
54 #include "nouveau_dma.h"
55 #include "nouveau_ttm.h"
56 #include "nouveau_gem.h"
57 #include "nouveau_vga.h"
58 #include "nouveau_led.h"
59 #include "nouveau_hwmon.h"
60 #include "nouveau_acpi.h"
61 #include "nouveau_bios.h"
62 #include "nouveau_ioctl.h"
63 #include "nouveau_abi16.h"
64 #include "nouveau_fbcon.h"
65 #include "nouveau_fence.h"
66 #include "nouveau_debugfs.h"
67 #include "nouveau_usif.h"
68 #include "nouveau_connector.h"
69 #include "nouveau_platform.h"
70 #include "nouveau_svm.h"
71 #include "nouveau_dmem.h"
73 MODULE_PARM_DESC(config, "option string to pass to driver core");
74 static char *nouveau_config;
75 module_param_named(config, nouveau_config, charp, 0400);
77 MODULE_PARM_DESC(debug, "debug string to pass to driver core");
78 static char *nouveau_debug;
79 module_param_named(debug, nouveau_debug, charp, 0400);
81 MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration");
82 static int nouveau_noaccel = 0;
83 module_param_named(noaccel, nouveau_noaccel, int, 0400);
85 MODULE_PARM_DESC(modeset, "enable driver (default: auto, "
86 "0 = disabled, 1 = enabled, 2 = headless)");
87 int nouveau_modeset = -1;
88 module_param_named(modeset, nouveau_modeset, int, 0400);
90 MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)");
91 static int nouveau_atomic = 0;
92 module_param_named(atomic, nouveau_atomic, int, 0400);
94 MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)");
95 static int nouveau_runtime_pm = -1;
96 module_param_named(runpm, nouveau_runtime_pm, int, 0400);
98 static struct drm_driver driver_stub;
99 static struct drm_driver driver_pci;
100 static struct drm_driver driver_platform;
103 nouveau_pci_name(struct pci_dev *pdev)
105 u64 name = (u64)pci_domain_nr(pdev->bus) << 32;
106 name |= pdev->bus->number << 16;
107 name |= PCI_SLOT(pdev->devfn) << 8;
108 return name | PCI_FUNC(pdev->devfn);
112 nouveau_platform_name(struct platform_device *platformdev)
114 return platformdev->id;
118 nouveau_name(struct drm_device *dev)
120 if (dev_is_pci(dev->dev))
121 return nouveau_pci_name(to_pci_dev(dev->dev));
123 return nouveau_platform_name(to_platform_device(dev->dev));
127 nouveau_cli_work_ready(struct dma_fence *fence)
129 if (!dma_fence_is_signaled(fence))
131 dma_fence_put(fence);
136 nouveau_cli_work(struct work_struct *w)
138 struct nouveau_cli *cli = container_of(w, typeof(*cli), work);
139 struct nouveau_cli_work *work, *wtmp;
140 mutex_lock(&cli->lock);
141 list_for_each_entry_safe(work, wtmp, &cli->worker, head) {
142 if (!work->fence || nouveau_cli_work_ready(work->fence)) {
143 list_del(&work->head);
147 mutex_unlock(&cli->lock);
151 nouveau_cli_work_fence(struct dma_fence *fence, struct dma_fence_cb *cb)
153 struct nouveau_cli_work *work = container_of(cb, typeof(*work), cb);
154 schedule_work(&work->cli->work);
158 nouveau_cli_work_queue(struct nouveau_cli *cli, struct dma_fence *fence,
159 struct nouveau_cli_work *work)
161 work->fence = dma_fence_get(fence);
163 mutex_lock(&cli->lock);
164 list_add_tail(&work->head, &cli->worker);
165 if (dma_fence_add_callback(fence, &work->cb, nouveau_cli_work_fence))
166 nouveau_cli_work_fence(fence, &work->cb);
167 mutex_unlock(&cli->lock);
171 nouveau_cli_fini(struct nouveau_cli *cli)
173 /* All our channels are dead now, which means all the fences they
174 * own are signalled, and all callback functions have been called.
176 * So, after flushing the workqueue, there should be nothing left.
178 flush_work(&cli->work);
179 WARN_ON(!list_empty(&cli->worker));
181 usif_client_fini(cli);
182 nouveau_vmm_fini(&cli->svm);
183 nouveau_vmm_fini(&cli->vmm);
184 nvif_mmu_dtor(&cli->mmu);
185 nvif_device_dtor(&cli->device);
186 mutex_lock(&cli->drm->master.lock);
187 nvif_client_dtor(&cli->base);
188 mutex_unlock(&cli->drm->master.lock);
192 nouveau_cli_init(struct nouveau_drm *drm, const char *sname,
193 struct nouveau_cli *cli)
195 static const struct nvif_mclass
197 { NVIF_CLASS_MEM_GF100, -1 },
198 { NVIF_CLASS_MEM_NV50 , -1 },
199 { NVIF_CLASS_MEM_NV04 , -1 },
202 static const struct nvif_mclass
204 { NVIF_CLASS_MMU_GF100, -1 },
205 { NVIF_CLASS_MMU_NV50 , -1 },
206 { NVIF_CLASS_MMU_NV04 , -1 },
209 static const struct nvif_mclass
211 { NVIF_CLASS_VMM_GP100, -1 },
212 { NVIF_CLASS_VMM_GM200, -1 },
213 { NVIF_CLASS_VMM_GF100, -1 },
214 { NVIF_CLASS_VMM_NV50 , -1 },
215 { NVIF_CLASS_VMM_NV04 , -1 },
218 u64 device = nouveau_name(drm->dev);
221 snprintf(cli->name, sizeof(cli->name), "%s", sname);
223 mutex_init(&cli->mutex);
224 usif_client_init(cli);
226 INIT_WORK(&cli->work, nouveau_cli_work);
227 INIT_LIST_HEAD(&cli->worker);
228 mutex_init(&cli->lock);
230 if (cli == &drm->master) {
231 ret = nvif_driver_init(NULL, nouveau_config, nouveau_debug,
232 cli->name, device, &cli->base);
234 mutex_lock(&drm->master.lock);
235 ret = nvif_client_ctor(&drm->master.base, cli->name, device,
237 mutex_unlock(&drm->master.lock);
240 NV_PRINTK(err, cli, "Client allocation failed: %d\n", ret);
244 ret = nvif_device_ctor(&cli->base.object, "drmDevice", 0, NV_DEVICE,
245 &(struct nv_device_v0) {
248 }, sizeof(struct nv_device_v0),
251 NV_PRINTK(err, cli, "Device allocation failed: %d\n", ret);
255 ret = nvif_mclass(&cli->device.object, mmus);
257 NV_PRINTK(err, cli, "No supported MMU class\n");
261 ret = nvif_mmu_ctor(&cli->device.object, "drmMmu", mmus[ret].oclass,
264 NV_PRINTK(err, cli, "MMU allocation failed: %d\n", ret);
268 ret = nvif_mclass(&cli->mmu.object, vmms);
270 NV_PRINTK(err, cli, "No supported VMM class\n");
274 ret = nouveau_vmm_init(cli, vmms[ret].oclass, &cli->vmm);
276 NV_PRINTK(err, cli, "VMM allocation failed: %d\n", ret);
280 ret = nvif_mclass(&cli->mmu.object, mems);
282 NV_PRINTK(err, cli, "No supported MEM class\n");
286 cli->mem = &mems[ret];
290 nouveau_cli_fini(cli);
295 nouveau_accel_ce_fini(struct nouveau_drm *drm)
297 nouveau_channel_idle(drm->cechan);
298 nvif_object_dtor(&drm->ttm.copy);
299 nouveau_channel_del(&drm->cechan);
303 nouveau_accel_ce_init(struct nouveau_drm *drm)
305 struct nvif_device *device = &drm->client.device;
308 /* Allocate channel that has access to a (preferably async) copy
309 * engine, to use for TTM buffer moves.
311 if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) {
312 ret = nouveau_channel_new(drm, device,
313 nvif_fifo_runlist_ce(device), 0,
316 if (device->info.chipset >= 0xa3 &&
317 device->info.chipset != 0xaa &&
318 device->info.chipset != 0xac) {
319 /* Prior to Kepler, there's only a single runlist, so all
320 * engines can be accessed from any channel.
322 * We still want to use a separate channel though.
324 ret = nouveau_channel_new(drm, device, NvDmaFB, NvDmaTT, false,
329 NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
333 nouveau_accel_gr_fini(struct nouveau_drm *drm)
335 nouveau_channel_idle(drm->channel);
336 nvif_object_dtor(&drm->ntfy);
337 nvkm_gpuobj_del(&drm->notify);
338 nouveau_channel_del(&drm->channel);
342 nouveau_accel_gr_init(struct nouveau_drm *drm)
344 struct nvif_device *device = &drm->client.device;
348 if (device->info.family >= NV_DEVICE_INFO_V0_AMPERE)
351 /* Allocate channel that has access to the graphics engine. */
352 if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) {
353 arg0 = nvif_fifo_runlist(device, NV_DEVICE_HOST_RUNLIST_ENGINES_GR);
360 ret = nouveau_channel_new(drm, device, arg0, arg1, false,
363 NV_ERROR(drm, "failed to create kernel channel, %d\n", ret);
364 nouveau_accel_gr_fini(drm);
368 /* A SW class is used on pre-NV50 HW to assist with handling the
369 * synchronisation of page flips, as well as to implement fences
370 * on TNT/TNT2 HW that lacks any kind of support in host.
372 if (!drm->channel->nvsw.client && device->info.family < NV_DEVICE_INFO_V0_TESLA) {
373 ret = nvif_object_ctor(&drm->channel->user, "drmNvsw",
374 NVDRM_NVSW, nouveau_abi16_swclass(drm),
375 NULL, 0, &drm->channel->nvsw);
377 struct nvif_push *push = drm->channel->chan.push;
378 ret = PUSH_WAIT(push, 2);
380 PUSH_NVSQ(push, NV_SW, 0x0000, drm->channel->nvsw.handle);
384 NV_ERROR(drm, "failed to allocate sw class, %d\n", ret);
385 nouveau_accel_gr_fini(drm);
390 /* NvMemoryToMemoryFormat requires a notifier ctxdma for some reason,
391 * even if notification is never requested, so, allocate a ctxdma on
392 * any GPU where it's possible we'll end up using M2MF for BO moves.
394 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
395 ret = nvkm_gpuobj_new(nvxx_device(device), 32, 0, false, NULL,
398 NV_ERROR(drm, "failed to allocate notifier, %d\n", ret);
399 nouveau_accel_gr_fini(drm);
403 ret = nvif_object_ctor(&drm->channel->user, "drmM2mfNtfy",
404 NvNotify0, NV_DMA_IN_MEMORY,
405 &(struct nv_dma_v0) {
406 .target = NV_DMA_V0_TARGET_VRAM,
407 .access = NV_DMA_V0_ACCESS_RDWR,
408 .start = drm->notify->addr,
409 .limit = drm->notify->addr + 31
410 }, sizeof(struct nv_dma_v0),
413 nouveau_accel_gr_fini(drm);
420 nouveau_accel_fini(struct nouveau_drm *drm)
422 nouveau_accel_ce_fini(drm);
423 nouveau_accel_gr_fini(drm);
425 nouveau_fence(drm)->dtor(drm);
429 nouveau_accel_init(struct nouveau_drm *drm)
431 struct nvif_device *device = &drm->client.device;
432 struct nvif_sclass *sclass;
438 /* Initialise global support for channels, and synchronisation. */
439 ret = nouveau_channels_init(drm);
443 /*XXX: this is crap, but the fence/channel stuff is a little
444 * backwards in some places. this will be fixed.
446 ret = n = nvif_object_sclass_get(&device->object, &sclass);
450 for (ret = -ENOSYS, i = 0; i < n; i++) {
451 switch (sclass[i].oclass) {
452 case NV03_CHANNEL_DMA:
453 ret = nv04_fence_create(drm);
455 case NV10_CHANNEL_DMA:
456 ret = nv10_fence_create(drm);
458 case NV17_CHANNEL_DMA:
459 case NV40_CHANNEL_DMA:
460 ret = nv17_fence_create(drm);
462 case NV50_CHANNEL_GPFIFO:
463 ret = nv50_fence_create(drm);
465 case G82_CHANNEL_GPFIFO:
466 ret = nv84_fence_create(drm);
468 case FERMI_CHANNEL_GPFIFO:
469 case KEPLER_CHANNEL_GPFIFO_A:
470 case KEPLER_CHANNEL_GPFIFO_B:
471 case MAXWELL_CHANNEL_GPFIFO_A:
472 case PASCAL_CHANNEL_GPFIFO_A:
473 case VOLTA_CHANNEL_GPFIFO_A:
474 case TURING_CHANNEL_GPFIFO_A:
475 case AMPERE_CHANNEL_GPFIFO_B:
476 ret = nvc0_fence_create(drm);
483 nvif_object_sclass_put(&sclass);
485 NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret);
486 nouveau_accel_fini(drm);
490 /* Volta requires access to a doorbell register for kickoff. */
491 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_VOLTA) {
492 ret = nvif_user_ctor(device, "drmUsermode");
497 /* Allocate channels we need to support various functions. */
498 nouveau_accel_gr_init(drm);
499 nouveau_accel_ce_init(drm);
501 /* Initialise accelerated TTM buffer moves. */
502 nouveau_bo_move_init(drm);
505 static void __printf(2, 3)
506 nouveau_drm_errorf(struct nvif_object *object, const char *fmt, ...)
508 struct nouveau_drm *drm = container_of(object->parent, typeof(*drm), parent);
509 struct va_format vaf;
515 NV_ERROR(drm, "%pV", &vaf);
519 static void __printf(2, 3)
520 nouveau_drm_debugf(struct nvif_object *object, const char *fmt, ...)
522 struct nouveau_drm *drm = container_of(object->parent, typeof(*drm), parent);
523 struct va_format vaf;
529 NV_DEBUG(drm, "%pV", &vaf);
533 static const struct nvif_parent_func
535 .debugf = nouveau_drm_debugf,
536 .errorf = nouveau_drm_errorf,
540 nouveau_drm_device_init(struct drm_device *dev)
542 struct nouveau_drm *drm;
545 if (!(drm = kzalloc(sizeof(*drm), GFP_KERNEL)))
547 dev->dev_private = drm;
550 nvif_parent_ctor(&nouveau_parent, &drm->parent);
551 drm->master.base.object.parent = &drm->parent;
553 ret = nouveau_cli_init(drm, "DRM-master", &drm->master);
557 ret = nouveau_cli_init(drm, "DRM", &drm->client);
561 nvxx_client(&drm->client.base)->debug =
562 nvkm_dbgopt(nouveau_debug, "DRM");
564 INIT_LIST_HEAD(&drm->clients);
565 mutex_init(&drm->clients_lock);
566 spin_lock_init(&drm->tile.lock);
568 /* workaround an odd issue on nvc1 by disabling the device's
569 * nosnoop capability. hopefully won't cause issues until a
570 * better fix is found - assuming there is one...
572 if (drm->client.device.info.chipset == 0xc1)
573 nvif_mask(&drm->client.device.object, 0x00088080, 0x00000800, 0x00000000);
575 nouveau_vga_init(drm);
577 ret = nouveau_ttm_init(drm);
581 ret = nouveau_bios_init(dev);
585 nouveau_accel_init(drm);
587 ret = nouveau_display_create(dev);
591 if (dev->mode_config.num_crtc) {
592 ret = nouveau_display_init(dev, false, false);
597 nouveau_debugfs_init(drm);
598 nouveau_hwmon_init(dev);
599 nouveau_svm_init(drm);
600 nouveau_dmem_init(drm);
601 nouveau_fbcon_init(dev);
602 nouveau_led_init(dev);
604 if (nouveau_pmops_runtime()) {
605 pm_runtime_use_autosuspend(dev->dev);
606 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
607 pm_runtime_set_active(dev->dev);
608 pm_runtime_allow(dev->dev);
609 pm_runtime_mark_last_busy(dev->dev);
610 pm_runtime_put(dev->dev);
616 nouveau_display_destroy(dev);
618 nouveau_accel_fini(drm);
619 nouveau_bios_takedown(dev);
621 nouveau_ttm_fini(drm);
623 nouveau_vga_fini(drm);
624 nouveau_cli_fini(&drm->client);
626 nouveau_cli_fini(&drm->master);
628 nvif_parent_dtor(&drm->parent);
634 nouveau_drm_device_fini(struct drm_device *dev)
636 struct nouveau_cli *cli, *temp_cli;
637 struct nouveau_drm *drm = nouveau_drm(dev);
639 if (nouveau_pmops_runtime()) {
640 pm_runtime_get_sync(dev->dev);
641 pm_runtime_forbid(dev->dev);
644 nouveau_led_fini(dev);
645 nouveau_fbcon_fini(dev);
646 nouveau_dmem_fini(drm);
647 nouveau_svm_fini(drm);
648 nouveau_hwmon_fini(dev);
649 nouveau_debugfs_fini(drm);
651 if (dev->mode_config.num_crtc)
652 nouveau_display_fini(dev, false, false);
653 nouveau_display_destroy(dev);
655 nouveau_accel_fini(drm);
656 nouveau_bios_takedown(dev);
658 nouveau_ttm_fini(drm);
659 nouveau_vga_fini(drm);
662 * There may be existing clients from as-yet unclosed files. For now,
663 * clean them up here rather than deferring until the file is closed,
664 * but this likely not correct if we want to support hot-unplugging
667 mutex_lock(&drm->clients_lock);
668 list_for_each_entry_safe(cli, temp_cli, &drm->clients, head) {
669 list_del(&cli->head);
670 mutex_lock(&cli->mutex);
672 nouveau_abi16_fini(cli->abi16);
673 mutex_unlock(&cli->mutex);
674 nouveau_cli_fini(cli);
677 mutex_unlock(&drm->clients_lock);
679 nouveau_cli_fini(&drm->client);
680 nouveau_cli_fini(&drm->master);
681 nvif_parent_dtor(&drm->parent);
682 mutex_destroy(&drm->clients_lock);
687 * On some Intel PCIe bridge controllers doing a
688 * D0 -> D3hot -> D3cold -> D0 sequence causes Nvidia GPUs to not reappear.
689 * Skipping the intermediate D3hot step seems to make it work again. This is
690 * probably caused by not meeting the expectation the involved AML code has
691 * when the GPU is put into D3hot state before invoking it.
693 * This leads to various manifestations of this issue:
694 * - AML code execution to power on the GPU hits an infinite loop (as the
695 * code waits on device memory to change).
696 * - kernel crashes, as all PCI reads return -1, which most code isn't able
697 * to handle well enough.
699 * In all cases dmesg will contain at least one line like this:
700 * 'nouveau 0000:01:00.0: Refused to change power state, currently in D3'
701 * followed by a lot of nouveau timeouts.
703 * In the \_SB.PCI0.PEG0.PG00._OFF code deeper down writes bit 0x80 to the not
704 * documented PCI config space register 0x248 of the Intel PCIe bridge
705 * controller (0x1901) in order to change the state of the PCIe link between
706 * the PCIe port and the GPU. There are alternative code paths using other
707 * registers, which seem to work fine (executed pre Windows 8):
708 * - 0xbc bit 0x20 (publicly available documentation claims 'reserved')
709 * - 0xb0 bit 0x10 (link disable)
710 * Changing the conditions inside the firmware by poking into the relevant
711 * addresses does resolve the issue, but it seemed to be ACPI private memory
712 * and not any device accessible memory at all, so there is no portable way of
713 * changing the conditions.
714 * On a XPS 9560 that means bits [0,3] on \CPEX need to be cleared.
716 * The only systems where this behavior can be seen are hybrid graphics laptops
717 * with a secondary Nvidia Maxwell, Pascal or Turing GPU. It's unclear whether
718 * this issue only occurs in combination with listed Intel PCIe bridge
719 * controllers and the mentioned GPUs or other devices as well.
721 * documentation on the PCIe bridge controller can be found in the
722 * "7th Generation Intel® Processor Families for H Platforms Datasheet Volume 2"
723 * Section "12 PCI Express* Controller (x16) Registers"
726 static void quirk_broken_nv_runpm(struct pci_dev *pdev)
728 struct drm_device *dev = pci_get_drvdata(pdev);
729 struct nouveau_drm *drm = nouveau_drm(dev);
730 struct pci_dev *bridge = pci_upstream_bridge(pdev);
732 if (!bridge || bridge->vendor != PCI_VENDOR_ID_INTEL)
735 switch (bridge->device) {
737 drm->old_pm_cap = pdev->pm_cap;
739 NV_INFO(drm, "Disabling PCI power management to avoid bug\n");
744 static int nouveau_drm_probe(struct pci_dev *pdev,
745 const struct pci_device_id *pent)
747 struct nvkm_device *device;
748 struct drm_device *drm_dev;
751 if (vga_switcheroo_client_probe_defer(pdev))
752 return -EPROBE_DEFER;
754 /* We need to check that the chipset is supported before booting
755 * fbdev off the hardware, as there's no way to put it back.
757 ret = nvkm_device_pci_new(pdev, nouveau_config, "error",
758 true, false, 0, &device);
762 nvkm_device_del(&device);
764 /* Remove conflicting drivers (vesafb, efifb etc). */
765 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &driver_pci);
769 ret = nvkm_device_pci_new(pdev, nouveau_config, nouveau_debug,
770 true, true, ~0ULL, &device);
774 pci_set_master(pdev);
777 driver_pci.driver_features |= DRIVER_ATOMIC;
779 drm_dev = drm_dev_alloc(&driver_pci, &pdev->dev);
780 if (IS_ERR(drm_dev)) {
781 ret = PTR_ERR(drm_dev);
785 ret = pci_enable_device(pdev);
789 pci_set_drvdata(pdev, drm_dev);
791 ret = nouveau_drm_device_init(drm_dev);
795 ret = drm_dev_register(drm_dev, pent->driver_data);
797 goto fail_drm_dev_init;
799 quirk_broken_nv_runpm(pdev);
803 nouveau_drm_device_fini(drm_dev);
805 pci_disable_device(pdev);
807 drm_dev_put(drm_dev);
809 nvkm_device_del(&device);
814 nouveau_drm_device_remove(struct drm_device *dev)
816 struct nouveau_drm *drm = nouveau_drm(dev);
817 struct nvkm_client *client;
818 struct nvkm_device *device;
822 client = nvxx_client(&drm->client.base);
823 device = nvkm_device_find(client->device);
825 nouveau_drm_device_fini(dev);
827 nvkm_device_del(&device);
831 nouveau_drm_remove(struct pci_dev *pdev)
833 struct drm_device *dev = pci_get_drvdata(pdev);
834 struct nouveau_drm *drm = nouveau_drm(dev);
836 /* revert our workaround */
838 pdev->pm_cap = drm->old_pm_cap;
839 nouveau_drm_device_remove(dev);
840 pci_disable_device(pdev);
844 nouveau_do_suspend(struct drm_device *dev, bool runtime)
846 struct nouveau_drm *drm = nouveau_drm(dev);
847 struct ttm_resource_manager *man;
850 nouveau_svm_suspend(drm);
851 nouveau_dmem_suspend(drm);
852 nouveau_led_suspend(dev);
854 if (dev->mode_config.num_crtc) {
855 NV_DEBUG(drm, "suspending console...\n");
856 nouveau_fbcon_set_suspend(dev, 1);
857 NV_DEBUG(drm, "suspending display...\n");
858 ret = nouveau_display_suspend(dev, runtime);
863 NV_DEBUG(drm, "evicting buffers...\n");
865 man = ttm_manager_type(&drm->ttm.bdev, TTM_PL_VRAM);
866 ttm_resource_manager_evict_all(&drm->ttm.bdev, man);
868 NV_DEBUG(drm, "waiting for kernel channels to go idle...\n");
870 ret = nouveau_channel_idle(drm->cechan);
876 ret = nouveau_channel_idle(drm->channel);
881 NV_DEBUG(drm, "suspending fence...\n");
882 if (drm->fence && nouveau_fence(drm)->suspend) {
883 if (!nouveau_fence(drm)->suspend(drm)) {
889 NV_DEBUG(drm, "suspending object tree...\n");
890 ret = nvif_client_suspend(&drm->master.base);
897 if (drm->fence && nouveau_fence(drm)->resume)
898 nouveau_fence(drm)->resume(drm);
901 if (dev->mode_config.num_crtc) {
902 NV_DEBUG(drm, "resuming display...\n");
903 nouveau_display_resume(dev, runtime);
909 nouveau_do_resume(struct drm_device *dev, bool runtime)
912 struct nouveau_drm *drm = nouveau_drm(dev);
914 NV_DEBUG(drm, "resuming object tree...\n");
915 ret = nvif_client_resume(&drm->master.base);
917 NV_ERROR(drm, "Client resume failed with error: %d\n", ret);
921 NV_DEBUG(drm, "resuming fence...\n");
922 if (drm->fence && nouveau_fence(drm)->resume)
923 nouveau_fence(drm)->resume(drm);
925 nouveau_run_vbios_init(dev);
927 if (dev->mode_config.num_crtc) {
928 NV_DEBUG(drm, "resuming display...\n");
929 nouveau_display_resume(dev, runtime);
930 NV_DEBUG(drm, "resuming console...\n");
931 nouveau_fbcon_set_suspend(dev, 0);
934 nouveau_led_resume(dev);
935 nouveau_dmem_resume(drm);
936 nouveau_svm_resume(drm);
941 nouveau_pmops_suspend(struct device *dev)
943 struct pci_dev *pdev = to_pci_dev(dev);
944 struct drm_device *drm_dev = pci_get_drvdata(pdev);
947 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
948 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
951 ret = nouveau_do_suspend(drm_dev, false);
955 pci_save_state(pdev);
956 pci_disable_device(pdev);
957 pci_set_power_state(pdev, PCI_D3hot);
963 nouveau_pmops_resume(struct device *dev)
965 struct pci_dev *pdev = to_pci_dev(dev);
966 struct drm_device *drm_dev = pci_get_drvdata(pdev);
969 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
970 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
973 pci_set_power_state(pdev, PCI_D0);
974 pci_restore_state(pdev);
975 ret = pci_enable_device(pdev);
978 pci_set_master(pdev);
980 ret = nouveau_do_resume(drm_dev, false);
982 /* Monitors may have been connected / disconnected during suspend */
983 nouveau_display_hpd_resume(drm_dev);
989 nouveau_pmops_freeze(struct device *dev)
991 struct pci_dev *pdev = to_pci_dev(dev);
992 struct drm_device *drm_dev = pci_get_drvdata(pdev);
993 return nouveau_do_suspend(drm_dev, false);
997 nouveau_pmops_thaw(struct device *dev)
999 struct pci_dev *pdev = to_pci_dev(dev);
1000 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1001 return nouveau_do_resume(drm_dev, false);
1005 nouveau_pmops_runtime(void)
1007 if (nouveau_runtime_pm == -1)
1008 return nouveau_is_optimus() || nouveau_is_v1_dsm();
1009 return nouveau_runtime_pm == 1;
1013 nouveau_pmops_runtime_suspend(struct device *dev)
1015 struct pci_dev *pdev = to_pci_dev(dev);
1016 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1019 if (!nouveau_pmops_runtime()) {
1020 pm_runtime_forbid(dev);
1024 nouveau_switcheroo_optimus_dsm();
1025 ret = nouveau_do_suspend(drm_dev, true);
1026 pci_save_state(pdev);
1027 pci_disable_device(pdev);
1028 pci_ignore_hotplug(pdev);
1029 pci_set_power_state(pdev, PCI_D3cold);
1030 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
1035 nouveau_pmops_runtime_resume(struct device *dev)
1037 struct pci_dev *pdev = to_pci_dev(dev);
1038 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1039 struct nouveau_drm *drm = nouveau_drm(drm_dev);
1040 struct nvif_device *device = &nouveau_drm(drm_dev)->client.device;
1043 if (!nouveau_pmops_runtime()) {
1044 pm_runtime_forbid(dev);
1048 pci_set_power_state(pdev, PCI_D0);
1049 pci_restore_state(pdev);
1050 ret = pci_enable_device(pdev);
1053 pci_set_master(pdev);
1055 ret = nouveau_do_resume(drm_dev, true);
1057 NV_ERROR(drm, "resume failed with: %d\n", ret);
1062 nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25));
1063 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
1065 /* Monitors may have been connected / disconnected during suspend */
1066 nouveau_display_hpd_resume(drm_dev);
1072 nouveau_pmops_runtime_idle(struct device *dev)
1074 if (!nouveau_pmops_runtime()) {
1075 pm_runtime_forbid(dev);
1079 pm_runtime_mark_last_busy(dev);
1080 pm_runtime_autosuspend(dev);
1081 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
1086 nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv)
1088 struct nouveau_drm *drm = nouveau_drm(dev);
1089 struct nouveau_cli *cli;
1090 char name[32], tmpname[TASK_COMM_LEN];
1093 /* need to bring up power immediately if opening device */
1094 ret = pm_runtime_get_sync(dev->dev);
1095 if (ret < 0 && ret != -EACCES) {
1096 pm_runtime_put_autosuspend(dev->dev);
1100 get_task_comm(tmpname, current);
1101 snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid));
1103 if (!(cli = kzalloc(sizeof(*cli), GFP_KERNEL))) {
1108 ret = nouveau_cli_init(drm, name, cli);
1112 fpriv->driver_priv = cli;
1114 mutex_lock(&drm->clients_lock);
1115 list_add(&cli->head, &drm->clients);
1116 mutex_unlock(&drm->clients_lock);
1120 nouveau_cli_fini(cli);
1124 pm_runtime_mark_last_busy(dev->dev);
1125 pm_runtime_put_autosuspend(dev->dev);
1130 nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv)
1132 struct nouveau_cli *cli = nouveau_cli(fpriv);
1133 struct nouveau_drm *drm = nouveau_drm(dev);
1137 * The device is gone, and as it currently stands all clients are
1138 * cleaned up in the removal codepath. In the future this may change
1139 * so that we can support hot-unplugging, but for now we immediately
1140 * return to avoid a double-free situation.
1142 if (!drm_dev_enter(dev, &dev_index))
1145 pm_runtime_get_sync(dev->dev);
1147 mutex_lock(&cli->mutex);
1149 nouveau_abi16_fini(cli->abi16);
1150 mutex_unlock(&cli->mutex);
1152 mutex_lock(&drm->clients_lock);
1153 list_del(&cli->head);
1154 mutex_unlock(&drm->clients_lock);
1156 nouveau_cli_fini(cli);
1158 pm_runtime_mark_last_busy(dev->dev);
1159 pm_runtime_put_autosuspend(dev->dev);
1160 drm_dev_exit(dev_index);
1163 static const struct drm_ioctl_desc
1164 nouveau_ioctls[] = {
1165 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_RENDER_ALLOW),
1166 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1167 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_RENDER_ALLOW),
1168 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_RENDER_ALLOW),
1169 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_RENDER_ALLOW),
1170 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_RENDER_ALLOW),
1171 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_RENDER_ALLOW),
1172 DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_INIT, nouveau_svmm_init, DRM_RENDER_ALLOW),
1173 DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_BIND, nouveau_svmm_bind, DRM_RENDER_ALLOW),
1174 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_RENDER_ALLOW),
1175 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_RENDER_ALLOW),
1176 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_RENDER_ALLOW),
1177 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_RENDER_ALLOW),
1178 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_RENDER_ALLOW),
1182 nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1184 struct drm_file *filp = file->private_data;
1185 struct drm_device *dev = filp->minor->dev;
1188 ret = pm_runtime_get_sync(dev->dev);
1189 if (ret < 0 && ret != -EACCES) {
1190 pm_runtime_put_autosuspend(dev->dev);
1194 switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) {
1195 case DRM_NOUVEAU_NVIF:
1196 ret = usif_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd));
1199 ret = drm_ioctl(file, cmd, arg);
1203 pm_runtime_mark_last_busy(dev->dev);
1204 pm_runtime_put_autosuspend(dev->dev);
1208 static const struct file_operations
1209 nouveau_driver_fops = {
1210 .owner = THIS_MODULE,
1212 .release = drm_release,
1213 .unlocked_ioctl = nouveau_drm_ioctl,
1214 .mmap = drm_gem_mmap,
1217 #if defined(CONFIG_COMPAT)
1218 .compat_ioctl = nouveau_compat_ioctl,
1220 .llseek = noop_llseek,
1223 static struct drm_driver
1226 DRIVER_GEM | DRIVER_MODESET | DRIVER_RENDER
1227 #if defined(CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT)
1228 | DRIVER_KMS_LEGACY_CONTEXT
1232 .open = nouveau_drm_open,
1233 .postclose = nouveau_drm_postclose,
1234 .lastclose = nouveau_vga_lastclose,
1236 #if defined(CONFIG_DEBUG_FS)
1237 .debugfs_init = nouveau_drm_debugfs_init,
1240 .ioctls = nouveau_ioctls,
1241 .num_ioctls = ARRAY_SIZE(nouveau_ioctls),
1242 .fops = &nouveau_driver_fops,
1244 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1245 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1246 .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table,
1247 .gem_prime_mmap = drm_gem_prime_mmap,
1249 .dumb_create = nouveau_display_dumb_create,
1250 .dumb_map_offset = drm_gem_ttm_dumb_map_offset,
1252 .name = DRIVER_NAME,
1253 .desc = DRIVER_DESC,
1255 .date = GIT_REVISION,
1257 .date = DRIVER_DATE,
1259 .major = DRIVER_MAJOR,
1260 .minor = DRIVER_MINOR,
1261 .patchlevel = DRIVER_PATCHLEVEL,
1264 static struct pci_device_id
1265 nouveau_drm_pci_table[] = {
1267 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
1268 .class = PCI_BASE_CLASS_DISPLAY << 16,
1269 .class_mask = 0xff << 16,
1272 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
1273 .class = PCI_BASE_CLASS_DISPLAY << 16,
1274 .class_mask = 0xff << 16,
1279 static void nouveau_display_options(void)
1281 DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n");
1283 DRM_DEBUG_DRIVER("... tv_disable : %d\n", nouveau_tv_disable);
1284 DRM_DEBUG_DRIVER("... ignorelid : %d\n", nouveau_ignorelid);
1285 DRM_DEBUG_DRIVER("... duallink : %d\n", nouveau_duallink);
1286 DRM_DEBUG_DRIVER("... nofbaccel : %d\n", nouveau_nofbaccel);
1287 DRM_DEBUG_DRIVER("... config : %s\n", nouveau_config);
1288 DRM_DEBUG_DRIVER("... debug : %s\n", nouveau_debug);
1289 DRM_DEBUG_DRIVER("... noaccel : %d\n", nouveau_noaccel);
1290 DRM_DEBUG_DRIVER("... modeset : %d\n", nouveau_modeset);
1291 DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm);
1292 DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf);
1293 DRM_DEBUG_DRIVER("... hdmimhz : %d\n", nouveau_hdmimhz);
1296 static const struct dev_pm_ops nouveau_pm_ops = {
1297 .suspend = nouveau_pmops_suspend,
1298 .resume = nouveau_pmops_resume,
1299 .freeze = nouveau_pmops_freeze,
1300 .thaw = nouveau_pmops_thaw,
1301 .poweroff = nouveau_pmops_freeze,
1302 .restore = nouveau_pmops_resume,
1303 .runtime_suspend = nouveau_pmops_runtime_suspend,
1304 .runtime_resume = nouveau_pmops_runtime_resume,
1305 .runtime_idle = nouveau_pmops_runtime_idle,
1308 static struct pci_driver
1309 nouveau_drm_pci_driver = {
1311 .id_table = nouveau_drm_pci_table,
1312 .probe = nouveau_drm_probe,
1313 .remove = nouveau_drm_remove,
1314 .driver.pm = &nouveau_pm_ops,
1318 nouveau_platform_device_create(const struct nvkm_device_tegra_func *func,
1319 struct platform_device *pdev,
1320 struct nvkm_device **pdevice)
1322 struct drm_device *drm;
1325 err = nvkm_device_tegra_new(func, pdev, nouveau_config, nouveau_debug,
1326 true, true, ~0ULL, pdevice);
1330 drm = drm_dev_alloc(&driver_platform, &pdev->dev);
1336 err = nouveau_drm_device_init(drm);
1340 platform_set_drvdata(pdev, drm);
1347 nvkm_device_del(pdevice);
1349 return ERR_PTR(err);
1353 nouveau_drm_init(void)
1355 driver_pci = driver_stub;
1356 driver_platform = driver_stub;
1358 nouveau_display_options();
1360 if (nouveau_modeset == -1) {
1361 if (drm_firmware_drivers_only())
1362 nouveau_modeset = 0;
1365 if (!nouveau_modeset)
1368 #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1369 platform_driver_register(&nouveau_platform_driver);
1372 nouveau_register_dsm_handler();
1373 nouveau_backlight_ctor();
1376 return pci_register_driver(&nouveau_drm_pci_driver);
1383 nouveau_drm_exit(void)
1385 if (!nouveau_modeset)
1389 pci_unregister_driver(&nouveau_drm_pci_driver);
1391 nouveau_backlight_dtor();
1392 nouveau_unregister_dsm_handler();
1394 #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1395 platform_driver_unregister(&nouveau_platform_driver);
1397 if (IS_ENABLED(CONFIG_DRM_NOUVEAU_SVM))
1398 mmu_notifier_synchronize();
1401 module_init(nouveau_drm_init);
1402 module_exit(nouveau_drm_exit);
1404 MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table);
1405 MODULE_AUTHOR(DRIVER_AUTHOR);
1406 MODULE_DESCRIPTION(DRIVER_DESC);
1407 MODULE_LICENSE("GPL and additional rights");