1 #ifndef __NVIF_CL0002_H__
2 #define __NVIF_CL0002_H__
6 #define NV_DMA_V0_TARGET_VM 0x00
7 #define NV_DMA_V0_TARGET_VRAM 0x01
8 #define NV_DMA_V0_TARGET_PCI 0x02
9 #define NV_DMA_V0_TARGET_PCI_US 0x03
10 #define NV_DMA_V0_TARGET_AGP 0x04
12 #define NV_DMA_V0_ACCESS_VM 0x00
13 #define NV_DMA_V0_ACCESS_RD 0x01
14 #define NV_DMA_V0_ACCESS_WR 0x02
15 #define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR)
20 /* ... chipset-specific class data */
25 #define NV50_DMA_V0_PRIV_VM 0x00
26 #define NV50_DMA_V0_PRIV_US 0x01
27 #define NV50_DMA_V0_PRIV__S 0x02
29 #define NV50_DMA_V0_PART_VM 0x00
30 #define NV50_DMA_V0_PART_256 0x01
31 #define NV50_DMA_V0_PART_1KB 0x02
33 #define NV50_DMA_V0_COMP_NONE 0x00
34 #define NV50_DMA_V0_COMP_1 0x01
35 #define NV50_DMA_V0_COMP_2 0x02
36 #define NV50_DMA_V0_COMP_VM 0x03
38 #define NV50_DMA_V0_KIND_PITCH 0x00
39 #define NV50_DMA_V0_KIND_VM 0x7f
46 #define GF100_DMA_V0_PRIV_VM 0x00
47 #define GF100_DMA_V0_PRIV_US 0x01
48 #define GF100_DMA_V0_PRIV__S 0x02
50 #define GF100_DMA_V0_KIND_PITCH 0x00
51 #define GF100_DMA_V0_KIND_VM 0xff
58 #define GF119_DMA_V0_PAGE_LP 0x00
59 #define GF119_DMA_V0_PAGE_SP 0x01
61 #define GF119_DMA_V0_KIND_PITCH 0x00
62 #define GF119_DMA_V0_KIND_VM 0xff