drivers/gpu/drm/nouveau/dispnv50/disp.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "disp.h"
  25 #include "atom.h"
  26 #include "core.h"
  27 #include "head.h"
  28 #include "wndw.h"
  29
  30 #include <linux/dma-mapping.h>
  31 #include <linux/hdmi.h>
  32
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_dp_helper.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_plane_helper.h>
  39 #include <drm/drm_edid.h>
  40
  41 #include <nvif/class.h>
  42 #include <nvif/cl0002.h>
  43 #include <nvif/cl5070.h>
  44 #include <nvif/cl507d.h>
  45 #include <nvif/event.h>
  46
  47 #include "nouveau_drv.h"
  48 #include "nouveau_dma.h"
  49 #include "nouveau_gem.h"
  50 #include "nouveau_connector.h"
  51 #include "nouveau_encoder.h"
  52 #include "nouveau_fence.h"
  53 #include "nouveau_fbcon.h"
  54
  55 #include <subdev/bios/dp.h>
  56
  57 /******************************************************************************
  58  * Atomic state
  59  *****************************************************************************/
  60
  61 struct nv50_outp_atom {
  62         struct list_head head;
  63
  64         struct drm_encoder *encoder;
  65         bool flush_disable;
  66
  67         union nv50_outp_atom_mask {
  68                 struct {
  69                         bool ctrl:1;
  70                 };
  71                 u8 mask;
  72         } set, clr;
  73 };
  74
  75 /******************************************************************************
  76  * EVO channel
  77  *****************************************************************************/
  78
  79 static int
  80 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
  81                  const s32 *oclass, u8 head, void *data, u32 size,
  82                  struct nv50_chan *chan)
  83 {
  84         struct nvif_sclass *sclass;
  85         int ret, i, n;
  86
  87         chan->device = device;
  88
  89         ret = n = nvif_object_sclass_get(disp, &sclass);
  90         if (ret < 0)
  91                 return ret;
  92
  93         while (oclass[0]) {
  94                 for (i = 0; i < n; i++) {
  95                         if (sclass[i].oclass == oclass[0]) {
  96                                 ret = nvif_object_init(disp, 0, oclass[0],
  97                                                        data, size, &chan->user);
  98                                 if (ret == 0)
  99                                         nvif_object_map(&chan->user, NULL, 0);
 100                                 nvif_object_sclass_put(&sclass);
 101                                 return ret;
 102                         }
 103                 }
 104                 oclass++;
 105         }
 106
 107         nvif_object_sclass_put(&sclass);
 108         return -ENOSYS;
 109 }
 110
 111 static void
 112 nv50_chan_destroy(struct nv50_chan *chan)
 113 {
 114         nvif_object_fini(&chan->user);
 115 }
 116
 117 /******************************************************************************
 118  * DMA EVO channel
 119  *****************************************************************************/
 120
 121 void
 122 nv50_dmac_destroy(struct nv50_dmac *dmac)
 123 {
 124         nvif_object_fini(&dmac->vram);
 125         nvif_object_fini(&dmac->sync);
 126
 127         nv50_chan_destroy(&dmac->base);
 128
 129         nvif_mem_fini(&dmac->push);
 130 }
 131
 132 int
 133 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
 134                  const s32 *oclass, u8 head, void *data, u32 size, s64 syncbuf,
 135                  struct nv50_dmac *dmac)
 136 {
 137         struct nouveau_cli *cli = (void *)device->object.client;
 138         struct nv50_disp_core_channel_dma_v0 *args = data;
 139         u8 type = NVIF_MEM_COHERENT;
 140         int ret;
 141
 142         mutex_init(&dmac->lock);
 143
 144         /* Pascal added support for 47-bit physical addresses, but some
 145          * parts of EVO still only accept 40-bit PAs.
 146          *
 147          * To avoid issues on systems with large amounts of RAM, and on
 148          * systems where an IOMMU maps pages at a high address, we need
 149          * to allocate push buffers in VRAM instead.
 150          *
 151          * This appears to match NVIDIA's behaviour on Pascal.
 152          */
 153         if (device->info.family == NV_DEVICE_INFO_V0_PASCAL)
 154                 type |= NVIF_MEM_VRAM;
 155
 156         ret = nvif_mem_init_map(&cli->mmu, type, 0x1000, &dmac->push);
 157         if (ret)
 158                 return ret;
 159
 160         dmac->ptr = dmac->push.object.map.ptr;
 161
 162         args->pushbuf = nvif_handle(&dmac->push.object);
 163
 164         ret = nv50_chan_create(device, disp, oclass, head, data, size,
 165                                &dmac->base);
 166         if (ret)
 167                 return ret;
 168
 169         if (syncbuf < 0)
 170                 return 0;
 171
 172         ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
 173                                &(struct nv_dma_v0) {
 174                                         .target = NV_DMA_V0_TARGET_VRAM,
 175                                         .access = NV_DMA_V0_ACCESS_RDWR,
 176                                         .start = syncbuf + 0x0000,
 177                                         .limit = syncbuf + 0x0fff,
 178                                }, sizeof(struct nv_dma_v0),
 179                                &dmac->sync);
 180         if (ret)
 181                 return ret;
 182
 183         ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
 184                                &(struct nv_dma_v0) {
 185                                         .target = NV_DMA_V0_TARGET_VRAM,
 186                                         .access = NV_DMA_V0_ACCESS_RDWR,
 187                                         .start = 0,
 188                                         .limit = device->info.ram_user - 1,
 189                                }, sizeof(struct nv_dma_v0),
 190                                &dmac->vram);
 191         if (ret)
 192                 return ret;
 193
 194         return ret;
 195 }
 196
 197 /******************************************************************************
 198  * EVO channel helpers
 199  *****************************************************************************/
 200 static void
 201 evo_flush(struct nv50_dmac *dmac)
 202 {
 203         /* Push buffer fetches are not coherent with BAR1, we need to ensure
 204          * writes have been flushed right through to VRAM before writing PUT.
 205          */
 206         if (dmac->push.type & NVIF_MEM_VRAM) {
 207                 struct nvif_device *device = dmac->base.device;
 208                 nvif_wr32(&device->object, 0x070000, 0x00000001);
 209                 nvif_msec(device, 2000,
 210                         if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
 211                                 break;
 212                 );
 213         }
 214 }
 215
 216 u32 *
 217 evo_wait(struct nv50_dmac *evoc, int nr)
 218 {
 219         struct nv50_dmac *dmac = evoc;
 220         struct nvif_device *device = dmac->base.device;
 221         u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
 222
 223         mutex_lock(&dmac->lock);
 224         if (put + nr >= (PAGE_SIZE / 4) - 8) {
 225                 dmac->ptr[put] = 0x20000000;
 226                 evo_flush(dmac);
 227
 228                 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
 229                 if (nvif_msec(device, 2000,
 230                         if (!nvif_rd32(&dmac->base.user, 0x0004))
 231                                 break;
 232                 ) < 0) {
 233                         mutex_unlock(&dmac->lock);
 234                         pr_err("nouveau: evo channel stalled\n");
 235                         return NULL;
 236                 }
 237
 238                 put = 0;
 239         }
 240
 241         return dmac->ptr + put;
 242 }
 243
 244 void
 245 evo_kick(u32 *push, struct nv50_dmac *evoc)
 246 {
 247         struct nv50_dmac *dmac = evoc;
 248
 249         evo_flush(dmac);
 250
 251         nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
 252         mutex_unlock(&dmac->lock);
 253 }
 254
 255 /******************************************************************************
 256  * Output path helpers
 257  *****************************************************************************/
 258 static void
 259 nv50_outp_release(struct nouveau_encoder *nv_encoder)
 260 {
 261         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
 262         struct {
 263                 struct nv50_disp_mthd_v1 base;
 264         } args = {
 265                 .base.version = 1,
 266                 .base.method = NV50_DISP_MTHD_V1_RELEASE,
 267                 .base.hasht  = nv_encoder->dcb->hasht,
 268                 .base.hashm  = nv_encoder->dcb->hashm,
 269         };
 270
 271         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 272         nv_encoder->or = -1;
 273         nv_encoder->link = 0;
 274 }
 275
 276 static int
 277 nv50_outp_acquire(struct nouveau_encoder *nv_encoder)
 278 {
 279         struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
 280         struct nv50_disp *disp = nv50_disp(drm->dev);
 281         struct {
 282                 struct nv50_disp_mthd_v1 base;
 283                 struct nv50_disp_acquire_v0 info;
 284         } args = {
 285                 .base.version = 1,
 286                 .base.method = NV50_DISP_MTHD_V1_ACQUIRE,
 287                 .base.hasht  = nv_encoder->dcb->hasht,
 288                 .base.hashm  = nv_encoder->dcb->hashm,
 289         };
 290         int ret;
 291
 292         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 293         if (ret) {
 294                 NV_ERROR(drm, "error acquiring output path: %d\n", ret);
 295                 return ret;
 296         }
 297
 298         nv_encoder->or = args.info.or;
 299         nv_encoder->link = args.info.link;
 300         return 0;
 301 }
 302
 303 static int
 304 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
 305                             struct drm_crtc_state *crtc_state,
 306                             struct drm_connector_state *conn_state,
 307                             struct drm_display_mode *native_mode)
 308 {
 309         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
 310         struct drm_display_mode *mode = &crtc_state->mode;
 311         struct drm_connector *connector = conn_state->connector;
 312         struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
 313         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 314
 315         NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
 316         asyc->scaler.full = false;
 317         if (!native_mode)
 318                 return 0;
 319
 320         if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
 321                 switch (connector->connector_type) {
 322                 case DRM_MODE_CONNECTOR_LVDS:
 323                 case DRM_MODE_CONNECTOR_eDP:
 324                         /* Force use of scaler for non-EDID modes. */
 325                         if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
 326                                 break;
 327                         mode = native_mode;
 328                         asyc->scaler.full = true;
 329                         break;
 330                 default:
 331                         break;
 332                 }
 333         } else {
 334                 mode = native_mode;
 335         }
 336
 337         if (!drm_mode_equal(adjusted_mode, mode)) {
 338                 drm_mode_copy(adjusted_mode, mode);
 339                 crtc_state->mode_changed = true;
 340         }
 341
 342         return 0;
 343 }
 344
 345 static int
 346 nv50_outp_atomic_check(struct drm_encoder *encoder,
 347                        struct drm_crtc_state *crtc_state,
 348                        struct drm_connector_state *conn_state)
 349 {
 350         struct nouveau_connector *nv_connector =
 351                 nouveau_connector(conn_state->connector);
 352         return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 353                                            nv_connector->native_mode);
 354 }
 355
 356 /******************************************************************************
 357  * DAC
 358  *****************************************************************************/
 359 static void
 360 nv50_dac_disable(struct drm_encoder *encoder)
 361 {
 362         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 363         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 364         if (nv_encoder->crtc)
 365                 core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL);
 366         nv_encoder->crtc = NULL;
 367         nv50_outp_release(nv_encoder);
 368 }
 369
 370 static void
 371 nv50_dac_enable(struct drm_encoder *encoder)
 372 {
 373         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 374         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 375         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
 376         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 377
 378         nv50_outp_acquire(nv_encoder);
 379
 380         core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh);
 381         asyh->or.depth = 0;
 382
 383         nv_encoder->crtc = encoder->crtc;
 384 }
 385
 386 static enum drm_connector_status
 387 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 388 {
 389         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 390         struct nv50_disp *disp = nv50_disp(encoder->dev);
 391         struct {
 392                 struct nv50_disp_mthd_v1 base;
 393                 struct nv50_disp_dac_load_v0 load;
 394         } args = {
 395                 .base.version = 1,
 396                 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
 397                 .base.hasht  = nv_encoder->dcb->hasht,
 398                 .base.hashm  = nv_encoder->dcb->hashm,
 399         };
 400         int ret;
 401
 402         args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
 403         if (args.load.data == 0)
 404                 args.load.data = 340;
 405
 406         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 407         if (ret || !args.load.load)
 408                 return connector_status_disconnected;
 409
 410         return connector_status_connected;
 411 }
 412
 413 static const struct drm_encoder_helper_funcs
 414 nv50_dac_help = {
 415         .atomic_check = nv50_outp_atomic_check,
 416         .enable = nv50_dac_enable,
 417         .disable = nv50_dac_disable,
 418         .detect = nv50_dac_detect
 419 };
 420
 421 static void
 422 nv50_dac_destroy(struct drm_encoder *encoder)
 423 {
 424         drm_encoder_cleanup(encoder);
 425         kfree(encoder);
 426 }
 427
 428 static const struct drm_encoder_funcs
 429 nv50_dac_func = {
 430         .destroy = nv50_dac_destroy,
 431 };
 432
 433 static int
 434 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
 435 {
 436         struct nouveau_drm *drm = nouveau_drm(connector->dev);
 437         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
 438         struct nvkm_i2c_bus *bus;
 439         struct nouveau_encoder *nv_encoder;
 440         struct drm_encoder *encoder;
 441         int type = DRM_MODE_ENCODER_DAC;
 442
 443         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 444         if (!nv_encoder)
 445                 return -ENOMEM;
 446         nv_encoder->dcb = dcbe;
 447
 448         bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
 449         if (bus)
 450                 nv_encoder->i2c = &bus->i2c;
 451
 452         encoder = to_drm_encoder(nv_encoder);
 453         encoder->possible_crtcs = dcbe->heads;
 454         encoder->possible_clones = 0;
 455         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
 456                          "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
 457         drm_encoder_helper_add(encoder, &nv50_dac_help);
 458
 459         drm_connector_attach_encoder(connector, encoder);
 460         return 0;
 461 }
 462
 463 /******************************************************************************
 464  * Audio
 465  *****************************************************************************/
 466 static void
 467 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 468 {
 469         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 470         struct nv50_disp *disp = nv50_disp(encoder->dev);
 471         struct {
 472                 struct nv50_disp_mthd_v1 base;
 473                 struct nv50_disp_sor_hda_eld_v0 eld;
 474         } args = {
 475                 .base.version = 1,
 476                 .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 477                 .base.hasht   = nv_encoder->dcb->hasht,
 478                 .base.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 479                                 (0x0100 << nv_crtc->index),
 480         };
 481
 482         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 483 }
 484
 485 static void
 486 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
 487 {
 488         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 489         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 490         struct nouveau_connector *nv_connector;
 491         struct nv50_disp *disp = nv50_disp(encoder->dev);
 492         struct __packed {
 493                 struct {
 494                         struct nv50_disp_mthd_v1 mthd;
 495                         struct nv50_disp_sor_hda_eld_v0 eld;
 496                 } base;
 497                 u8 data[sizeof(nv_connector->base.eld)];
 498         } args = {
 499                 .base.mthd.version = 1,
 500                 .base.mthd.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 501                 .base.mthd.hasht   = nv_encoder->dcb->hasht,
 502                 .base.mthd.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 503                                      (0x0100 << nv_crtc->index),
 504         };
 505
 506         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 507         if (!drm_detect_monitor_audio(nv_connector->edid))
 508                 return;
 509
 510         memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
 511
 512         nvif_mthd(&disp->disp->object, 0, &args,
 513                   sizeof(args.base) + drm_eld_size(args.data));
 514 }
 515
 516 /******************************************************************************
 517  * HDMI
 518  *****************************************************************************/
 519 static void
 520 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 521 {
 522         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 523         struct nv50_disp *disp = nv50_disp(encoder->dev);
 524         struct {
 525                 struct nv50_disp_mthd_v1 base;
 526                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 527         } args = {
 528                 .base.version = 1,
 529                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 530                 .base.hasht  = nv_encoder->dcb->hasht,
 531                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 532                                (0x0100 << nv_crtc->index),
 533         };
 534
 535         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 536 }
 537
 538 static void
 539 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
 540 {
 541         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 542         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 543         struct nv50_disp *disp = nv50_disp(encoder->dev);
 544         struct {
 545                 struct nv50_disp_mthd_v1 base;
 546                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 547                 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */
 548         } args = {
 549                 .base.version = 1,
 550                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 551                 .base.hasht  = nv_encoder->dcb->hasht,
 552                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 553                                (0x0100 << nv_crtc->index),
 554                 .pwr.state = 1,
 555                 .pwr.rekey = 56, /* binary driver, and tegra, constant */
 556         };
 557         struct nouveau_connector *nv_connector;
 558         u32 max_ac_packet;
 559         union hdmi_infoframe avi_frame;
 560         union hdmi_infoframe vendor_frame;
 561         int ret;
 562         int size;
 563
 564         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 565         if (!drm_detect_hdmi_monitor(nv_connector->edid))
 566                 return;
 567
 568         ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi, mode,
 569                                                        false);
 570         if (!ret) {
 571                 /* We have an AVI InfoFrame, populate it to the display */
 572                 args.pwr.avi_infoframe_length
 573                         = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17);
 574         }
 575
 576         ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi,
 577                                                           &nv_connector->base, mode);
 578         if (!ret) {
 579                 /* We have a Vendor InfoFrame, populate it to the display */
 580                 args.pwr.vendor_infoframe_length
 581                         = hdmi_infoframe_pack(&vendor_frame,
 582                                               args.infoframes
 583                                               + args.pwr.avi_infoframe_length,
 584                                               17);
 585         }
 586
 587         max_ac_packet  = mode->htotal - mode->hdisplay;
 588         max_ac_packet -= args.pwr.rekey;
 589         max_ac_packet -= 18; /* constant from tegra */
 590         args.pwr.max_ac_packet = max_ac_packet / 32;
 591
 592         size = sizeof(args.base)
 593                 + sizeof(args.pwr)
 594                 + args.pwr.avi_infoframe_length
 595                 + args.pwr.vendor_infoframe_length;
 596         nvif_mthd(&disp->disp->object, 0, &args, size);
 597         nv50_audio_enable(encoder, mode);
 598 }
 599
 600 /******************************************************************************
 601  * MST
 602  *****************************************************************************/
 603 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
 604 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
 605 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
 606
 607 struct nv50_mstm {
 608         struct nouveau_encoder *outp;
 609
 610         struct drm_dp_mst_topology_mgr mgr;
 611         struct nv50_msto *msto[4];
 612
 613         bool modified;
 614         bool disabled;
 615         int links;
 616 };
 617
 618 struct nv50_mstc {
 619         struct nv50_mstm *mstm;
 620         struct drm_dp_mst_port *port;
 621         struct drm_connector connector;
 622
 623         struct drm_display_mode *native;
 624         struct edid *edid;
 625
 626         int pbn;
 627 };
 628
 629 struct nv50_msto {
 630         struct drm_encoder encoder;
 631
 632         struct nv50_head *head;
 633         struct nv50_mstc *mstc;
 634         bool disabled;
 635 };
 636
 637 static struct drm_dp_payload *
 638 nv50_msto_payload(struct nv50_msto *msto)
 639 {
 640         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 641         struct nv50_mstc *mstc = msto->mstc;
 642         struct nv50_mstm *mstm = mstc->mstm;
 643         int vcpi = mstc->port->vcpi.vcpi, i;
 644
 645         NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
 646         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 647                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 648                 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
 649                           mstm->outp->base.base.name, i, payload->vcpi,
 650                           payload->start_slot, payload->num_slots);
 651         }
 652
 653         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 654                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 655                 if (payload->vcpi == vcpi)
 656                         return payload;
 657         }
 658
 659         return NULL;
 660 }
 661
 662 static void
 663 nv50_msto_cleanup(struct nv50_msto *msto)
 664 {
 665         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 666         struct nv50_mstc *mstc = msto->mstc;
 667         struct nv50_mstm *mstm = mstc->mstm;
 668
 669         NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
 670         if (mstc->port && mstc->port->vcpi.vcpi > 0 && !nv50_msto_payload(msto))
 671                 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
 672         if (msto->disabled) {
 673                 msto->mstc = NULL;
 674                 msto->head = NULL;
 675                 msto->disabled = false;
 676         }
 677 }
 678
 679 static void
 680 nv50_msto_prepare(struct nv50_msto *msto)
 681 {
 682         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 683         struct nv50_mstc *mstc = msto->mstc;
 684         struct nv50_mstm *mstm = mstc->mstm;
 685         struct {
 686                 struct nv50_disp_mthd_v1 base;
 687                 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
 688         } args = {
 689                 .base.version = 1,
 690                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
 691                 .base.hasht  = mstm->outp->dcb->hasht,
 692                 .base.hashm  = (0xf0ff & mstm->outp->dcb->hashm) |
 693                                (0x0100 << msto->head->base.index),
 694         };
 695
 696         NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
 697         if (mstc->port && mstc->port->vcpi.vcpi > 0) {
 698                 struct drm_dp_payload *payload = nv50_msto_payload(msto);
 699                 if (payload) {
 700                         args.vcpi.start_slot = payload->start_slot;
 701                         args.vcpi.num_slots = payload->num_slots;
 702                         args.vcpi.pbn = mstc->port->vcpi.pbn;
 703                         args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
 704                 }
 705         }
 706
 707         NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
 708                   msto->encoder.name, msto->head->base.base.name,
 709                   args.vcpi.start_slot, args.vcpi.num_slots,
 710                   args.vcpi.pbn, args.vcpi.aligned_pbn);
 711         nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args));
 712 }
 713
 714 static int
 715 nv50_msto_atomic_check(struct drm_encoder *encoder,
 716                        struct drm_crtc_state *crtc_state,
 717                        struct drm_connector_state *conn_state)
 718 {
 719         struct nv50_mstc *mstc = nv50_mstc(conn_state->connector);
 720         struct nv50_mstm *mstm = mstc->mstm;
 721         int bpp = conn_state->connector->display_info.bpc * 3;
 722         int slots;
 723
 724         mstc->pbn = drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock, bpp);
 725
 726         slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
 727         if (slots < 0)
 728                 return slots;
 729
 730         return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 731                                            mstc->native);
 732 }
 733
 734 static void
 735 nv50_msto_enable(struct drm_encoder *encoder)
 736 {
 737         struct nv50_head *head = nv50_head(encoder->crtc);
 738         struct nv50_msto *msto = nv50_msto(encoder);
 739         struct nv50_mstc *mstc = NULL;
 740         struct nv50_mstm *mstm = NULL;
 741         struct drm_connector *connector;
 742         struct drm_connector_list_iter conn_iter;
 743         u8 proto, depth;
 744         int slots;
 745         bool r;
 746
 747         drm_connector_list_iter_begin(encoder->dev, &conn_iter);
 748         drm_for_each_connector_iter(connector, &conn_iter) {
 749                 if (connector->state->best_encoder == &msto->encoder) {
 750                         mstc = nv50_mstc(connector);
 751                         mstm = mstc->mstm;
 752                         break;
 753                 }
 754         }
 755         drm_connector_list_iter_end(&conn_iter);
 756
 757         if (WARN_ON(!mstc))
 758                 return;
 759
 760         slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
 761         r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, mstc->pbn, slots);
 762         if (!r)
 763                 DRM_DEBUG_KMS("Failed to allocate VCPI\n");
 764
 765         if (!mstm->links++)
 766                 nv50_outp_acquire(mstm->outp);
 767
 768         if (mstm->outp->link & 1)
 769                 proto = 0x8;
 770         else
 771                 proto = 0x9;
 772
 773         switch (mstc->connector.display_info.bpc) {
 774         case  6: depth = 0x2; break;
 775         case  8: depth = 0x5; break;
 776         case 10:
 777         default: depth = 0x6; break;
 778         }
 779
 780         mstm->outp->update(mstm->outp, head->base.index,
 781                            nv50_head_atom(head->base.base.state), proto, depth);
 782
 783         msto->head = head;
 784         msto->mstc = mstc;
 785         mstm->modified = true;
 786 }
 787
 788 static void
 789 nv50_msto_disable(struct drm_encoder *encoder)
 790 {
 791         struct nv50_msto *msto = nv50_msto(encoder);
 792         struct nv50_mstc *mstc = msto->mstc;
 793         struct nv50_mstm *mstm = mstc->mstm;
 794
 795         if (mstc->port)
 796                 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
 797
 798         mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
 799         mstm->modified = true;
 800         if (!--mstm->links)
 801                 mstm->disabled = true;
 802         msto->disabled = true;
 803 }
 804
 805 static const struct drm_encoder_helper_funcs
 806 nv50_msto_help = {
 807         .disable = nv50_msto_disable,
 808         .enable = nv50_msto_enable,
 809         .atomic_check = nv50_msto_atomic_check,
 810 };
 811
 812 static void
 813 nv50_msto_destroy(struct drm_encoder *encoder)
 814 {
 815         struct nv50_msto *msto = nv50_msto(encoder);
 816         drm_encoder_cleanup(&msto->encoder);
 817         kfree(msto);
 818 }
 819
 820 static const struct drm_encoder_funcs
 821 nv50_msto = {
 822         .destroy = nv50_msto_destroy,
 823 };
 824
 825 static int
 826 nv50_msto_new(struct drm_device *dev, u32 heads, const char *name, int id,
 827               struct nv50_msto **pmsto)
 828 {
 829         struct nv50_msto *msto;
 830         int ret;
 831
 832         if (!(msto = *pmsto = kzalloc(sizeof(*msto), GFP_KERNEL)))
 833                 return -ENOMEM;
 834
 835         ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
 836                                DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id);
 837         if (ret) {
 838                 kfree(*pmsto);
 839                 *pmsto = NULL;
 840                 return ret;
 841         }
 842
 843         drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
 844         msto->encoder.possible_crtcs = heads;
 845         return 0;
 846 }
 847
 848 static struct drm_encoder *
 849 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
 850                               struct drm_connector_state *connector_state)
 851 {
 852         struct nv50_head *head = nv50_head(connector_state->crtc);
 853         struct nv50_mstc *mstc = nv50_mstc(connector);
 854
 855         return &mstc->mstm->msto[head->base.index]->encoder;
 856 }
 857
 858 static struct drm_encoder *
 859 nv50_mstc_best_encoder(struct drm_connector *connector)
 860 {
 861         struct nv50_mstc *mstc = nv50_mstc(connector);
 862
 863         return &mstc->mstm->msto[0]->encoder;
 864 }
 865
 866 static enum drm_mode_status
 867 nv50_mstc_mode_valid(struct drm_connector *connector,
 868                      struct drm_display_mode *mode)
 869 {
 870         return MODE_OK;
 871 }
 872
 873 static int
 874 nv50_mstc_get_modes(struct drm_connector *connector)
 875 {
 876         struct nv50_mstc *mstc = nv50_mstc(connector);
 877         int ret = 0;
 878
 879         mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
 880         drm_connector_update_edid_property(&mstc->connector, mstc->edid);
 881         if (mstc->edid)
 882                 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
 883
 884         if (!mstc->connector.display_info.bpc)
 885                 mstc->connector.display_info.bpc = 8;
 886
 887         if (mstc->native)
 888                 drm_mode_destroy(mstc->connector.dev, mstc->native);
 889         mstc->native = nouveau_conn_native_mode(&mstc->connector);
 890         return ret;
 891 }
 892
 893 static const struct drm_connector_helper_funcs
 894 nv50_mstc_help = {
 895         .get_modes = nv50_mstc_get_modes,
 896         .mode_valid = nv50_mstc_mode_valid,
 897         .best_encoder = nv50_mstc_best_encoder,
 898         .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
 899 };
 900
 901 static enum drm_connector_status
 902 nv50_mstc_detect(struct drm_connector *connector, bool force)
 903 {
 904         struct nv50_mstc *mstc = nv50_mstc(connector);
 905         enum drm_connector_status conn_status;
 906         int ret;
 907
 908         if (!mstc->port)
 909                 return connector_status_disconnected;
 910
 911         ret = pm_runtime_get_sync(connector->dev->dev);
 912         if (ret < 0 && ret != -EACCES) {
 913                 pm_runtime_put_autosuspend(connector->dev->dev);
 914                 return connector_status_disconnected;
 915         }
 916
 917         conn_status = drm_dp_mst_detect_port(connector, mstc->port->mgr,
 918                                              mstc->port);
 919
 920         pm_runtime_mark_last_busy(connector->dev->dev);
 921         pm_runtime_put_autosuspend(connector->dev->dev);
 922         return conn_status;
 923 }
 924
 925 static void
 926 nv50_mstc_destroy(struct drm_connector *connector)
 927 {
 928         struct nv50_mstc *mstc = nv50_mstc(connector);
 929         drm_connector_cleanup(&mstc->connector);
 930         kfree(mstc);
 931 }
 932
 933 static const struct drm_connector_funcs
 934 nv50_mstc = {
 935         .reset = nouveau_conn_reset,
 936         .detect = nv50_mstc_detect,
 937         .fill_modes = drm_helper_probe_single_connector_modes,
 938         .destroy = nv50_mstc_destroy,
 939         .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
 940         .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
 941         .atomic_set_property = nouveau_conn_atomic_set_property,
 942         .atomic_get_property = nouveau_conn_atomic_get_property,
 943 };
 944
 945 static int
 946 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
 947               const char *path, struct nv50_mstc **pmstc)
 948 {
 949         struct drm_device *dev = mstm->outp->base.base.dev;
 950         struct nv50_mstc *mstc;
 951         int ret, i;
 952
 953         if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
 954                 return -ENOMEM;
 955         mstc->mstm = mstm;
 956         mstc->port = port;
 957
 958         ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
 959                                  DRM_MODE_CONNECTOR_DisplayPort);
 960         if (ret) {
 961                 kfree(*pmstc);
 962                 *pmstc = NULL;
 963                 return ret;
 964         }
 965
 966         drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
 967
 968         mstc->connector.funcs->reset(&mstc->connector);
 969         nouveau_conn_attach_properties(&mstc->connector);
 970
 971         for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto[i]; i++)
 972                 drm_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder);
 973
 974         drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
 975         drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
 976         drm_connector_set_path_property(&mstc->connector, path);
 977         return 0;
 978 }
 979
 980 static void
 981 nv50_mstm_cleanup(struct nv50_mstm *mstm)
 982 {
 983         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
 984         struct drm_encoder *encoder;
 985         int ret;
 986
 987         NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
 988         ret = drm_dp_check_act_status(&mstm->mgr);
 989
 990         ret = drm_dp_update_payload_part2(&mstm->mgr);
 991
 992         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
 993                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
 994                         struct nv50_msto *msto = nv50_msto(encoder);
 995                         struct nv50_mstc *mstc = msto->mstc;
 996                         if (mstc && mstc->mstm == mstm)
 997                                 nv50_msto_cleanup(msto);
 998                 }
 999         }
1000
1001         mstm->modified = false;
1002 }
1003
1004 static void
1005 nv50_mstm_prepare(struct nv50_mstm *mstm)
1006 {
1007         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1008         struct drm_encoder *encoder;
1009         int ret;
1010
1011         NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
1012         ret = drm_dp_update_payload_part1(&mstm->mgr);
1013
1014         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1015                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1016                         struct nv50_msto *msto = nv50_msto(encoder);
1017                         struct nv50_mstc *mstc = msto->mstc;
1018                         if (mstc && mstc->mstm == mstm)
1019                                 nv50_msto_prepare(msto);
1020                 }
1021         }
1022
1023         if (mstm->disabled) {
1024                 if (!mstm->links)
1025                         nv50_outp_release(mstm->outp);
1026                 mstm->disabled = false;
1027         }
1028 }
1029
1030 static void
1031 nv50_mstm_hotplug(struct drm_dp_mst_topology_mgr *mgr)
1032 {
1033         struct nv50_mstm *mstm = nv50_mstm(mgr);
1034         drm_kms_helper_hotplug_event(mstm->outp->base.base.dev);
1035 }
1036
1037 static void
1038 nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr,
1039                             struct drm_connector *connector)
1040 {
1041         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1042         struct nv50_mstc *mstc = nv50_mstc(connector);
1043
1044         drm_connector_unregister(&mstc->connector);
1045
1046         drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector);
1047
1048         drm_modeset_lock(&drm->dev->mode_config.connection_mutex, NULL);
1049         mstc->port = NULL;
1050         drm_modeset_unlock(&drm->dev->mode_config.connection_mutex);
1051
1052         drm_connector_put(&mstc->connector);
1053 }
1054
1055 static void
1056 nv50_mstm_register_connector(struct drm_connector *connector)
1057 {
1058         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1059
1060         drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector);
1061
1062         drm_connector_register(connector);
1063 }
1064
1065 static struct drm_connector *
1066 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1067                         struct drm_dp_mst_port *port, const char *path)
1068 {
1069         struct nv50_mstm *mstm = nv50_mstm(mgr);
1070         struct nv50_mstc *mstc;
1071         int ret;
1072
1073         ret = nv50_mstc_new(mstm, port, path, &mstc);
1074         if (ret) {
1075                 if (mstc)
1076                         mstc->connector.funcs->destroy(&mstc->connector);
1077                 return NULL;
1078         }
1079
1080         return &mstc->connector;
1081 }
1082
1083 static const struct drm_dp_mst_topology_cbs
1084 nv50_mstm = {
1085         .add_connector = nv50_mstm_add_connector,
1086         .register_connector = nv50_mstm_register_connector,
1087         .destroy_connector = nv50_mstm_destroy_connector,
1088         .hotplug = nv50_mstm_hotplug,
1089 };
1090
1091 void
1092 nv50_mstm_service(struct nv50_mstm *mstm)
1093 {
1094         struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL;
1095         bool handled = true;
1096         int ret;
1097         u8 esi[8] = {};
1098
1099         if (!aux)
1100                 return;
1101
1102         while (handled) {
1103                 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1104                 if (ret != 8) {
1105                         drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1106                         return;
1107                 }
1108
1109                 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
1110                 if (!handled)
1111                         break;
1112
1113                 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
1114         }
1115 }
1116
1117 void
1118 nv50_mstm_remove(struct nv50_mstm *mstm)
1119 {
1120         if (mstm)
1121                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1122 }
1123
1124 static int
1125 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
1126 {
1127         struct nouveau_encoder *outp = mstm->outp;
1128         struct {
1129                 struct nv50_disp_mthd_v1 base;
1130                 struct nv50_disp_sor_dp_mst_link_v0 mst;
1131         } args = {
1132                 .base.version = 1,
1133                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
1134                 .base.hasht = outp->dcb->hasht,
1135                 .base.hashm = outp->dcb->hashm,
1136                 .mst.state = state,
1137         };
1138         struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
1139         struct nvif_object *disp = &drm->display->disp.object;
1140         int ret;
1141
1142         if (dpcd >= 0x12) {
1143                 /* Even if we're enabling MST, start with disabling the
1144                  * branching unit to clear any sink-side MST topology state
1145                  * that wasn't set by us
1146                  */
1147                 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 0);
1148                 if (ret < 0)
1149                         return ret;
1150
1151                 if (state) {
1152                         /* Now, start initializing */
1153                         ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL,
1154                                                  DP_MST_EN);
1155                         if (ret < 0)
1156                                 return ret;
1157                 }
1158         }
1159
1160         return nvif_mthd(disp, 0, &args, sizeof(args));
1161 }
1162
1163 int
1164 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
1165 {
1166         struct drm_dp_aux *aux;
1167         int ret;
1168         bool old_state, new_state;
1169         u8 mstm_ctrl;
1170
1171         if (!mstm)
1172                 return 0;
1173
1174         mutex_lock(&mstm->mgr.lock);
1175
1176         old_state = mstm->mgr.mst_state;
1177         new_state = old_state;
1178         aux = mstm->mgr.aux;
1179
1180         if (old_state) {
1181                 /* Just check that the MST hub is still as we expect it */
1182                 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CTRL, &mstm_ctrl);
1183                 if (ret < 0 || !(mstm_ctrl & DP_MST_EN)) {
1184                         DRM_DEBUG_KMS("Hub gone, disabling MST topology\n");
1185                         new_state = false;
1186                 }
1187         } else if (dpcd[0] >= 0x12) {
1188                 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]);
1189                 if (ret < 0)
1190                         goto probe_error;
1191
1192                 if (!(dpcd[1] & DP_MST_CAP))
1193                         dpcd[0] = 0x11;
1194                 else
1195                         new_state = allow;
1196         }
1197
1198         if (new_state == old_state) {
1199                 mutex_unlock(&mstm->mgr.lock);
1200                 return new_state;
1201         }
1202
1203         ret = nv50_mstm_enable(mstm, dpcd[0], new_state);
1204         if (ret)
1205                 goto probe_error;
1206
1207         mutex_unlock(&mstm->mgr.lock);
1208
1209         ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, new_state);
1210         if (ret)
1211                 return nv50_mstm_enable(mstm, dpcd[0], 0);
1212
1213         return new_state;
1214
1215 probe_error:
1216         mutex_unlock(&mstm->mgr.lock);
1217         return ret;
1218 }
1219
1220 static void
1221 nv50_mstm_fini(struct nv50_mstm *mstm)
1222 {
1223         if (mstm && mstm->mgr.mst_state)
1224                 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1225 }
1226
1227 static void
1228 nv50_mstm_init(struct nv50_mstm *mstm)
1229 {
1230         int ret;
1231
1232         if (!mstm || !mstm->mgr.mst_state)
1233                 return;
1234
1235         ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr);
1236         if (ret == -1) {
1237                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1238                 drm_kms_helper_hotplug_event(mstm->mgr.dev);
1239         }
1240 }
1241
1242 static void
1243 nv50_mstm_del(struct nv50_mstm **pmstm)
1244 {
1245         struct nv50_mstm *mstm = *pmstm;
1246         if (mstm) {
1247                 drm_dp_mst_topology_mgr_destroy(&mstm->mgr);
1248                 kfree(*pmstm);
1249                 *pmstm = NULL;
1250         }
1251 }
1252
1253 static int
1254 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
1255               int conn_base_id, struct nv50_mstm **pmstm)
1256 {
1257         const int max_payloads = hweight8(outp->dcb->heads);
1258         struct drm_device *dev = outp->base.base.dev;
1259         struct nv50_mstm *mstm;
1260         int ret, i;
1261         u8 dpcd;
1262
1263         /* This is a workaround for some monitors not functioning
1264          * correctly in MST mode on initial module load.  I think
1265          * some bad interaction with the VBIOS may be responsible.
1266          *
1267          * A good ol' off and on again seems to work here ;)
1268          */
1269         ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
1270         if (ret >= 0 && dpcd >= 0x12)
1271                 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
1272
1273         if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
1274                 return -ENOMEM;
1275         mstm->outp = outp;
1276         mstm->mgr.cbs = &nv50_mstm;
1277
1278         ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
1279                                            max_payloads, conn_base_id);
1280         if (ret)
1281                 return ret;
1282
1283         for (i = 0; i < max_payloads; i++) {
1284                 ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name,
1285                                     i, &mstm->msto[i]);
1286                 if (ret)
1287                         return ret;
1288         }
1289
1290         return 0;
1291 }
1292
1293 /******************************************************************************
1294  * SOR
1295  *****************************************************************************/
1296 static void
1297 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
1298                 struct nv50_head_atom *asyh, u8 proto, u8 depth)
1299 {
1300         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
1301         struct nv50_core *core = disp->core;
1302
1303         if (!asyh) {
1304                 nv_encoder->ctrl &= ~BIT(head);
1305                 if (!(nv_encoder->ctrl & 0x0000000f))
1306                         nv_encoder->ctrl = 0;
1307         } else {
1308                 nv_encoder->ctrl |= proto << 8;
1309                 nv_encoder->ctrl |= BIT(head);
1310                 asyh->or.depth = depth;
1311         }
1312
1313         core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);
1314 }
1315
1316 static void
1317 nv50_sor_disable(struct drm_encoder *encoder)
1318 {
1319         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1320         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1321
1322         nv_encoder->crtc = NULL;
1323
1324         if (nv_crtc) {
1325                 struct nvkm_i2c_aux *aux = nv_encoder->aux;
1326                 u8 pwr;
1327
1328                 if (aux) {
1329                         int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1);
1330                         if (ret == 0) {
1331                                 pwr &= ~DP_SET_POWER_MASK;
1332                                 pwr |=  DP_SET_POWER_D3;
1333                                 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1);
1334                         }
1335                 }
1336
1337                 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
1338                 nv50_audio_disable(encoder, nv_crtc);
1339                 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
1340                 nv50_outp_release(nv_encoder);
1341         }
1342 }
1343
1344 static void
1345 nv50_sor_enable(struct drm_encoder *encoder)
1346 {
1347         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1348         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1349         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1350         struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1351         struct {
1352                 struct nv50_disp_mthd_v1 base;
1353                 struct nv50_disp_sor_lvds_script_v0 lvds;
1354         } lvds = {
1355                 .base.version = 1,
1356                 .base.method  = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1357                 .base.hasht   = nv_encoder->dcb->hasht,
1358                 .base.hashm   = nv_encoder->dcb->hashm,
1359         };
1360         struct nv50_disp *disp = nv50_disp(encoder->dev);
1361         struct drm_device *dev = encoder->dev;
1362         struct nouveau_drm *drm = nouveau_drm(dev);
1363         struct nouveau_connector *nv_connector;
1364         struct nvbios *bios = &drm->vbios;
1365         u8 proto = 0xf;
1366         u8 depth = 0x0;
1367
1368         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1369         nv_encoder->crtc = encoder->crtc;
1370         nv50_outp_acquire(nv_encoder);
1371
1372         switch (nv_encoder->dcb->type) {
1373         case DCB_OUTPUT_TMDS:
1374                 if (nv_encoder->link & 1) {
1375                         proto = 0x1;
1376                         /* Only enable dual-link if:
1377                          *  - Need to (i.e. rate > 165MHz)
1378                          *  - DCB says we can
1379                          *  - Not an HDMI monitor, since there's no dual-link
1380                          *    on HDMI.
1381                          */
1382                         if (mode->clock >= 165000 &&
1383                             nv_encoder->dcb->duallink_possible &&
1384                             !drm_detect_hdmi_monitor(nv_connector->edid))
1385                                 proto |= 0x4;
1386                 } else {
1387                         proto = 0x2;
1388                 }
1389
1390                 nv50_hdmi_enable(&nv_encoder->base.base, mode);
1391                 break;
1392         case DCB_OUTPUT_LVDS:
1393                 proto = 0x0;
1394
1395                 if (bios->fp_no_ddc) {
1396                         if (bios->fp.dual_link)
1397                                 lvds.lvds.script |= 0x0100;
1398                         if (bios->fp.if_is_24bit)
1399                                 lvds.lvds.script |= 0x0200;
1400                 } else {
1401                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1402                                 if (((u8 *)nv_connector->edid)[121] == 2)
1403                                         lvds.lvds.script |= 0x0100;
1404                         } else
1405                         if (mode->clock >= bios->fp.duallink_transition_clk) {
1406                                 lvds.lvds.script |= 0x0100;
1407                         }
1408
1409                         if (lvds.lvds.script & 0x0100) {
1410                                 if (bios->fp.strapless_is_24bit & 2)
1411                                         lvds.lvds.script |= 0x0200;
1412                         } else {
1413                                 if (bios->fp.strapless_is_24bit & 1)
1414                                         lvds.lvds.script |= 0x0200;
1415                         }
1416
1417                         if (nv_connector->base.display_info.bpc == 8)
1418                                 lvds.lvds.script |= 0x0200;
1419                 }
1420
1421                 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds));
1422                 break;
1423         case DCB_OUTPUT_DP:
1424                 if (nv_connector->base.display_info.bpc == 6)
1425                         depth = 0x2;
1426                 else
1427                 if (nv_connector->base.display_info.bpc == 8)
1428                         depth = 0x5;
1429                 else
1430                         depth = 0x6;
1431
1432                 if (nv_encoder->link & 1)
1433                         proto = 0x8;
1434                 else
1435                         proto = 0x9;
1436
1437                 nv50_audio_enable(encoder, mode);
1438                 break;
1439         default:
1440                 BUG();
1441                 break;
1442         }
1443
1444         nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1445 }
1446
1447 static const struct drm_encoder_helper_funcs
1448 nv50_sor_help = {
1449         .atomic_check = nv50_outp_atomic_check,
1450         .enable = nv50_sor_enable,
1451         .disable = nv50_sor_disable,
1452 };
1453
1454 static void
1455 nv50_sor_destroy(struct drm_encoder *encoder)
1456 {
1457         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1458         nv50_mstm_del(&nv_encoder->dp.mstm);
1459         drm_encoder_cleanup(encoder);
1460         kfree(encoder);
1461 }
1462
1463 static const struct drm_encoder_funcs
1464 nv50_sor_func = {
1465         .destroy = nv50_sor_destroy,
1466 };
1467
1468 static int
1469 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1470 {
1471         struct nouveau_connector *nv_connector = nouveau_connector(connector);
1472         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1473         struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
1474         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1475         struct nouveau_encoder *nv_encoder;
1476         struct drm_encoder *encoder;
1477         u8 ver, hdr, cnt, len;
1478         u32 data;
1479         int type, ret;
1480
1481         switch (dcbe->type) {
1482         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1483         case DCB_OUTPUT_TMDS:
1484         case DCB_OUTPUT_DP:
1485         default:
1486                 type = DRM_MODE_ENCODER_TMDS;
1487                 break;
1488         }
1489
1490         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1491         if (!nv_encoder)
1492                 return -ENOMEM;
1493         nv_encoder->dcb = dcbe;
1494         nv_encoder->update = nv50_sor_update;
1495
1496         encoder = to_drm_encoder(nv_encoder);
1497         encoder->possible_crtcs = dcbe->heads;
1498         encoder->possible_clones = 0;
1499         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
1500                          "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
1501         drm_encoder_helper_add(encoder, &nv50_sor_help);
1502
1503         drm_connector_attach_encoder(connector, encoder);
1504
1505         if (dcbe->type == DCB_OUTPUT_DP) {
1506                 struct nv50_disp *disp = nv50_disp(encoder->dev);
1507                 struct nvkm_i2c_aux *aux =
1508                         nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
1509                 if (aux) {
1510                         if (disp->disp->object.oclass < GF110_DISP) {
1511                                 /* HW has no support for address-only
1512                                  * transactions, so we're required to
1513                                  * use custom I2C-over-AUX code.
1514                                  */
1515                                 nv_encoder->i2c = &aux->i2c;
1516                         } else {
1517                                 nv_encoder->i2c = &nv_connector->aux.ddc;
1518                         }
1519                         nv_encoder->aux = aux;
1520                 }
1521
1522                 if (nv_connector->type != DCB_CONNECTOR_eDP &&
1523                     (data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len)) &&
1524                     ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04)) {
1525                         ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16,
1526                                             nv_connector->base.base.id,
1527                                             &nv_encoder->dp.mstm);
1528                         if (ret)
1529                                 return ret;
1530                 }
1531         } else {
1532                 struct nvkm_i2c_bus *bus =
1533                         nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1534                 if (bus)
1535                         nv_encoder->i2c = &bus->i2c;
1536         }
1537
1538         return 0;
1539 }
1540
1541 /******************************************************************************
1542  * PIOR
1543  *****************************************************************************/
1544 static int
1545 nv50_pior_atomic_check(struct drm_encoder *encoder,
1546                        struct drm_crtc_state *crtc_state,
1547                        struct drm_connector_state *conn_state)
1548 {
1549         int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
1550         if (ret)
1551                 return ret;
1552         crtc_state->adjusted_mode.clock *= 2;
1553         return 0;
1554 }
1555
1556 static void
1557 nv50_pior_disable(struct drm_encoder *encoder)
1558 {
1559         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1560         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1561         if (nv_encoder->crtc)
1562                 core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL);
1563         nv_encoder->crtc = NULL;
1564         nv50_outp_release(nv_encoder);
1565 }
1566
1567 static void
1568 nv50_pior_enable(struct drm_encoder *encoder)
1569 {
1570         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1571         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1572         struct nouveau_connector *nv_connector;
1573         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1574         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1575         u8 owner = 1 << nv_crtc->index;
1576         u8 proto;
1577
1578         nv50_outp_acquire(nv_encoder);
1579
1580         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1581         switch (nv_connector->base.display_info.bpc) {
1582         case 10: asyh->or.depth = 0x6; break;
1583         case  8: asyh->or.depth = 0x5; break;
1584         case  6: asyh->or.depth = 0x2; break;
1585         default: asyh->or.depth = 0x0; break;
1586         }
1587
1588         switch (nv_encoder->dcb->type) {
1589         case DCB_OUTPUT_TMDS:
1590         case DCB_OUTPUT_DP:
1591                 proto = 0x0;
1592                 break;
1593         default:
1594                 BUG();
1595                 break;
1596         }
1597
1598         core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh);
1599         nv_encoder->crtc = encoder->crtc;
1600 }
1601
1602 static const struct drm_encoder_helper_funcs
1603 nv50_pior_help = {
1604         .atomic_check = nv50_pior_atomic_check,
1605         .enable = nv50_pior_enable,
1606         .disable = nv50_pior_disable,
1607 };
1608
1609 static void
1610 nv50_pior_destroy(struct drm_encoder *encoder)
1611 {
1612         drm_encoder_cleanup(encoder);
1613         kfree(encoder);
1614 }
1615
1616 static const struct drm_encoder_funcs
1617 nv50_pior_func = {
1618         .destroy = nv50_pior_destroy,
1619 };
1620
1621 static int
1622 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
1623 {
1624         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1625         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1626         struct nvkm_i2c_bus *bus = NULL;
1627         struct nvkm_i2c_aux *aux = NULL;
1628         struct i2c_adapter *ddc;
1629         struct nouveau_encoder *nv_encoder;
1630         struct drm_encoder *encoder;
1631         int type;
1632
1633         switch (dcbe->type) {
1634         case DCB_OUTPUT_TMDS:
1635                 bus  = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
1636                 ddc  = bus ? &bus->i2c : NULL;
1637                 type = DRM_MODE_ENCODER_TMDS;
1638                 break;
1639         case DCB_OUTPUT_DP:
1640                 aux  = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
1641                 ddc  = aux ? &aux->i2c : NULL;
1642                 type = DRM_MODE_ENCODER_TMDS;
1643                 break;
1644         default:
1645                 return -ENODEV;
1646         }
1647
1648         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1649         if (!nv_encoder)
1650                 return -ENOMEM;
1651         nv_encoder->dcb = dcbe;
1652         nv_encoder->i2c = ddc;
1653         nv_encoder->aux = aux;
1654
1655         encoder = to_drm_encoder(nv_encoder);
1656         encoder->possible_crtcs = dcbe->heads;
1657         encoder->possible_clones = 0;
1658         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
1659                          "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
1660         drm_encoder_helper_add(encoder, &nv50_pior_help);
1661
1662         drm_connector_attach_encoder(connector, encoder);
1663         return 0;
1664 }
1665
1666 /******************************************************************************
1667  * Atomic
1668  *****************************************************************************/
1669
1670 static void
1671 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock)
1672 {
1673         struct nouveau_drm *drm = nouveau_drm(state->dev);
1674         struct nv50_disp *disp = nv50_disp(drm->dev);
1675         struct nv50_core *core = disp->core;
1676         struct nv50_mstm *mstm;
1677         struct drm_encoder *encoder;
1678
1679         NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]);
1680
1681         drm_for_each_encoder(encoder, drm->dev) {
1682                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1683                         mstm = nouveau_encoder(encoder)->dp.mstm;
1684                         if (mstm && mstm->modified)
1685                                 nv50_mstm_prepare(mstm);
1686                 }
1687         }
1688
1689         core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY);
1690         core->func->update(core, interlock, true);
1691         if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY,
1692                                        disp->core->chan.base.device))
1693                 NV_ERROR(drm, "core notifier timeout\n");
1694
1695         drm_for_each_encoder(encoder, drm->dev) {
1696                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1697                         mstm = nouveau_encoder(encoder)->dp.mstm;
1698                         if (mstm && mstm->modified)
1699                                 nv50_mstm_cleanup(mstm);
1700                 }
1701         }
1702 }
1703
1704 static void
1705 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock)
1706 {
1707         struct drm_plane_state *new_plane_state;
1708         struct drm_plane *plane;
1709         int i;
1710
1711         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1712                 struct nv50_wndw *wndw = nv50_wndw(plane);
1713                 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
1714                         if (wndw->func->update)
1715                                 wndw->func->update(wndw, interlock);
1716                 }
1717         }
1718 }
1719
1720 static void
1721 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
1722 {
1723         struct drm_device *dev = state->dev;
1724         struct drm_crtc_state *new_crtc_state, *old_crtc_state;
1725         struct drm_crtc *crtc;
1726         struct drm_plane_state *new_plane_state;
1727         struct drm_plane *plane;
1728         struct nouveau_drm *drm = nouveau_drm(dev);
1729         struct nv50_disp *disp = nv50_disp(dev);
1730         struct nv50_atom *atom = nv50_atom(state);
1731         struct nv50_outp_atom *outp, *outt;
1732         u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
1733         int i;
1734
1735         NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
1736         drm_atomic_helper_wait_for_fences(dev, state, false);
1737         drm_atomic_helper_wait_for_dependencies(state);
1738         drm_atomic_helper_update_legacy_modeset_state(dev, state);
1739
1740         if (atom->lock_core)
1741                 mutex_lock(&disp->mutex);
1742
1743         /* Disable head(s). */
1744         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1745                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1746                 struct nv50_head *head = nv50_head(crtc);
1747
1748                 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
1749                           asyh->clr.mask, asyh->set.mask);
1750                 if (old_crtc_state->active && !new_crtc_state->active)
1751                         drm_crtc_vblank_off(crtc);
1752
1753                 if (asyh->clr.mask) {
1754                         nv50_head_flush_clr(head, asyh, atom->flush_disable);
1755                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1756                 }
1757         }
1758
1759         /* Disable plane(s). */
1760         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1761                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1762                 struct nv50_wndw *wndw = nv50_wndw(plane);
1763
1764                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
1765                           asyw->clr.mask, asyw->set.mask);
1766                 if (!asyw->clr.mask)
1767                         continue;
1768
1769                 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
1770         }
1771
1772         /* Disable output path(s). */
1773         list_for_each_entry(outp, &atom->outp, head) {
1774                 const struct drm_encoder_helper_funcs *help;
1775                 struct drm_encoder *encoder;
1776
1777                 encoder = outp->encoder;
1778                 help = encoder->helper_private;
1779
1780                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
1781                           outp->clr.mask, outp->set.mask);
1782
1783                 if (outp->clr.mask) {
1784                         help->disable(encoder);
1785                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1786                         if (outp->flush_disable) {
1787                                 nv50_disp_atomic_commit_wndw(state, interlock);
1788                                 nv50_disp_atomic_commit_core(state, interlock);
1789                                 memset(interlock, 0x00, sizeof(interlock));
1790                         }
1791                 }
1792         }
1793
1794         /* Flush disable. */
1795         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1796                 if (atom->flush_disable) {
1797                         nv50_disp_atomic_commit_wndw(state, interlock);
1798                         nv50_disp_atomic_commit_core(state, interlock);
1799                         memset(interlock, 0x00, sizeof(interlock));
1800                 }
1801         }
1802
1803         /* Update output path(s). */
1804         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
1805                 const struct drm_encoder_helper_funcs *help;
1806                 struct drm_encoder *encoder;
1807
1808                 encoder = outp->encoder;
1809                 help = encoder->helper_private;
1810
1811                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
1812                           outp->set.mask, outp->clr.mask);
1813
1814                 if (outp->set.mask) {
1815                         help->enable(encoder);
1816                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1817                 }
1818
1819                 list_del(&outp->head);
1820                 kfree(outp);
1821         }
1822
1823         /* Update head(s). */
1824         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1825                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1826                 struct nv50_head *head = nv50_head(crtc);
1827
1828                 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
1829                           asyh->set.mask, asyh->clr.mask);
1830
1831                 if (asyh->set.mask) {
1832                         nv50_head_flush_set(head, asyh);
1833                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1834                 }
1835
1836                 if (new_crtc_state->active) {
1837                         if (!old_crtc_state->active)
1838                                 drm_crtc_vblank_on(crtc);
1839                         if (new_crtc_state->event)
1840                                 drm_crtc_vblank_get(crtc);
1841                 }
1842         }
1843
1844         /* Update plane(s). */
1845         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1846                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1847                 struct nv50_wndw *wndw = nv50_wndw(plane);
1848
1849                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
1850                           asyw->set.mask, asyw->clr.mask);
1851                 if ( !asyw->set.mask &&
1852                     (!asyw->clr.mask || atom->flush_disable))
1853                         continue;
1854
1855                 nv50_wndw_flush_set(wndw, interlock, asyw);
1856         }
1857
1858         /* Flush update. */
1859         nv50_disp_atomic_commit_wndw(state, interlock);
1860
1861         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1862                 if (interlock[NV50_DISP_INTERLOCK_BASE] ||
1863                     interlock[NV50_DISP_INTERLOCK_OVLY] ||
1864                     interlock[NV50_DISP_INTERLOCK_WNDW] ||
1865                     !atom->state.legacy_cursor_update)
1866                         nv50_disp_atomic_commit_core(state, interlock);
1867                 else
1868                         disp->core->func->update(disp->core, interlock, false);
1869         }
1870
1871         if (atom->lock_core)
1872                 mutex_unlock(&disp->mutex);
1873
1874         /* Wait for HW to signal completion. */
1875         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1876                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1877                 struct nv50_wndw *wndw = nv50_wndw(plane);
1878                 int ret = nv50_wndw_wait_armed(wndw, asyw);
1879                 if (ret)
1880                         NV_ERROR(drm, "%s: timeout\n", plane->name);
1881         }
1882
1883         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
1884                 if (new_crtc_state->event) {
1885                         unsigned long flags;
1886                         /* Get correct count/ts if racing with vblank irq */
1887                         if (new_crtc_state->active)
1888                                 drm_crtc_accurate_vblank_count(crtc);
1889                         spin_lock_irqsave(&crtc->dev->event_lock, flags);
1890                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
1891                         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1892
1893                         new_crtc_state->event = NULL;
1894                         if (new_crtc_state->active)
1895                                 drm_crtc_vblank_put(crtc);
1896                 }
1897         }
1898
1899         drm_atomic_helper_commit_hw_done(state);
1900         drm_atomic_helper_cleanup_planes(dev, state);
1901         drm_atomic_helper_commit_cleanup_done(state);
1902         drm_atomic_state_put(state);
1903 }
1904
1905 static void
1906 nv50_disp_atomic_commit_work(struct work_struct *work)
1907 {
1908         struct drm_atomic_state *state =
1909                 container_of(work, typeof(*state), commit_work);
1910         nv50_disp_atomic_commit_tail(state);
1911 }
1912
1913 static int
1914 nv50_disp_atomic_commit(struct drm_device *dev,
1915                         struct drm_atomic_state *state, bool nonblock)
1916 {
1917         struct nouveau_drm *drm = nouveau_drm(dev);
1918         struct drm_plane_state *new_plane_state;
1919         struct drm_plane *plane;
1920         struct drm_crtc *crtc;
1921         bool active = false;
1922         int ret, i;
1923
1924         ret = pm_runtime_get_sync(dev->dev);
1925         if (ret < 0 && ret != -EACCES) {
1926                 pm_runtime_put_autosuspend(dev->dev);
1927                 return ret;
1928         }
1929
1930         ret = drm_atomic_helper_setup_commit(state, nonblock);
1931         if (ret)
1932                 goto done;
1933
1934         INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
1935
1936         ret = drm_atomic_helper_prepare_planes(dev, state);
1937         if (ret)
1938                 goto done;
1939
1940         if (!nonblock) {
1941                 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
1942                 if (ret)
1943                         goto err_cleanup;
1944         }
1945
1946         ret = drm_atomic_helper_swap_state(state, true);
1947         if (ret)
1948                 goto err_cleanup;
1949
1950         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1951                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1952                 struct nv50_wndw *wndw = nv50_wndw(plane);
1953
1954                 if (asyw->set.image)
1955                         nv50_wndw_ntfy_enable(wndw, asyw);
1956         }
1957
1958         drm_atomic_state_get(state);
1959
1960         if (nonblock)
1961                 queue_work(system_unbound_wq, &state->commit_work);
1962         else
1963                 nv50_disp_atomic_commit_tail(state);
1964
1965         drm_for_each_crtc(crtc, dev) {
1966                 if (crtc->state->active) {
1967                         if (!drm->have_disp_power_ref) {
1968                                 drm->have_disp_power_ref = true;
1969                                 return 0;
1970                         }
1971                         active = true;
1972                         break;
1973                 }
1974         }
1975
1976         if (!active && drm->have_disp_power_ref) {
1977                 pm_runtime_put_autosuspend(dev->dev);
1978                 drm->have_disp_power_ref = false;
1979         }
1980
1981 err_cleanup:
1982         if (ret)
1983                 drm_atomic_helper_cleanup_planes(dev, state);
1984 done:
1985         pm_runtime_put_autosuspend(dev->dev);
1986         return ret;
1987 }
1988
1989 static struct nv50_outp_atom *
1990 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
1991 {
1992         struct nv50_outp_atom *outp;
1993
1994         list_for_each_entry(outp, &atom->outp, head) {
1995                 if (outp->encoder == encoder)
1996                         return outp;
1997         }
1998
1999         outp = kzalloc(sizeof(*outp), GFP_KERNEL);
2000         if (!outp)
2001                 return ERR_PTR(-ENOMEM);
2002
2003         list_add(&outp->head, &atom->outp);
2004         outp->encoder = encoder;
2005         return outp;
2006 }
2007
2008 static int
2009 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
2010                                 struct drm_connector_state *old_connector_state)
2011 {
2012         struct drm_encoder *encoder = old_connector_state->best_encoder;
2013         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
2014         struct drm_crtc *crtc;
2015         struct nv50_outp_atom *outp;
2016
2017         if (!(crtc = old_connector_state->crtc))
2018                 return 0;
2019
2020         old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
2021         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2022         if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2023                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2024                 if (IS_ERR(outp))
2025                         return PTR_ERR(outp);
2026
2027                 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
2028                         outp->flush_disable = true;
2029                         atom->flush_disable = true;
2030                 }
2031                 outp->clr.ctrl = true;
2032                 atom->lock_core = true;
2033         }
2034
2035         return 0;
2036 }
2037
2038 static int
2039 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
2040                                 struct drm_connector_state *connector_state)
2041 {
2042         struct drm_encoder *encoder = connector_state->best_encoder;
2043         struct drm_crtc_state *new_crtc_state;
2044         struct drm_crtc *crtc;
2045         struct nv50_outp_atom *outp;
2046
2047         if (!(crtc = connector_state->crtc))
2048                 return 0;
2049
2050         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2051         if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2052                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2053                 if (IS_ERR(outp))
2054                         return PTR_ERR(outp);
2055
2056                 outp->set.ctrl = true;
2057                 atom->lock_core = true;
2058         }
2059
2060         return 0;
2061 }
2062
2063 static int
2064 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
2065 {
2066         struct nv50_atom *atom = nv50_atom(state);
2067         struct drm_connector_state *old_connector_state, *new_connector_state;
2068         struct drm_connector *connector;
2069         struct drm_crtc_state *new_crtc_state;
2070         struct drm_crtc *crtc;
2071         int ret, i;
2072
2073         /* We need to handle colour management on a per-plane basis. */
2074         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2075                 if (new_crtc_state->color_mgmt_changed) {
2076                         ret = drm_atomic_add_affected_planes(state, crtc);
2077                         if (ret)
2078                                 return ret;
2079                 }
2080         }
2081
2082         ret = drm_atomic_helper_check(dev, state);
2083         if (ret)
2084                 return ret;
2085
2086         for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
2087                 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
2088                 if (ret)
2089                         return ret;
2090
2091                 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
2092                 if (ret)
2093                         return ret;
2094         }
2095
2096         return 0;
2097 }
2098
2099 static void
2100 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
2101 {
2102         struct nv50_atom *atom = nv50_atom(state);
2103         struct nv50_outp_atom *outp, *outt;
2104
2105         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2106                 list_del(&outp->head);
2107                 kfree(outp);
2108         }
2109
2110         drm_atomic_state_default_clear(state);
2111 }
2112
2113 static void
2114 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
2115 {
2116         struct nv50_atom *atom = nv50_atom(state);
2117         drm_atomic_state_default_release(&atom->state);
2118         kfree(atom);
2119 }
2120
2121 static struct drm_atomic_state *
2122 nv50_disp_atomic_state_alloc(struct drm_device *dev)
2123 {
2124         struct nv50_atom *atom;
2125         if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
2126             drm_atomic_state_init(dev, &atom->state) < 0) {
2127                 kfree(atom);
2128                 return NULL;
2129         }
2130         INIT_LIST_HEAD(&atom->outp);
2131         return &atom->state;
2132 }
2133
2134 static const struct drm_mode_config_funcs
2135 nv50_disp_func = {
2136         .fb_create = nouveau_user_framebuffer_create,
2137         .output_poll_changed = nouveau_fbcon_output_poll_changed,
2138         .atomic_check = nv50_disp_atomic_check,
2139         .atomic_commit = nv50_disp_atomic_commit,
2140         .atomic_state_alloc = nv50_disp_atomic_state_alloc,
2141         .atomic_state_clear = nv50_disp_atomic_state_clear,
2142         .atomic_state_free = nv50_disp_atomic_state_free,
2143 };
2144
2145 /******************************************************************************
2146  * Init
2147  *****************************************************************************/
2148
2149 void
2150 nv50_display_fini(struct drm_device *dev)
2151 {
2152         struct nouveau_encoder *nv_encoder;
2153         struct drm_encoder *encoder;
2154         struct drm_plane *plane;
2155
2156         drm_for_each_plane(plane, dev) {
2157                 struct nv50_wndw *wndw = nv50_wndw(plane);
2158                 if (plane->funcs != &nv50_wndw)
2159                         continue;
2160                 nv50_wndw_fini(wndw);
2161         }
2162
2163         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2164                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2165                         nv_encoder = nouveau_encoder(encoder);
2166                         nv50_mstm_fini(nv_encoder->dp.mstm);
2167                 }
2168         }
2169 }
2170
2171 int
2172 nv50_display_init(struct drm_device *dev)
2173 {
2174         struct nv50_core *core = nv50_disp(dev)->core;
2175         struct drm_encoder *encoder;
2176         struct drm_plane *plane;
2177
2178         core->func->init(core);
2179
2180         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2181                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2182                         struct nouveau_encoder *nv_encoder =
2183                                 nouveau_encoder(encoder);
2184                         nv50_mstm_init(nv_encoder->dp.mstm);
2185                 }
2186         }
2187
2188         drm_for_each_plane(plane, dev) {
2189                 struct nv50_wndw *wndw = nv50_wndw(plane);
2190                 if (plane->funcs != &nv50_wndw)
2191                         continue;
2192                 nv50_wndw_init(wndw);
2193         }
2194
2195         return 0;
2196 }
2197
2198 void
2199 nv50_display_destroy(struct drm_device *dev)
2200 {
2201         struct nv50_disp *disp = nv50_disp(dev);
2202
2203         nv50_core_del(&disp->core);
2204
2205         nouveau_bo_unmap(disp->sync);
2206         if (disp->sync)
2207                 nouveau_bo_unpin(disp->sync);
2208         nouveau_bo_ref(NULL, &disp->sync);
2209
2210         nouveau_display(dev)->priv = NULL;
2211         kfree(disp);
2212 }
2213
2214 int
2215 nv50_display_create(struct drm_device *dev)
2216 {
2217         struct nvif_device *device = &nouveau_drm(dev)->client.device;
2218         struct nouveau_drm *drm = nouveau_drm(dev);
2219         struct dcb_table *dcb = &drm->vbios.dcb;
2220         struct drm_connector *connector, *tmp;
2221         struct nv50_disp *disp;
2222         struct dcb_output *dcbe;
2223         int crtcs, ret, i;
2224
2225         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2226         if (!disp)
2227                 return -ENOMEM;
2228
2229         mutex_init(&disp->mutex);
2230
2231         nouveau_display(dev)->priv = disp;
2232         nouveau_display(dev)->dtor = nv50_display_destroy;
2233         nouveau_display(dev)->init = nv50_display_init;
2234         nouveau_display(dev)->fini = nv50_display_fini;
2235         disp->disp = &nouveau_display(dev)->disp;
2236         dev->mode_config.funcs = &nv50_disp_func;
2237         dev->driver->driver_features |= DRIVER_PREFER_XBGR_30BPP;
2238
2239         /* small shared memory area we use for notifiers and semaphores */
2240         ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2241                              0, 0x0000, NULL, NULL, &disp->sync);
2242         if (!ret) {
2243                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
2244                 if (!ret) {
2245                         ret = nouveau_bo_map(disp->sync);
2246                         if (ret)
2247                                 nouveau_bo_unpin(disp->sync);
2248                 }
2249                 if (ret)
2250                         nouveau_bo_ref(NULL, &disp->sync);
2251         }
2252
2253         if (ret)
2254                 goto out;
2255
2256         /* allocate master evo channel */
2257         ret = nv50_core_new(drm, &disp->core);
2258         if (ret)
2259                 goto out;
2260
2261         /* create crtc objects to represent the hw heads */
2262         if (disp->disp->object.oclass >= GV100_DISP)
2263                 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff;
2264         else
2265         if (disp->disp->object.oclass >= GF110_DISP)
2266                 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
2267         else
2268                 crtcs = 0x3;
2269
2270         for (i = 0; i < fls(crtcs); i++) {
2271                 if (!(crtcs & (1 << i)))
2272                         continue;
2273                 ret = nv50_head_create(dev, i);
2274                 if (ret)
2275                         goto out;
2276         }
2277
2278         /* create encoder/connector objects based on VBIOS DCB table */
2279         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2280                 connector = nouveau_connector_create(dev, dcbe->connector);
2281                 if (IS_ERR(connector))
2282                         continue;
2283
2284                 if (dcbe->location == DCB_LOC_ON_CHIP) {
2285                         switch (dcbe->type) {
2286                         case DCB_OUTPUT_TMDS:
2287                         case DCB_OUTPUT_LVDS:
2288                         case DCB_OUTPUT_DP:
2289                                 ret = nv50_sor_create(connector, dcbe);
2290                                 break;
2291                         case DCB_OUTPUT_ANALOG:
2292                                 ret = nv50_dac_create(connector, dcbe);
2293                                 break;
2294                         default:
2295                                 ret = -ENODEV;
2296                                 break;
2297                         }
2298                 } else {
2299                         ret = nv50_pior_create(connector, dcbe);
2300                 }
2301
2302                 if (ret) {
2303                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2304                                      dcbe->location, dcbe->type,
2305                                      ffs(dcbe->or) - 1, ret);
2306                         ret = 0;
2307                 }
2308         }
2309
2310         /* cull any connectors we created that don't have an encoder */
2311         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2312                 if (connector->encoder_ids[0])
2313                         continue;
2314
2315                 NV_WARN(drm, "%s has no encoders, removing\n",
2316                         connector->name);
2317                 connector->funcs->destroy(connector);
2318         }
2319
2320         /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
2321         dev->vblank_disable_immediate = true;
2322
2323 out:
2324         if (ret)
2325                 nv50_display_destroy(dev);
2326         return ret;
2327 }