drivers/gpu/drm/mxsfb/mxsfb_kms.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2016 Marek Vasut <marex@denx.de>
   4  *
   5  * This code is based on drivers/video/fbdev/mxsfb.c :
   6  * Copyright (C) 2010 Juergen Beisert, Pengutronix
   7  * Copyright (C) 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
   8  * Copyright (C) 2008 Embedded Alley Solutions, Inc All Rights Reserved.
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/io.h>
  13 #include <linux/iopoll.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/spinlock.h>
  16
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_atomic_helper.h>
  19 #include <drm/drm_bridge.h>
  20 #include <drm/drm_crtc.h>
  21 #include <drm/drm_encoder.h>
  22 #include <drm/drm_fb_cma_helper.h>
  23 #include <drm/drm_fourcc.h>
  24 #include <drm/drm_gem_cma_helper.h>
  25 #include <drm/drm_gem_framebuffer_helper.h>
  26 #include <drm/drm_plane.h>
  27 #include <drm/drm_plane_helper.h>
  28 #include <drm/drm_vblank.h>
  29
  30 #include "mxsfb_drv.h"
  31 #include "mxsfb_regs.h"
  32
  33 /* 1 second delay should be plenty of time for block reset */
  34 #define RESET_TIMEOUT           1000000
  35
  36 /* -----------------------------------------------------------------------------
  37  * CRTC
  38  */
  39
  40 static u32 set_hsync_pulse_width(struct mxsfb_drm_private *mxsfb, u32 val)
  41 {
  42         return (val & mxsfb->devdata->hs_wdth_mask) <<
  43                 mxsfb->devdata->hs_wdth_shift;
  44 }
  45
  46 /*
  47  * Setup the MXSFB registers for decoding the pixels out of the framebuffer and
  48  * outputting them on the bus.
  49  */
  50 static void mxsfb_set_formats(struct mxsfb_drm_private *mxsfb)
  51 {
  52         struct drm_device *drm = mxsfb->drm;
  53         const u32 format = mxsfb->crtc.primary->state->fb->format->format;
  54         u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
  55         u32 ctrl, ctrl1;
  56
  57         if (mxsfb->connector->display_info.num_bus_formats)
  58                 bus_format = mxsfb->connector->display_info.bus_formats[0];
  59
  60         DRM_DEV_DEBUG_DRIVER(drm->dev, "Using bus_format: 0x%08X\n",
  61                              bus_format);
  62
  63         ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER;
  64
  65         /* CTRL1 contains IRQ config and status bits, preserve those. */
  66         ctrl1 = readl(mxsfb->base + LCDC_CTRL1);
  67         ctrl1 &= CTRL1_CUR_FRAME_DONE_IRQ_EN | CTRL1_CUR_FRAME_DONE_IRQ;
  68
  69         switch (format) {
  70         case DRM_FORMAT_RGB565:
  71                 dev_dbg(drm->dev, "Setting up RGB565 mode\n");
  72                 ctrl |= CTRL_WORD_LENGTH_16;
  73                 ctrl1 |= CTRL1_SET_BYTE_PACKAGING(0xf);
  74                 break;
  75         case DRM_FORMAT_XRGB8888:
  76                 dev_dbg(drm->dev, "Setting up XRGB8888 mode\n");
  77                 ctrl |= CTRL_WORD_LENGTH_24;
  78                 /* Do not use packed pixels = one pixel per word instead. */
  79                 ctrl1 |= CTRL1_SET_BYTE_PACKAGING(0x7);
  80                 break;
  81         }
  82
  83         switch (bus_format) {
  84         case MEDIA_BUS_FMT_RGB565_1X16:
  85                 ctrl |= CTRL_BUS_WIDTH_16;
  86                 break;
  87         case MEDIA_BUS_FMT_RGB666_1X18:
  88                 ctrl |= CTRL_BUS_WIDTH_18;
  89                 break;
  90         case MEDIA_BUS_FMT_RGB888_1X24:
  91                 ctrl |= CTRL_BUS_WIDTH_24;
  92                 break;
  93         default:
  94                 dev_err(drm->dev, "Unknown media bus format %d\n", bus_format);
  95                 break;
  96         }
  97
  98         writel(ctrl1, mxsfb->base + LCDC_CTRL1);
  99         writel(ctrl, mxsfb->base + LCDC_CTRL);
 100 }
 101
 102 static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb)
 103 {
 104         u32 reg;
 105
 106         if (mxsfb->clk_disp_axi)
 107                 clk_prepare_enable(mxsfb->clk_disp_axi);
 108         clk_prepare_enable(mxsfb->clk);
 109
 110         /* Increase number of outstanding requests on all supported IPs */
 111         if (mxsfb->devdata->has_ctrl2) {
 112                 reg = readl(mxsfb->base + LCDC_V4_CTRL2);
 113                 reg &= ~CTRL2_SET_OUTSTANDING_REQS_MASK;
 114                 reg |= CTRL2_SET_OUTSTANDING_REQS_16;
 115                 writel(reg, mxsfb->base + LCDC_V4_CTRL2);
 116         }
 117
 118         /* If it was disabled, re-enable the mode again */
 119         writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_SET);
 120
 121         /* Enable the SYNC signals first, then the DMA engine */
 122         reg = readl(mxsfb->base + LCDC_VDCTRL4);
 123         reg |= VDCTRL4_SYNC_SIGNALS_ON;
 124         writel(reg, mxsfb->base + LCDC_VDCTRL4);
 125
 126         /*
 127          * Enable recovery on underflow.
 128          *
 129          * There is some sort of corner case behavior of the controller,
 130          * which could rarely be triggered at least on i.MX6SX connected
 131          * to 800x480 DPI panel and i.MX8MM connected to DPI->DSI->LVDS
 132          * bridged 1920x1080 panel (and likely on other setups too), where
 133          * the image on the panel shifts to the right and wraps around.
 134          * This happens either when the controller is enabled on boot or
 135          * even later during run time. The condition does not correct
 136          * itself automatically, i.e. the display image remains shifted.
 137          *
 138          * It seems this problem is known and is due to sporadic underflows
 139          * of the LCDIF FIFO. While the LCDIF IP does have underflow/overflow
 140          * IRQs, neither of the IRQs trigger and neither IRQ status bit is
 141          * asserted when this condition occurs.
 142          *
 143          * All known revisions of the LCDIF IP have CTRL1 RECOVER_ON_UNDERFLOW
 144          * bit, which is described in the reference manual since i.MX23 as
 145          * "
 146          *   Set this bit to enable the LCDIF block to recover in the next
 147          *   field/frame if there was an underflow in the current field/frame.
 148          * "
 149          * Enable this bit to mitigate the sporadic underflows.
 150          */
 151         reg = readl(mxsfb->base + LCDC_CTRL1);
 152         reg |= CTRL1_RECOVER_ON_UNDERFLOW;
 153         writel(reg, mxsfb->base + LCDC_CTRL1);
 154
 155         writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_SET);
 156 }
 157
 158 static void mxsfb_disable_controller(struct mxsfb_drm_private *mxsfb)
 159 {
 160         u32 reg;
 161
 162         /*
 163          * Even if we disable the controller here, it will still continue
 164          * until its FIFOs are running out of data
 165          */
 166         writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_CLR);
 167
 168         readl_poll_timeout(mxsfb->base + LCDC_CTRL, reg, !(reg & CTRL_RUN),
 169                            0, 1000);
 170
 171         reg = readl(mxsfb->base + LCDC_VDCTRL4);
 172         reg &= ~VDCTRL4_SYNC_SIGNALS_ON;
 173         writel(reg, mxsfb->base + LCDC_VDCTRL4);
 174
 175         clk_disable_unprepare(mxsfb->clk);
 176         if (mxsfb->clk_disp_axi)
 177                 clk_disable_unprepare(mxsfb->clk_disp_axi);
 178 }
 179
 180 /*
 181  * Clear the bit and poll it cleared.  This is usually called with
 182  * a reset address and mask being either SFTRST(bit 31) or CLKGATE
 183  * (bit 30).
 184  */
 185 static int clear_poll_bit(void __iomem *addr, u32 mask)
 186 {
 187         u32 reg;
 188
 189         writel(mask, addr + REG_CLR);
 190         return readl_poll_timeout(addr, reg, !(reg & mask), 0, RESET_TIMEOUT);
 191 }
 192
 193 static int mxsfb_reset_block(struct mxsfb_drm_private *mxsfb)
 194 {
 195         int ret;
 196
 197         ret = clear_poll_bit(mxsfb->base + LCDC_CTRL, CTRL_SFTRST);
 198         if (ret)
 199                 return ret;
 200
 201         writel(CTRL_CLKGATE, mxsfb->base + LCDC_CTRL + REG_CLR);
 202
 203         ret = clear_poll_bit(mxsfb->base + LCDC_CTRL, CTRL_SFTRST);
 204         if (ret)
 205                 return ret;
 206
 207         return clear_poll_bit(mxsfb->base + LCDC_CTRL, CTRL_CLKGATE);
 208 }
 209
 210 static dma_addr_t mxsfb_get_fb_paddr(struct drm_plane *plane)
 211 {
 212         struct drm_framebuffer *fb = plane->state->fb;
 213         struct drm_gem_cma_object *gem;
 214
 215         if (!fb)
 216                 return 0;
 217
 218         gem = drm_fb_cma_get_gem_obj(fb, 0);
 219         if (!gem)
 220                 return 0;
 221
 222         return gem->paddr;
 223 }
 224
 225 static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb)
 226 {
 227         struct drm_device *drm = mxsfb->crtc.dev;
 228         struct drm_display_mode *m = &mxsfb->crtc.state->adjusted_mode;
 229         u32 bus_flags = mxsfb->connector->display_info.bus_flags;
 230         u32 vdctrl0, vsync_pulse_len, hsync_pulse_len;
 231         int err;
 232
 233         /*
 234          * It seems, you can't re-program the controller if it is still
 235          * running. This may lead to shifted pictures (FIFO issue?), so
 236          * first stop the controller and drain its FIFOs.
 237          */
 238
 239         /* Mandatory eLCDIF reset as per the Reference Manual */
 240         err = mxsfb_reset_block(mxsfb);
 241         if (err)
 242                 return;
 243
 244         /* Clear the FIFOs */
 245         writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_SET);
 246         readl(mxsfb->base + LCDC_CTRL1);
 247         writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_CLR);
 248         readl(mxsfb->base + LCDC_CTRL1);
 249
 250         if (mxsfb->devdata->has_overlay)
 251                 writel(0, mxsfb->base + LCDC_AS_CTRL);
 252
 253         mxsfb_set_formats(mxsfb);
 254
 255         clk_set_rate(mxsfb->clk, m->crtc_clock * 1000);
 256
 257         if (mxsfb->bridge && mxsfb->bridge->timings)
 258                 bus_flags = mxsfb->bridge->timings->input_bus_flags;
 259
 260         DRM_DEV_DEBUG_DRIVER(drm->dev, "Pixel clock: %dkHz (actual: %dkHz)\n",
 261                              m->crtc_clock,
 262                              (int)(clk_get_rate(mxsfb->clk) / 1000));
 263         DRM_DEV_DEBUG_DRIVER(drm->dev, "Connector bus_flags: 0x%08X\n",
 264                              bus_flags);
 265         DRM_DEV_DEBUG_DRIVER(drm->dev, "Mode flags: 0x%08X\n", m->flags);
 266
 267         writel(TRANSFER_COUNT_SET_VCOUNT(m->crtc_vdisplay) |
 268                TRANSFER_COUNT_SET_HCOUNT(m->crtc_hdisplay),
 269                mxsfb->base + mxsfb->devdata->transfer_count);
 270
 271         vsync_pulse_len = m->crtc_vsync_end - m->crtc_vsync_start;
 272
 273         vdctrl0 = VDCTRL0_ENABLE_PRESENT |      /* Always in DOTCLOCK mode */
 274                   VDCTRL0_VSYNC_PERIOD_UNIT |
 275                   VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
 276                   VDCTRL0_SET_VSYNC_PULSE_WIDTH(vsync_pulse_len);
 277         if (m->flags & DRM_MODE_FLAG_PHSYNC)
 278                 vdctrl0 |= VDCTRL0_HSYNC_ACT_HIGH;
 279         if (m->flags & DRM_MODE_FLAG_PVSYNC)
 280                 vdctrl0 |= VDCTRL0_VSYNC_ACT_HIGH;
 281         /* Make sure Data Enable is high active by default */
 282         if (!(bus_flags & DRM_BUS_FLAG_DE_LOW))
 283                 vdctrl0 |= VDCTRL0_ENABLE_ACT_HIGH;
 284         /*
 285          * DRM_BUS_FLAG_PIXDATA_DRIVE_ defines are controller centric,
 286          * controllers VDCTRL0_DOTCLK is display centric.
 287          * Drive on positive edge       -> display samples on falling edge
 288          * DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE -> VDCTRL0_DOTCLK_ACT_FALLING
 289          */
 290         if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE)
 291                 vdctrl0 |= VDCTRL0_DOTCLK_ACT_FALLING;
 292
 293         writel(vdctrl0, mxsfb->base + LCDC_VDCTRL0);
 294
 295         /* Frame length in lines. */
 296         writel(m->crtc_vtotal, mxsfb->base + LCDC_VDCTRL1);
 297
 298         /* Line length in units of clocks or pixels. */
 299         hsync_pulse_len = m->crtc_hsync_end - m->crtc_hsync_start;
 300         writel(set_hsync_pulse_width(mxsfb, hsync_pulse_len) |
 301                VDCTRL2_SET_HSYNC_PERIOD(m->crtc_htotal),
 302                mxsfb->base + LCDC_VDCTRL2);
 303
 304         writel(SET_HOR_WAIT_CNT(m->crtc_htotal - m->crtc_hsync_start) |
 305                SET_VERT_WAIT_CNT(m->crtc_vtotal - m->crtc_vsync_start),
 306                mxsfb->base + LCDC_VDCTRL3);
 307
 308         writel(SET_DOTCLK_H_VALID_DATA_CNT(m->hdisplay),
 309                mxsfb->base + LCDC_VDCTRL4);
 310 }
 311
 312 static int mxsfb_crtc_atomic_check(struct drm_crtc *crtc,
 313                                    struct drm_crtc_state *state)
 314 {
 315         bool has_primary = state->plane_mask &
 316                            drm_plane_mask(crtc->primary);
 317
 318         /* The primary plane has to be enabled when the CRTC is active. */
 319         if (state->active && !has_primary)
 320                 return -EINVAL;
 321
 322         /* TODO: Is this needed ? */
 323         return drm_atomic_add_affected_planes(state->state, crtc);
 324 }
 325
 326 static void mxsfb_crtc_atomic_flush(struct drm_crtc *crtc,
 327                                     struct drm_crtc_state *old_state)
 328 {
 329         struct drm_pending_vblank_event *event;
 330
 331         event = crtc->state->event;
 332         crtc->state->event = NULL;
 333
 334         if (!event)
 335                 return;
 336
 337         spin_lock_irq(&crtc->dev->event_lock);
 338         if (drm_crtc_vblank_get(crtc) == 0)
 339                 drm_crtc_arm_vblank_event(crtc, event);
 340         else
 341                 drm_crtc_send_vblank_event(crtc, event);
 342         spin_unlock_irq(&crtc->dev->event_lock);
 343 }
 344
 345 static void mxsfb_crtc_atomic_enable(struct drm_crtc *crtc,
 346                                      struct drm_crtc_state *old_state)
 347 {
 348         struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev);
 349         struct drm_device *drm = mxsfb->drm;
 350         dma_addr_t paddr;
 351
 352         pm_runtime_get_sync(drm->dev);
 353         mxsfb_enable_axi_clk(mxsfb);
 354
 355         drm_crtc_vblank_on(crtc);
 356
 357         mxsfb_crtc_mode_set_nofb(mxsfb);
 358
 359         /* Write cur_buf as well to avoid an initial corrupt frame */
 360         paddr = mxsfb_get_fb_paddr(crtc->primary);
 361         if (paddr) {
 362                 writel(paddr, mxsfb->base + mxsfb->devdata->cur_buf);
 363                 writel(paddr, mxsfb->base + mxsfb->devdata->next_buf);
 364         }
 365
 366         mxsfb_enable_controller(mxsfb);
 367 }
 368
 369 static void mxsfb_crtc_atomic_disable(struct drm_crtc *crtc,
 370                                       struct drm_crtc_state *old_state)
 371 {
 372         struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev);
 373         struct drm_device *drm = mxsfb->drm;
 374         struct drm_pending_vblank_event *event;
 375
 376         mxsfb_disable_controller(mxsfb);
 377
 378         spin_lock_irq(&drm->event_lock);
 379         event = crtc->state->event;
 380         if (event) {
 381                 crtc->state->event = NULL;
 382                 drm_crtc_send_vblank_event(crtc, event);
 383         }
 384         spin_unlock_irq(&drm->event_lock);
 385
 386         drm_crtc_vblank_off(crtc);
 387
 388         mxsfb_disable_axi_clk(mxsfb);
 389         pm_runtime_put_sync(drm->dev);
 390 }
 391
 392 static int mxsfb_crtc_enable_vblank(struct drm_crtc *crtc)
 393 {
 394         struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev);
 395
 396         /* Clear and enable VBLANK IRQ */
 397         writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR);
 398         writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_SET);
 399
 400         return 0;
 401 }
 402
 403 static void mxsfb_crtc_disable_vblank(struct drm_crtc *crtc)
 404 {
 405         struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev);
 406
 407         /* Disable and clear VBLANK IRQ */
 408         writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR);
 409         writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR);
 410 }
 411
 412 static const struct drm_crtc_helper_funcs mxsfb_crtc_helper_funcs = {
 413         .atomic_check = mxsfb_crtc_atomic_check,
 414         .atomic_flush = mxsfb_crtc_atomic_flush,
 415         .atomic_enable = mxsfb_crtc_atomic_enable,
 416         .atomic_disable = mxsfb_crtc_atomic_disable,
 417 };
 418
 419 static const struct drm_crtc_funcs mxsfb_crtc_funcs = {
 420         .reset = drm_atomic_helper_crtc_reset,
 421         .destroy = drm_crtc_cleanup,
 422         .set_config = drm_atomic_helper_set_config,
 423         .page_flip = drm_atomic_helper_page_flip,
 424         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 425         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 426         .enable_vblank = mxsfb_crtc_enable_vblank,
 427         .disable_vblank = mxsfb_crtc_disable_vblank,
 428 };
 429
 430 /* -----------------------------------------------------------------------------
 431  * Encoder
 432  */
 433
 434 static const struct drm_encoder_funcs mxsfb_encoder_funcs = {
 435         .destroy = drm_encoder_cleanup,
 436 };
 437
 438 /* -----------------------------------------------------------------------------
 439  * Planes
 440  */
 441
 442 static int mxsfb_plane_atomic_check(struct drm_plane *plane,
 443                                     struct drm_plane_state *plane_state)
 444 {
 445         struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(plane->dev);
 446         struct drm_crtc_state *crtc_state;
 447
 448         crtc_state = drm_atomic_get_new_crtc_state(plane_state->state,
 449                                                    &mxsfb->crtc);
 450
 451         return drm_atomic_helper_check_plane_state(plane_state, crtc_state,
 452                                                    DRM_PLANE_HELPER_NO_SCALING,
 453                                                    DRM_PLANE_HELPER_NO_SCALING,
 454                                                    false, true);
 455 }
 456
 457 static void mxsfb_plane_primary_atomic_update(struct drm_plane *plane,
 458                                               struct drm_plane_state *old_pstate)
 459 {
 460         struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(plane->dev);
 461         dma_addr_t paddr;
 462
 463         paddr = mxsfb_get_fb_paddr(plane);
 464         if (paddr)
 465                 writel(paddr, mxsfb->base + mxsfb->devdata->next_buf);
 466 }
 467
 468 static void mxsfb_plane_overlay_atomic_update(struct drm_plane *plane,
 469                                               struct drm_plane_state *old_pstate)
 470 {
 471         struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(plane->dev);
 472         struct drm_plane_state *state = plane->state;
 473         dma_addr_t paddr;
 474         u32 ctrl;
 475
 476         paddr = mxsfb_get_fb_paddr(plane);
 477         if (!paddr) {
 478                 writel(0, mxsfb->base + LCDC_AS_CTRL);
 479                 return;
 480         }
 481
 482         /*
 483          * HACK: The hardware seems to output 64 bytes of data of unknown
 484          * origin, and then to proceed with the framebuffer. Until the reason
 485          * is understood, live with the 16 initial invalid pixels on the first
 486          * line and start 64 bytes within the framebuffer.
 487          */
 488         paddr += 64;
 489
 490         writel(paddr, mxsfb->base + LCDC_AS_NEXT_BUF);
 491
 492         /*
 493          * If the plane was previously disabled, write LCDC_AS_BUF as well to
 494          * provide the first buffer.
 495          */
 496         if (!old_pstate->fb)
 497                 writel(paddr, mxsfb->base + LCDC_AS_BUF);
 498
 499         ctrl = AS_CTRL_AS_ENABLE | AS_CTRL_ALPHA(255);
 500
 501         switch (state->fb->format->format) {
 502         case DRM_FORMAT_XRGB4444:
 503                 ctrl |= AS_CTRL_FORMAT_RGB444 | AS_CTRL_ALPHA_CTRL_OVERRIDE;
 504                 break;
 505         case DRM_FORMAT_ARGB4444:
 506                 ctrl |= AS_CTRL_FORMAT_ARGB4444 | AS_CTRL_ALPHA_CTRL_EMBEDDED;
 507                 break;
 508         case DRM_FORMAT_XRGB1555:
 509                 ctrl |= AS_CTRL_FORMAT_RGB555 | AS_CTRL_ALPHA_CTRL_OVERRIDE;
 510                 break;
 511         case DRM_FORMAT_ARGB1555:
 512                 ctrl |= AS_CTRL_FORMAT_ARGB1555 | AS_CTRL_ALPHA_CTRL_EMBEDDED;
 513                 break;
 514         case DRM_FORMAT_RGB565:
 515                 ctrl |= AS_CTRL_FORMAT_RGB565 | AS_CTRL_ALPHA_CTRL_OVERRIDE;
 516                 break;
 517         case DRM_FORMAT_XRGB8888:
 518                 ctrl |= AS_CTRL_FORMAT_RGB888 | AS_CTRL_ALPHA_CTRL_OVERRIDE;
 519                 break;
 520         case DRM_FORMAT_ARGB8888:
 521                 ctrl |= AS_CTRL_FORMAT_ARGB8888 | AS_CTRL_ALPHA_CTRL_EMBEDDED;
 522                 break;
 523         }
 524
 525         writel(ctrl, mxsfb->base + LCDC_AS_CTRL);
 526 }
 527
 528 static bool mxsfb_format_mod_supported(struct drm_plane *plane,
 529                                        uint32_t format,
 530                                        uint64_t modifier)
 531 {
 532         return modifier == DRM_FORMAT_MOD_LINEAR;
 533 }
 534
 535 static const struct drm_plane_helper_funcs mxsfb_plane_primary_helper_funcs = {
 536         .prepare_fb = drm_gem_fb_prepare_fb,
 537         .atomic_check = mxsfb_plane_atomic_check,
 538         .atomic_update = mxsfb_plane_primary_atomic_update,
 539 };
 540
 541 static const struct drm_plane_helper_funcs mxsfb_plane_overlay_helper_funcs = {
 542         .prepare_fb = drm_gem_fb_prepare_fb,
 543         .atomic_check = mxsfb_plane_atomic_check,
 544         .atomic_update = mxsfb_plane_overlay_atomic_update,
 545 };
 546
 547 static const struct drm_plane_funcs mxsfb_plane_funcs = {
 548         .format_mod_supported   = mxsfb_format_mod_supported,
 549         .update_plane           = drm_atomic_helper_update_plane,
 550         .disable_plane          = drm_atomic_helper_disable_plane,
 551         .destroy                = drm_plane_cleanup,
 552         .reset                  = drm_atomic_helper_plane_reset,
 553         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 554         .atomic_destroy_state   = drm_atomic_helper_plane_destroy_state,
 555 };
 556
 557 static const uint32_t mxsfb_primary_plane_formats[] = {
 558         DRM_FORMAT_RGB565,
 559         DRM_FORMAT_XRGB8888,
 560 };
 561
 562 static const uint32_t mxsfb_overlay_plane_formats[] = {
 563         DRM_FORMAT_XRGB4444,
 564         DRM_FORMAT_ARGB4444,
 565         DRM_FORMAT_XRGB1555,
 566         DRM_FORMAT_ARGB1555,
 567         DRM_FORMAT_RGB565,
 568         DRM_FORMAT_XRGB8888,
 569         DRM_FORMAT_ARGB8888,
 570 };
 571
 572 static const uint64_t mxsfb_modifiers[] = {
 573         DRM_FORMAT_MOD_LINEAR,
 574         DRM_FORMAT_MOD_INVALID
 575 };
 576
 577 /* -----------------------------------------------------------------------------
 578  * Initialization
 579  */
 580
 581 int mxsfb_kms_init(struct mxsfb_drm_private *mxsfb)
 582 {
 583         struct drm_encoder *encoder = &mxsfb->encoder;
 584         struct drm_crtc *crtc = &mxsfb->crtc;
 585         int ret;
 586
 587         drm_plane_helper_add(&mxsfb->planes.primary,
 588                              &mxsfb_plane_primary_helper_funcs);
 589         ret = drm_universal_plane_init(mxsfb->drm, &mxsfb->planes.primary, 1,
 590                                        &mxsfb_plane_funcs,
 591                                        mxsfb_primary_plane_formats,
 592                                        ARRAY_SIZE(mxsfb_primary_plane_formats),
 593                                        mxsfb_modifiers, DRM_PLANE_TYPE_PRIMARY,
 594                                        NULL);
 595         if (ret)
 596                 return ret;
 597
 598         if (mxsfb->devdata->has_overlay) {
 599                 drm_plane_helper_add(&mxsfb->planes.overlay,
 600                                      &mxsfb_plane_overlay_helper_funcs);
 601                 ret = drm_universal_plane_init(mxsfb->drm,
 602                                                &mxsfb->planes.overlay, 1,
 603                                                &mxsfb_plane_funcs,
 604                                                mxsfb_overlay_plane_formats,
 605                                                ARRAY_SIZE(mxsfb_overlay_plane_formats),
 606                                                mxsfb_modifiers, DRM_PLANE_TYPE_OVERLAY,
 607                                                NULL);
 608                 if (ret)
 609                         return ret;
 610         }
 611
 612         drm_crtc_helper_add(crtc, &mxsfb_crtc_helper_funcs);
 613         ret = drm_crtc_init_with_planes(mxsfb->drm, crtc,
 614                                         &mxsfb->planes.primary, NULL,
 615                                         &mxsfb_crtc_funcs, NULL);
 616         if (ret)
 617                 return ret;
 618
 619         encoder->possible_crtcs = drm_crtc_mask(crtc);
 620         return drm_encoder_init(mxsfb->drm, encoder, &mxsfb_encoder_funcs,
 621                                 DRM_MODE_ENCODER_NONE, NULL);
 622 }