1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
10 #include "msm_fence.h"
11 #include "msm_gpu_trace.h"
12 #include "adreno/adreno_gpu.h"
14 #include <generated/utsrelease.h>
15 #include <linux/string_helpers.h>
16 #include <linux/devcoredump.h>
17 #include <linux/sched/task.h>
23 static int enable_pwrrail(struct msm_gpu *gpu)
25 struct drm_device *dev = gpu->dev;
29 ret = regulator_enable(gpu->gpu_reg);
31 DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_reg': %d\n", ret);
37 ret = regulator_enable(gpu->gpu_cx);
39 DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_cx': %d\n", ret);
47 static int disable_pwrrail(struct msm_gpu *gpu)
50 regulator_disable(gpu->gpu_cx);
52 regulator_disable(gpu->gpu_reg);
56 static int enable_clk(struct msm_gpu *gpu)
58 if (gpu->core_clk && gpu->fast_rate)
59 clk_set_rate(gpu->core_clk, gpu->fast_rate);
61 /* Set the RBBM timer rate to 19.2Mhz */
62 if (gpu->rbbmtimer_clk)
63 clk_set_rate(gpu->rbbmtimer_clk, 19200000);
65 return clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks);
68 static int disable_clk(struct msm_gpu *gpu)
70 clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks);
73 * Set the clock to a deliberately low rate. On older targets the clock
74 * speed had to be non zero to avoid problems. On newer targets this
75 * will be rounded down to zero anyway so it all works out.
78 clk_set_rate(gpu->core_clk, 27000000);
80 if (gpu->rbbmtimer_clk)
81 clk_set_rate(gpu->rbbmtimer_clk, 0);
86 static int enable_axi(struct msm_gpu *gpu)
88 return clk_prepare_enable(gpu->ebi1_clk);
91 static int disable_axi(struct msm_gpu *gpu)
93 clk_disable_unprepare(gpu->ebi1_clk);
97 int msm_gpu_pm_resume(struct msm_gpu *gpu)
101 DBG("%s", gpu->name);
102 trace_msm_gpu_resume(0);
104 ret = enable_pwrrail(gpu);
108 ret = enable_clk(gpu);
112 ret = enable_axi(gpu);
116 msm_devfreq_resume(gpu);
118 gpu->needs_hw_init = true;
123 int msm_gpu_pm_suspend(struct msm_gpu *gpu)
127 DBG("%s", gpu->name);
128 trace_msm_gpu_suspend(0);
130 msm_devfreq_suspend(gpu);
132 ret = disable_axi(gpu);
136 ret = disable_clk(gpu);
140 ret = disable_pwrrail(gpu);
144 gpu->suspend_count++;
149 int msm_gpu_hw_init(struct msm_gpu *gpu)
153 WARN_ON(!mutex_is_locked(&gpu->lock));
155 if (!gpu->needs_hw_init)
158 disable_irq(gpu->irq);
159 ret = gpu->funcs->hw_init(gpu);
161 gpu->needs_hw_init = false;
162 enable_irq(gpu->irq);
167 #ifdef CONFIG_DEV_COREDUMP
168 static ssize_t msm_gpu_devcoredump_read(char *buffer, loff_t offset,
169 size_t count, void *data, size_t datalen)
171 struct msm_gpu *gpu = data;
172 struct drm_print_iterator iter;
173 struct drm_printer p;
174 struct msm_gpu_state *state;
176 state = msm_gpu_crashstate_get(gpu);
185 p = drm_coredump_printer(&iter);
187 drm_printf(&p, "---\n");
188 drm_printf(&p, "kernel: " UTS_RELEASE "\n");
189 drm_printf(&p, "module: " KBUILD_MODNAME "\n");
190 drm_printf(&p, "time: %lld.%09ld\n",
191 state->time.tv_sec, state->time.tv_nsec);
193 drm_printf(&p, "comm: %s\n", state->comm);
195 drm_printf(&p, "cmdline: %s\n", state->cmd);
197 gpu->funcs->show(gpu, state, &p);
199 msm_gpu_crashstate_put(gpu);
201 return count - iter.remain;
204 static void msm_gpu_devcoredump_free(void *data)
206 struct msm_gpu *gpu = data;
208 msm_gpu_crashstate_put(gpu);
211 static void msm_gpu_crashstate_get_bo(struct msm_gpu_state *state,
212 struct msm_gem_object *obj, u64 iova, u32 flags)
214 struct msm_gpu_state_bo *state_bo = &state->bos[state->nr_bos];
216 /* Don't record write only objects */
217 state_bo->size = obj->base.size;
218 state_bo->iova = iova;
220 /* Only store data for non imported buffer objects marked for read */
221 if ((flags & MSM_SUBMIT_BO_READ) && !obj->base.import_attach) {
224 state_bo->data = kvmalloc(obj->base.size, GFP_KERNEL);
228 msm_gem_lock(&obj->base);
229 ptr = msm_gem_get_vaddr_active(&obj->base);
230 msm_gem_unlock(&obj->base);
232 kvfree(state_bo->data);
233 state_bo->data = NULL;
237 memcpy(state_bo->data, ptr, obj->base.size);
238 msm_gem_put_vaddr(&obj->base);
244 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
245 struct msm_gem_submit *submit, char *comm, char *cmd)
247 struct msm_gpu_state *state;
249 /* Check if the target supports capturing crash state */
250 if (!gpu->funcs->gpu_state_get)
253 /* Only save one crash state at a time */
257 state = gpu->funcs->gpu_state_get(gpu);
258 if (IS_ERR_OR_NULL(state))
261 /* Fill in the additional crash state information */
262 state->comm = kstrdup(comm, GFP_KERNEL);
263 state->cmd = kstrdup(cmd, GFP_KERNEL);
264 state->fault_info = gpu->fault_info;
269 /* count # of buffers to dump: */
270 for (i = 0; i < submit->nr_bos; i++)
271 if (should_dump(submit, i))
273 /* always dump cmd bo's, but don't double count them: */
274 for (i = 0; i < submit->nr_cmds; i++)
275 if (!should_dump(submit, submit->cmd[i].idx))
278 state->bos = kcalloc(nr,
279 sizeof(struct msm_gpu_state_bo), GFP_KERNEL);
281 for (i = 0; state->bos && i < submit->nr_bos; i++) {
282 if (should_dump(submit, i)) {
283 msm_gpu_crashstate_get_bo(state, submit->bos[i].obj,
284 submit->bos[i].iova, submit->bos[i].flags);
288 for (i = 0; state->bos && i < submit->nr_cmds; i++) {
289 int idx = submit->cmd[i].idx;
291 if (!should_dump(submit, submit->cmd[i].idx)) {
292 msm_gpu_crashstate_get_bo(state, submit->bos[idx].obj,
293 submit->bos[idx].iova, submit->bos[idx].flags);
298 /* Set the active crash state to be dumped on failure */
299 gpu->crashstate = state;
301 /* FIXME: Release the crashstate if this errors out? */
302 dev_coredumpm(gpu->dev->dev, THIS_MODULE, gpu, 0, GFP_KERNEL,
303 msm_gpu_devcoredump_read, msm_gpu_devcoredump_free);
306 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
307 struct msm_gem_submit *submit, char *comm, char *cmd)
313 * Hangcheck detection for locked gpu:
316 static struct msm_gem_submit *
317 find_submit(struct msm_ringbuffer *ring, uint32_t fence)
319 struct msm_gem_submit *submit;
322 spin_lock_irqsave(&ring->submit_lock, flags);
323 list_for_each_entry(submit, &ring->submits, node) {
324 if (submit->seqno == fence) {
325 spin_unlock_irqrestore(&ring->submit_lock, flags);
329 spin_unlock_irqrestore(&ring->submit_lock, flags);
334 static void retire_submits(struct msm_gpu *gpu);
336 static void get_comm_cmdline(struct msm_gem_submit *submit, char **comm, char **cmd)
338 struct msm_file_private *ctx = submit->queue->ctx;
339 struct task_struct *task;
341 /* Note that kstrdup will return NULL if argument is NULL: */
342 *comm = kstrdup(ctx->comm, GFP_KERNEL);
343 *cmd = kstrdup(ctx->cmdline, GFP_KERNEL);
345 task = get_pid_task(submit->pid, PIDTYPE_PID);
350 *comm = kstrdup(task->comm, GFP_KERNEL);
353 *cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL);
355 put_task_struct(task);
358 static void recover_worker(struct kthread_work *work)
360 struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work);
361 struct drm_device *dev = gpu->dev;
362 struct msm_drm_private *priv = dev->dev_private;
363 struct msm_gem_submit *submit;
364 struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
365 char *comm = NULL, *cmd = NULL;
368 mutex_lock(&gpu->lock);
370 DRM_DEV_ERROR(dev->dev, "%s: hangcheck recover!\n", gpu->name);
372 submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1);
374 /* Increment the fault counts */
375 submit->queue->faults++;
377 submit->aspace->faults++;
379 get_comm_cmdline(submit, &comm, &cmd);
382 DRM_DEV_ERROR(dev->dev, "%s: offending task: %s (%s)\n",
383 gpu->name, comm, cmd);
385 msm_rd_dump_submit(priv->hangrd, submit,
386 "offending task: %s (%s)", comm, cmd);
388 msm_rd_dump_submit(priv->hangrd, submit, NULL);
392 * We couldn't attribute this fault to any particular context,
393 * so increment the global fault count instead.
395 gpu->global_faults++;
398 /* Record the crash state */
399 pm_runtime_get_sync(&gpu->pdev->dev);
400 msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
401 pm_runtime_put_sync(&gpu->pdev->dev);
407 * Update all the rings with the latest and greatest fence.. this
408 * needs to happen after msm_rd_dump_submit() to ensure that the
409 * bo's referenced by the offending submit are still around.
411 for (i = 0; i < gpu->nr_rings; i++) {
412 struct msm_ringbuffer *ring = gpu->rb[i];
414 uint32_t fence = ring->memptrs->fence;
417 * For the current (faulting?) ring/submit advance the fence by
418 * one more to clear the faulting submit
420 if (ring == cur_ring)
421 ring->memptrs->fence = ++fence;
423 msm_update_fence(ring->fctx, fence);
426 if (msm_gpu_active(gpu)) {
427 /* retire completed submits, plus the one that hung: */
430 pm_runtime_get_sync(&gpu->pdev->dev);
431 gpu->funcs->recover(gpu);
432 pm_runtime_put_sync(&gpu->pdev->dev);
435 * Replay all remaining submits starting with highest priority
438 for (i = 0; i < gpu->nr_rings; i++) {
439 struct msm_ringbuffer *ring = gpu->rb[i];
442 spin_lock_irqsave(&ring->submit_lock, flags);
443 list_for_each_entry(submit, &ring->submits, node)
444 gpu->funcs->submit(gpu, submit);
445 spin_unlock_irqrestore(&ring->submit_lock, flags);
449 mutex_unlock(&gpu->lock);
454 static void fault_worker(struct kthread_work *work)
456 struct msm_gpu *gpu = container_of(work, struct msm_gpu, fault_work);
457 struct msm_gem_submit *submit;
458 struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
459 char *comm = NULL, *cmd = NULL;
461 mutex_lock(&gpu->lock);
463 submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1);
464 if (submit && submit->fault_dumped)
468 get_comm_cmdline(submit, &comm, &cmd);
471 * When we get GPU iova faults, we can get 1000s of them,
472 * but we really only want to log the first one.
474 submit->fault_dumped = true;
477 /* Record the crash state */
478 pm_runtime_get_sync(&gpu->pdev->dev);
479 msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
480 pm_runtime_put_sync(&gpu->pdev->dev);
486 memset(&gpu->fault_info, 0, sizeof(gpu->fault_info));
487 gpu->aspace->mmu->funcs->resume_translation(gpu->aspace->mmu);
489 mutex_unlock(&gpu->lock);
492 static void hangcheck_timer_reset(struct msm_gpu *gpu)
494 struct msm_drm_private *priv = gpu->dev->dev_private;
495 mod_timer(&gpu->hangcheck_timer,
496 round_jiffies_up(jiffies + msecs_to_jiffies(priv->hangcheck_period)));
499 static void hangcheck_handler(struct timer_list *t)
501 struct msm_gpu *gpu = from_timer(gpu, t, hangcheck_timer);
502 struct drm_device *dev = gpu->dev;
503 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
504 uint32_t fence = ring->memptrs->fence;
506 if (fence != ring->hangcheck_fence) {
507 /* some progress has been made.. ya! */
508 ring->hangcheck_fence = fence;
509 } else if (fence_before(fence, ring->fctx->last_fence)) {
510 /* no progress and not done.. hung! */
511 ring->hangcheck_fence = fence;
512 DRM_DEV_ERROR(dev->dev, "%s: hangcheck detected gpu lockup rb %d!\n",
513 gpu->name, ring->id);
514 DRM_DEV_ERROR(dev->dev, "%s: completed fence: %u\n",
516 DRM_DEV_ERROR(dev->dev, "%s: submitted fence: %u\n",
517 gpu->name, ring->fctx->last_fence);
519 kthread_queue_work(gpu->worker, &gpu->recover_work);
522 /* if still more pending work, reset the hangcheck timer: */
523 if (fence_after(ring->fctx->last_fence, ring->hangcheck_fence))
524 hangcheck_timer_reset(gpu);
526 /* workaround for missing irq: */
531 * Performance Counters:
534 /* called under perf_lock */
535 static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs)
537 uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)];
538 int i, n = min(ncntrs, gpu->num_perfcntrs);
540 /* read current values: */
541 for (i = 0; i < gpu->num_perfcntrs; i++)
542 current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg);
545 for (i = 0; i < n; i++)
546 cntrs[i] = current_cntrs[i] - gpu->last_cntrs[i];
548 /* save current values: */
549 for (i = 0; i < gpu->num_perfcntrs; i++)
550 gpu->last_cntrs[i] = current_cntrs[i];
555 static void update_sw_cntrs(struct msm_gpu *gpu)
561 spin_lock_irqsave(&gpu->perf_lock, flags);
562 if (!gpu->perfcntr_active)
566 elapsed = ktime_to_us(ktime_sub(time, gpu->last_sample.time));
568 gpu->totaltime += elapsed;
569 if (gpu->last_sample.active)
570 gpu->activetime += elapsed;
572 gpu->last_sample.active = msm_gpu_active(gpu);
573 gpu->last_sample.time = time;
576 spin_unlock_irqrestore(&gpu->perf_lock, flags);
579 void msm_gpu_perfcntr_start(struct msm_gpu *gpu)
583 pm_runtime_get_sync(&gpu->pdev->dev);
585 spin_lock_irqsave(&gpu->perf_lock, flags);
586 /* we could dynamically enable/disable perfcntr registers too.. */
587 gpu->last_sample.active = msm_gpu_active(gpu);
588 gpu->last_sample.time = ktime_get();
589 gpu->activetime = gpu->totaltime = 0;
590 gpu->perfcntr_active = true;
591 update_hw_cntrs(gpu, 0, NULL);
592 spin_unlock_irqrestore(&gpu->perf_lock, flags);
595 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu)
597 gpu->perfcntr_active = false;
598 pm_runtime_put_sync(&gpu->pdev->dev);
601 /* returns -errno or # of cntrs sampled */
602 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
603 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs)
608 spin_lock_irqsave(&gpu->perf_lock, flags);
610 if (!gpu->perfcntr_active) {
615 *activetime = gpu->activetime;
616 *totaltime = gpu->totaltime;
618 gpu->activetime = gpu->totaltime = 0;
620 ret = update_hw_cntrs(gpu, ncntrs, cntrs);
623 spin_unlock_irqrestore(&gpu->perf_lock, flags);
629 * Cmdstream submission/retirement:
632 static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
633 struct msm_gem_submit *submit)
635 int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
636 volatile struct msm_gpu_submit_stats *stats;
637 u64 elapsed, clock = 0;
640 stats = &ring->memptrs->stats[index];
641 /* Convert 19.2Mhz alwayson ticks to nanoseconds for elapsed time */
642 elapsed = (stats->alwayson_end - stats->alwayson_start) * 10000;
643 do_div(elapsed, 192);
645 /* Calculate the clock frequency from the number of CP cycles */
647 clock = (stats->cpcycles_end - stats->cpcycles_start) * 1000;
648 do_div(clock, elapsed);
651 trace_msm_gpu_submit_retired(submit, elapsed, clock,
652 stats->alwayson_start, stats->alwayson_end);
654 msm_submit_retire(submit);
656 pm_runtime_mark_last_busy(&gpu->pdev->dev);
658 spin_lock_irqsave(&ring->submit_lock, flags);
659 list_del(&submit->node);
660 spin_unlock_irqrestore(&ring->submit_lock, flags);
662 /* Update devfreq on transition from active->idle: */
663 mutex_lock(&gpu->active_lock);
664 gpu->active_submits--;
665 WARN_ON(gpu->active_submits < 0);
666 if (!gpu->active_submits)
667 msm_devfreq_idle(gpu);
668 mutex_unlock(&gpu->active_lock);
670 pm_runtime_put_autosuspend(&gpu->pdev->dev);
672 msm_gem_submit_put(submit);
675 static void retire_submits(struct msm_gpu *gpu)
679 /* Retire the commits starting with highest priority */
680 for (i = 0; i < gpu->nr_rings; i++) {
681 struct msm_ringbuffer *ring = gpu->rb[i];
684 struct msm_gem_submit *submit = NULL;
687 spin_lock_irqsave(&ring->submit_lock, flags);
688 submit = list_first_entry_or_null(&ring->submits,
689 struct msm_gem_submit, node);
690 spin_unlock_irqrestore(&ring->submit_lock, flags);
693 * If no submit, we are done. If submit->fence hasn't
694 * been signalled, then later submits are not signalled
695 * either, so we are also done.
697 if (submit && dma_fence_is_signaled(submit->hw_fence)) {
698 retire_submit(gpu, ring, submit);
705 wake_up_all(&gpu->retire_event);
708 static void retire_worker(struct kthread_work *work)
710 struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work);
715 /* call from irq handler to schedule work to retire bo's */
716 void msm_gpu_retire(struct msm_gpu *gpu)
720 for (i = 0; i < gpu->nr_rings; i++)
721 msm_update_fence(gpu->rb[i]->fctx, gpu->rb[i]->memptrs->fence);
723 kthread_queue_work(gpu->worker, &gpu->retire_work);
724 update_sw_cntrs(gpu);
727 /* add bo's to gpu's ring, and kick gpu: */
728 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
730 struct drm_device *dev = gpu->dev;
731 struct msm_drm_private *priv = dev->dev_private;
732 struct msm_ringbuffer *ring = submit->ring;
735 WARN_ON(!mutex_is_locked(&gpu->lock));
737 pm_runtime_get_sync(&gpu->pdev->dev);
739 msm_gpu_hw_init(gpu);
741 submit->seqno = submit->hw_fence->seqno;
743 msm_rd_dump_submit(priv->rd, submit, NULL);
745 update_sw_cntrs(gpu);
748 * ring->submits holds a ref to the submit, to deal with the case
749 * that a submit completes before msm_ioctl_gem_submit() returns.
751 msm_gem_submit_get(submit);
753 spin_lock_irqsave(&ring->submit_lock, flags);
754 list_add_tail(&submit->node, &ring->submits);
755 spin_unlock_irqrestore(&ring->submit_lock, flags);
757 /* Update devfreq on transition from idle->active: */
758 mutex_lock(&gpu->active_lock);
759 if (!gpu->active_submits)
760 msm_devfreq_active(gpu);
761 gpu->active_submits++;
762 mutex_unlock(&gpu->active_lock);
764 gpu->funcs->submit(gpu, submit);
765 gpu->cur_ctx_seqno = submit->queue->ctx->seqno;
767 hangcheck_timer_reset(gpu);
774 static irqreturn_t irq_handler(int irq, void *data)
776 struct msm_gpu *gpu = data;
777 return gpu->funcs->irq(gpu);
780 static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu)
782 int ret = devm_clk_bulk_get_all(&pdev->dev, &gpu->grp_clks);
789 gpu->nr_clocks = ret;
791 gpu->core_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
792 gpu->nr_clocks, "core");
794 gpu->rbbmtimer_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
795 gpu->nr_clocks, "rbbmtimer");
800 /* Return a new address space for a msm_drm_private instance */
801 struct msm_gem_address_space *
802 msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task)
804 struct msm_gem_address_space *aspace = NULL;
809 * If the target doesn't support private address spaces then return
812 if (gpu->funcs->create_private_address_space) {
813 aspace = gpu->funcs->create_private_address_space(gpu);
815 aspace->pid = get_pid(task_pid(task));
818 if (IS_ERR_OR_NULL(aspace))
819 aspace = msm_gem_address_space_get(gpu->aspace);
824 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
825 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
826 const char *name, struct msm_gpu_config *config)
828 int i, ret, nr_rings = config->nr_rings;
830 uint64_t memptrs_iova;
832 if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs)))
833 gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs);
839 gpu->worker = kthread_create_worker(0, "gpu-worker");
840 if (IS_ERR(gpu->worker)) {
841 ret = PTR_ERR(gpu->worker);
846 sched_set_fifo_low(gpu->worker->task);
848 INIT_LIST_HEAD(&gpu->active_list);
849 mutex_init(&gpu->active_lock);
850 mutex_init(&gpu->lock);
851 init_waitqueue_head(&gpu->retire_event);
852 kthread_init_work(&gpu->retire_work, retire_worker);
853 kthread_init_work(&gpu->recover_work, recover_worker);
854 kthread_init_work(&gpu->fault_work, fault_worker);
856 timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0);
858 spin_lock_init(&gpu->perf_lock);
862 gpu->mmio = msm_ioremap(pdev, config->ioname);
863 if (IS_ERR(gpu->mmio)) {
864 ret = PTR_ERR(gpu->mmio);
869 gpu->irq = platform_get_irq(pdev, 0);
872 DRM_DEV_ERROR(drm->dev, "failed to get irq: %d\n", ret);
876 ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler,
877 IRQF_TRIGGER_HIGH, "gpu-irq", gpu);
879 DRM_DEV_ERROR(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret);
883 ret = get_clocks(pdev, gpu);
887 gpu->ebi1_clk = msm_clk_get(pdev, "bus");
888 DBG("ebi1_clk: %p", gpu->ebi1_clk);
889 if (IS_ERR(gpu->ebi1_clk))
890 gpu->ebi1_clk = NULL;
892 /* Acquire regulators: */
893 gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd");
894 DBG("gpu_reg: %p", gpu->gpu_reg);
895 if (IS_ERR(gpu->gpu_reg))
898 gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx");
899 DBG("gpu_cx: %p", gpu->gpu_cx);
900 if (IS_ERR(gpu->gpu_cx))
904 platform_set_drvdata(pdev, &gpu->adreno_smmu);
906 msm_devfreq_init(gpu);
909 gpu->aspace = gpu->funcs->create_address_space(gpu, pdev);
911 if (gpu->aspace == NULL)
912 DRM_DEV_INFO(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name);
913 else if (IS_ERR(gpu->aspace)) {
914 ret = PTR_ERR(gpu->aspace);
918 memptrs = msm_gem_kernel_new(drm,
919 sizeof(struct msm_rbmemptrs) * nr_rings,
920 check_apriv(gpu, MSM_BO_UNCACHED), gpu->aspace, &gpu->memptrs_bo,
923 if (IS_ERR(memptrs)) {
924 ret = PTR_ERR(memptrs);
925 DRM_DEV_ERROR(drm->dev, "could not allocate memptrs: %d\n", ret);
929 msm_gem_object_set_name(gpu->memptrs_bo, "memptrs");
931 if (nr_rings > ARRAY_SIZE(gpu->rb)) {
932 DRM_DEV_INFO_ONCE(drm->dev, "Only creating %zu ringbuffers\n",
933 ARRAY_SIZE(gpu->rb));
934 nr_rings = ARRAY_SIZE(gpu->rb);
937 /* Create ringbuffer(s): */
938 for (i = 0; i < nr_rings; i++) {
939 gpu->rb[i] = msm_ringbuffer_new(gpu, i, memptrs, memptrs_iova);
941 if (IS_ERR(gpu->rb[i])) {
942 ret = PTR_ERR(gpu->rb[i]);
943 DRM_DEV_ERROR(drm->dev,
944 "could not create ringbuffer %d: %d\n", i, ret);
948 memptrs += sizeof(struct msm_rbmemptrs);
949 memptrs_iova += sizeof(struct msm_rbmemptrs);
952 gpu->nr_rings = nr_rings;
954 refcount_set(&gpu->sysprof_active, 1);
959 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
960 msm_ringbuffer_destroy(gpu->rb[i]);
964 msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace);
966 platform_set_drvdata(pdev, NULL);
970 void msm_gpu_cleanup(struct msm_gpu *gpu)
974 DBG("%s", gpu->name);
976 WARN_ON(!list_empty(&gpu->active_list));
978 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
979 msm_ringbuffer_destroy(gpu->rb[i]);
983 msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace);
985 if (!IS_ERR_OR_NULL(gpu->aspace)) {
986 gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu);
987 msm_gem_address_space_put(gpu->aspace);
991 kthread_destroy_worker(gpu->worker);
994 msm_devfreq_cleanup(gpu);