2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include "msm_debugfs.h"
20 #include "msm_fence.h"
27 * - 1.0.0 - initial interface
28 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
29 * - 1.2.0 - adds explicit fence support for submit ioctl
31 #define MSM_VERSION_MAJOR 1
32 #define MSM_VERSION_MINOR 2
33 #define MSM_VERSION_PATCHLEVEL 0
35 static void msm_fb_output_poll_changed(struct drm_device *dev)
37 struct msm_drm_private *priv = dev->dev_private;
39 drm_fb_helper_hotplug_event(priv->fbdev);
42 static const struct drm_mode_config_funcs mode_config_funcs = {
43 .fb_create = msm_framebuffer_create,
44 .output_poll_changed = msm_fb_output_poll_changed,
45 .atomic_check = msm_atomic_check,
46 .atomic_commit = msm_atomic_commit,
49 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu)
51 struct msm_drm_private *priv = dev->dev_private;
52 int idx = priv->num_mmus++;
54 if (WARN_ON(idx >= ARRAY_SIZE(priv->mmus)))
57 priv->mmus[idx] = mmu;
62 #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
63 static bool reglog = false;
64 MODULE_PARM_DESC(reglog, "Enable register read/write logging");
65 module_param(reglog, bool, 0600);
70 #ifdef CONFIG_DRM_FBDEV_EMULATION
71 static bool fbdev = true;
72 MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
73 module_param(fbdev, bool, 0600);
76 static char *vram = "16m";
77 MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
78 module_param(vram, charp, 0);
84 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
92 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
94 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
97 dev_err(&pdev->dev, "failed to get memory resource: %s\n", name);
98 return ERR_PTR(-EINVAL);
101 size = resource_size(res);
103 ptr = devm_ioremap_nocache(&pdev->dev, res->start, size);
105 dev_err(&pdev->dev, "failed to ioremap: %s\n", name);
106 return ERR_PTR(-ENOMEM);
110 printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
115 void msm_writel(u32 data, void __iomem *addr)
118 printk(KERN_DEBUG "IO:W %p %08x\n", addr, data);
122 u32 msm_readl(const void __iomem *addr)
124 u32 val = readl(addr);
126 printk(KERN_ERR "IO:R %p %08x\n", addr, val);
130 struct vblank_event {
131 struct list_head node;
136 static void vblank_ctrl_worker(struct work_struct *work)
138 struct msm_vblank_ctrl *vbl_ctrl = container_of(work,
139 struct msm_vblank_ctrl, work);
140 struct msm_drm_private *priv = container_of(vbl_ctrl,
141 struct msm_drm_private, vblank_ctrl);
142 struct msm_kms *kms = priv->kms;
143 struct vblank_event *vbl_ev, *tmp;
146 spin_lock_irqsave(&vbl_ctrl->lock, flags);
147 list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) {
148 list_del(&vbl_ev->node);
149 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
152 kms->funcs->enable_vblank(kms,
153 priv->crtcs[vbl_ev->crtc_id]);
155 kms->funcs->disable_vblank(kms,
156 priv->crtcs[vbl_ev->crtc_id]);
160 spin_lock_irqsave(&vbl_ctrl->lock, flags);
163 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
166 static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
167 int crtc_id, bool enable)
169 struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl;
170 struct vblank_event *vbl_ev;
173 vbl_ev = kzalloc(sizeof(*vbl_ev), GFP_ATOMIC);
177 vbl_ev->crtc_id = crtc_id;
178 vbl_ev->enable = enable;
180 spin_lock_irqsave(&vbl_ctrl->lock, flags);
181 list_add_tail(&vbl_ev->node, &vbl_ctrl->event_list);
182 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
184 queue_work(priv->wq, &vbl_ctrl->work);
189 static int msm_drm_uninit(struct device *dev)
191 struct platform_device *pdev = to_platform_device(dev);
192 struct drm_device *ddev = platform_get_drvdata(pdev);
193 struct msm_drm_private *priv = ddev->dev_private;
194 struct msm_kms *kms = priv->kms;
195 struct msm_gpu *gpu = priv->gpu;
196 struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl;
197 struct vblank_event *vbl_ev, *tmp;
199 /* We must cancel and cleanup any pending vblank enable/disable
200 * work before drm_irq_uninstall() to avoid work re-enabling an
201 * irq after uninstall has disabled it.
203 cancel_work_sync(&vbl_ctrl->work);
204 list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) {
205 list_del(&vbl_ev->node);
209 msm_gem_shrinker_cleanup(ddev);
211 drm_kms_helper_poll_fini(ddev);
213 drm_dev_unregister(ddev);
215 #ifdef CONFIG_DRM_FBDEV_EMULATION
216 if (fbdev && priv->fbdev)
217 msm_fbdev_free(ddev);
219 drm_mode_config_cleanup(ddev);
221 pm_runtime_get_sync(dev);
222 drm_irq_uninstall(ddev);
223 pm_runtime_put_sync(dev);
225 flush_workqueue(priv->wq);
226 destroy_workqueue(priv->wq);
228 flush_workqueue(priv->atomic_wq);
229 destroy_workqueue(priv->atomic_wq);
231 if (kms && kms->funcs)
232 kms->funcs->destroy(kms);
235 mutex_lock(&ddev->struct_mutex);
236 gpu->funcs->pm_suspend(gpu);
237 mutex_unlock(&ddev->struct_mutex);
238 gpu->funcs->destroy(gpu);
241 if (priv->vram.paddr) {
242 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
243 drm_mm_takedown(&priv->vram.mm);
244 dma_free_attrs(dev, priv->vram.size, NULL,
245 priv->vram.paddr, attrs);
248 component_unbind_all(dev, ddev);
250 msm_mdss_destroy(ddev);
252 ddev->dev_private = NULL;
260 static int get_mdp_ver(struct platform_device *pdev)
262 struct device *dev = &pdev->dev;
264 return (int) (unsigned long) of_device_get_match_data(dev);
267 #include <linux/of_address.h>
269 static int msm_init_vram(struct drm_device *dev)
271 struct msm_drm_private *priv = dev->dev_private;
272 struct device_node *node;
273 unsigned long size = 0;
276 /* In the device-tree world, we could have a 'memory-region'
277 * phandle, which gives us a link to our "vram". Allocating
278 * is all nicely abstracted behind the dma api, but we need
279 * to know the entire size to allocate it all in one go. There
281 * 1) device with no IOMMU, in which case we need exclusive
282 * access to a VRAM carveout big enough for all gpu
284 * 2) device with IOMMU, but where the bootloader puts up
285 * a splash screen. In this case, the VRAM carveout
286 * need only be large enough for fbdev fb. But we need
287 * exclusive access to the buffer to avoid the kernel
288 * using those pages for other purposes (which appears
289 * as corruption on screen before we have a chance to
290 * load and do initial modeset)
293 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
296 ret = of_address_to_resource(node, 0, &r);
300 size = r.end - r.start + 1;
301 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
303 /* if we have no IOMMU, then we need to use carveout allocator.
304 * Grab the entire CMA chunk carved out in early startup in
307 } else if (!iommu_present(&platform_bus_type)) {
308 DRM_INFO("using %s VRAM carveout\n", vram);
309 size = memparse(vram, NULL);
313 unsigned long attrs = 0;
316 priv->vram.size = size;
318 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
320 attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
321 attrs |= DMA_ATTR_WRITE_COMBINE;
323 /* note that for no-kernel-mapping, the vaddr returned
324 * is bogus, but non-null if allocation succeeded:
326 p = dma_alloc_attrs(dev->dev, size,
327 &priv->vram.paddr, GFP_KERNEL, attrs);
329 dev_err(dev->dev, "failed to allocate VRAM\n");
330 priv->vram.paddr = 0;
334 dev_info(dev->dev, "VRAM: %08x->%08x\n",
335 (uint32_t)priv->vram.paddr,
336 (uint32_t)(priv->vram.paddr + size));
342 static int msm_drm_init(struct device *dev, struct drm_driver *drv)
344 struct platform_device *pdev = to_platform_device(dev);
345 struct drm_device *ddev;
346 struct msm_drm_private *priv;
350 ddev = drm_dev_alloc(drv, dev);
352 dev_err(dev, "failed to allocate drm_device\n");
353 return PTR_ERR(ddev);
356 platform_set_drvdata(pdev, ddev);
357 ddev->platformdev = pdev;
359 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
365 ddev->dev_private = priv;
368 ret = msm_mdss_init(ddev);
375 priv->wq = alloc_ordered_workqueue("msm", 0);
376 priv->atomic_wq = alloc_ordered_workqueue("msm:atomic", 0);
377 init_waitqueue_head(&priv->pending_crtcs_event);
379 INIT_LIST_HEAD(&priv->inactive_list);
380 INIT_LIST_HEAD(&priv->vblank_ctrl.event_list);
381 INIT_WORK(&priv->vblank_ctrl.work, vblank_ctrl_worker);
382 spin_lock_init(&priv->vblank_ctrl.lock);
384 drm_mode_config_init(ddev);
386 /* Bind all our sub-components: */
387 ret = component_bind_all(dev, ddev);
389 msm_mdss_destroy(ddev);
395 ret = msm_init_vram(ddev);
399 if (!dev->dma_parms) {
400 dev->dma_parms = devm_kzalloc(dev, sizeof(*dev->dma_parms),
405 dma_set_max_seg_size(dev, DMA_BIT_MASK(32));
407 msm_gem_shrinker_init(ddev);
409 switch (get_mdp_ver(pdev)) {
411 kms = mdp4_kms_init(ddev);
415 kms = mdp5_kms_init(ddev);
418 kms = ERR_PTR(-ENODEV);
424 * NOTE: once we have GPU support, having no kms should not
425 * be considered fatal.. ideally we would still support gpu
426 * and (for example) use dmabuf/prime to share buffers with
427 * imx drm driver on iMX5
429 dev_err(dev, "failed to load kms\n");
435 ret = kms->funcs->hw_init(kms);
437 dev_err(dev, "kms hw init failed: %d\n", ret);
442 ddev->mode_config.funcs = &mode_config_funcs;
444 ret = drm_vblank_init(ddev, priv->num_crtcs);
446 dev_err(dev, "failed to initialize vblank\n");
451 pm_runtime_get_sync(dev);
452 ret = drm_irq_install(ddev, kms->irq);
453 pm_runtime_put_sync(dev);
455 dev_err(dev, "failed to install IRQ handler\n");
460 ret = drm_dev_register(ddev, 0);
464 drm_mode_config_reset(ddev);
466 #ifdef CONFIG_DRM_FBDEV_EMULATION
468 priv->fbdev = msm_fbdev_init(ddev);
471 ret = msm_debugfs_late_init(ddev);
475 drm_kms_helper_poll_init(ddev);
488 static void load_gpu(struct drm_device *dev)
490 static DEFINE_MUTEX(init_lock);
491 struct msm_drm_private *priv = dev->dev_private;
493 mutex_lock(&init_lock);
496 priv->gpu = adreno_load_gpu(dev);
498 mutex_unlock(&init_lock);
501 static int msm_open(struct drm_device *dev, struct drm_file *file)
503 struct msm_file_private *ctx;
505 /* For now, load gpu on open.. to avoid the requirement of having
506 * firmware in the initrd.
510 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
514 file->driver_priv = ctx;
519 static void msm_preclose(struct drm_device *dev, struct drm_file *file)
521 struct msm_drm_private *priv = dev->dev_private;
522 struct msm_file_private *ctx = file->driver_priv;
524 mutex_lock(&dev->struct_mutex);
525 if (ctx == priv->lastctx)
526 priv->lastctx = NULL;
527 mutex_unlock(&dev->struct_mutex);
532 static void msm_lastclose(struct drm_device *dev)
534 struct msm_drm_private *priv = dev->dev_private;
536 drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev);
539 static irqreturn_t msm_irq(int irq, void *arg)
541 struct drm_device *dev = arg;
542 struct msm_drm_private *priv = dev->dev_private;
543 struct msm_kms *kms = priv->kms;
545 return kms->funcs->irq(kms);
548 static void msm_irq_preinstall(struct drm_device *dev)
550 struct msm_drm_private *priv = dev->dev_private;
551 struct msm_kms *kms = priv->kms;
553 kms->funcs->irq_preinstall(kms);
556 static int msm_irq_postinstall(struct drm_device *dev)
558 struct msm_drm_private *priv = dev->dev_private;
559 struct msm_kms *kms = priv->kms;
561 return kms->funcs->irq_postinstall(kms);
564 static void msm_irq_uninstall(struct drm_device *dev)
566 struct msm_drm_private *priv = dev->dev_private;
567 struct msm_kms *kms = priv->kms;
569 kms->funcs->irq_uninstall(kms);
572 static int msm_enable_vblank(struct drm_device *dev, unsigned int pipe)
574 struct msm_drm_private *priv = dev->dev_private;
575 struct msm_kms *kms = priv->kms;
578 DBG("dev=%p, crtc=%u", dev, pipe);
579 return vblank_ctrl_queue_work(priv, pipe, true);
582 static void msm_disable_vblank(struct drm_device *dev, unsigned int pipe)
584 struct msm_drm_private *priv = dev->dev_private;
585 struct msm_kms *kms = priv->kms;
588 DBG("dev=%p, crtc=%u", dev, pipe);
589 vblank_ctrl_queue_work(priv, pipe, false);
596 static int msm_ioctl_get_param(struct drm_device *dev, void *data,
597 struct drm_file *file)
599 struct msm_drm_private *priv = dev->dev_private;
600 struct drm_msm_param *args = data;
603 /* for now, we just have 3d pipe.. eventually this would need to
604 * be more clever to dispatch to appropriate gpu module:
606 if (args->pipe != MSM_PIPE_3D0)
614 return gpu->funcs->get_param(gpu, args->param, &args->value);
617 static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
618 struct drm_file *file)
620 struct drm_msm_gem_new *args = data;
622 if (args->flags & ~MSM_BO_FLAGS) {
623 DRM_ERROR("invalid flags: %08x\n", args->flags);
627 return msm_gem_new_handle(dev, file, args->size,
628 args->flags, &args->handle);
631 static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
633 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
636 static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
637 struct drm_file *file)
639 struct drm_msm_gem_cpu_prep *args = data;
640 struct drm_gem_object *obj;
641 ktime_t timeout = to_ktime(args->timeout);
644 if (args->op & ~MSM_PREP_FLAGS) {
645 DRM_ERROR("invalid op: %08x\n", args->op);
649 obj = drm_gem_object_lookup(file, args->handle);
653 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
655 drm_gem_object_unreference_unlocked(obj);
660 static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
661 struct drm_file *file)
663 struct drm_msm_gem_cpu_fini *args = data;
664 struct drm_gem_object *obj;
667 obj = drm_gem_object_lookup(file, args->handle);
671 ret = msm_gem_cpu_fini(obj);
673 drm_gem_object_unreference_unlocked(obj);
678 static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
679 struct drm_file *file)
681 struct drm_msm_gem_info *args = data;
682 struct drm_gem_object *obj;
688 obj = drm_gem_object_lookup(file, args->handle);
692 args->offset = msm_gem_mmap_offset(obj);
694 drm_gem_object_unreference_unlocked(obj);
699 static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
700 struct drm_file *file)
702 struct msm_drm_private *priv = dev->dev_private;
703 struct drm_msm_wait_fence *args = data;
704 ktime_t timeout = to_ktime(args->timeout);
707 DRM_ERROR("invalid pad: %08x\n", args->pad);
714 return msm_wait_fence(priv->gpu->fctx, args->fence, &timeout, true);
717 static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
718 struct drm_file *file)
720 struct drm_msm_gem_madvise *args = data;
721 struct drm_gem_object *obj;
724 switch (args->madv) {
725 case MSM_MADV_DONTNEED:
726 case MSM_MADV_WILLNEED:
732 ret = mutex_lock_interruptible(&dev->struct_mutex);
736 obj = drm_gem_object_lookup(file, args->handle);
742 ret = msm_gem_madvise(obj, args->madv);
744 args->retained = ret;
748 drm_gem_object_unreference(obj);
751 mutex_unlock(&dev->struct_mutex);
755 static const struct drm_ioctl_desc msm_ioctls[] = {
756 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_AUTH|DRM_RENDER_ALLOW),
757 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_AUTH|DRM_RENDER_ALLOW),
758 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_AUTH|DRM_RENDER_ALLOW),
759 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW),
760 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW),
761 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_AUTH|DRM_RENDER_ALLOW),
762 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_AUTH|DRM_RENDER_ALLOW),
763 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_AUTH|DRM_RENDER_ALLOW),
766 static const struct vm_operations_struct vm_ops = {
767 .fault = msm_gem_fault,
768 .open = drm_gem_vm_open,
769 .close = drm_gem_vm_close,
772 static const struct file_operations fops = {
773 .owner = THIS_MODULE,
775 .release = drm_release,
776 .unlocked_ioctl = drm_ioctl,
778 .compat_ioctl = drm_compat_ioctl,
783 .mmap = msm_gem_mmap,
786 static struct drm_driver msm_driver = {
787 .driver_features = DRIVER_HAVE_IRQ |
794 .preclose = msm_preclose,
795 .lastclose = msm_lastclose,
796 .irq_handler = msm_irq,
797 .irq_preinstall = msm_irq_preinstall,
798 .irq_postinstall = msm_irq_postinstall,
799 .irq_uninstall = msm_irq_uninstall,
800 .get_vblank_counter = drm_vblank_no_hw_counter,
801 .enable_vblank = msm_enable_vblank,
802 .disable_vblank = msm_disable_vblank,
803 .gem_free_object = msm_gem_free_object,
804 .gem_vm_ops = &vm_ops,
805 .dumb_create = msm_gem_dumb_create,
806 .dumb_map_offset = msm_gem_dumb_map_offset,
807 .dumb_destroy = drm_gem_dumb_destroy,
808 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
809 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
810 .gem_prime_export = drm_gem_prime_export,
811 .gem_prime_import = drm_gem_prime_import,
812 .gem_prime_res_obj = msm_gem_prime_res_obj,
813 .gem_prime_pin = msm_gem_prime_pin,
814 .gem_prime_unpin = msm_gem_prime_unpin,
815 .gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
816 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
817 .gem_prime_vmap = msm_gem_prime_vmap,
818 .gem_prime_vunmap = msm_gem_prime_vunmap,
819 .gem_prime_mmap = msm_gem_prime_mmap,
820 #ifdef CONFIG_DEBUG_FS
821 .debugfs_init = msm_debugfs_init,
822 .debugfs_cleanup = msm_debugfs_cleanup,
824 .ioctls = msm_ioctls,
825 .num_ioctls = DRM_MSM_NUM_IOCTLS,
828 .desc = "MSM Snapdragon DRM",
830 .major = MSM_VERSION_MAJOR,
831 .minor = MSM_VERSION_MINOR,
832 .patchlevel = MSM_VERSION_PATCHLEVEL,
835 #ifdef CONFIG_PM_SLEEP
836 static int msm_pm_suspend(struct device *dev)
838 struct drm_device *ddev = dev_get_drvdata(dev);
840 drm_kms_helper_poll_disable(ddev);
845 static int msm_pm_resume(struct device *dev)
847 struct drm_device *ddev = dev_get_drvdata(dev);
849 drm_kms_helper_poll_enable(ddev);
855 static const struct dev_pm_ops msm_pm_ops = {
856 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
860 * Componentized driver support:
864 * NOTE: duplication of the same code as exynos or imx (or probably any other).
865 * so probably some room for some helpers
867 static int compare_of(struct device *dev, void *data)
869 return dev->of_node == data;
873 * Identify what components need to be added by parsing what remote-endpoints
874 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
875 * is no external component that we need to add since LVDS is within MDP4
878 static int add_components_mdp(struct device *mdp_dev,
879 struct component_match **matchptr)
881 struct device_node *np = mdp_dev->of_node;
882 struct device_node *ep_node;
883 struct device *master_dev;
886 * on MDP4 based platforms, the MDP platform device is the component
887 * master that adds other display interface components to itself.
889 * on MDP5 based platforms, the MDSS platform device is the component
890 * master that adds MDP5 and other display interface components to
893 if (of_device_is_compatible(np, "qcom,mdp4"))
894 master_dev = mdp_dev;
896 master_dev = mdp_dev->parent;
898 for_each_endpoint_of_node(np, ep_node) {
899 struct device_node *intf;
900 struct of_endpoint ep;
903 ret = of_graph_parse_endpoint(ep_node, &ep);
905 dev_err(mdp_dev, "unable to parse port endpoint\n");
906 of_node_put(ep_node);
911 * The LCDC/LVDS port on MDP4 is a speacial case where the
912 * remote-endpoint isn't a component that we need to add
914 if (of_device_is_compatible(np, "qcom,mdp4") &&
916 of_node_put(ep_node);
921 * It's okay if some of the ports don't have a remote endpoint
922 * specified. It just means that the port isn't connected to
923 * any external interface.
925 intf = of_graph_get_remote_port_parent(ep_node);
927 of_node_put(ep_node);
931 component_match_add(master_dev, matchptr, compare_of, intf);
934 of_node_put(ep_node);
940 static int compare_name_mdp(struct device *dev, void *data)
942 return (strstr(dev_name(dev), "mdp") != NULL);
945 static int add_display_components(struct device *dev,
946 struct component_match **matchptr)
948 struct device *mdp_dev;
952 * MDP5 based devices don't have a flat hierarchy. There is a top level
953 * parent: MDSS, and children: MDP5, DSI, HDMI, eDP etc. Populate the
954 * children devices, find the MDP5 node, and then add the interfaces
955 * to our components list.
957 if (of_device_is_compatible(dev->of_node, "qcom,mdss")) {
958 ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
960 dev_err(dev, "failed to populate children devices\n");
964 mdp_dev = device_find_child(dev, NULL, compare_name_mdp);
966 dev_err(dev, "failed to find MDSS MDP node\n");
967 of_platform_depopulate(dev);
973 /* add the MDP component itself */
974 component_match_add(dev, matchptr, compare_of,
981 ret = add_components_mdp(mdp_dev, matchptr);
983 of_platform_depopulate(dev);
989 * We don't know what's the best binding to link the gpu with the drm device.
990 * Fow now, we just hunt for all the possible gpus that we support, and add them
993 static const struct of_device_id msm_gpu_match[] = {
994 { .compatible = "qcom,adreno-3xx" },
995 { .compatible = "qcom,kgsl-3d0" },
999 static int add_gpu_components(struct device *dev,
1000 struct component_match **matchptr)
1002 struct device_node *np;
1004 np = of_find_matching_node(NULL, msm_gpu_match);
1008 component_match_add(dev, matchptr, compare_of, np);
1015 static int msm_drm_bind(struct device *dev)
1017 return msm_drm_init(dev, &msm_driver);
1020 static void msm_drm_unbind(struct device *dev)
1022 msm_drm_uninit(dev);
1025 static const struct component_master_ops msm_drm_ops = {
1026 .bind = msm_drm_bind,
1027 .unbind = msm_drm_unbind,
1034 static int msm_pdev_probe(struct platform_device *pdev)
1036 struct component_match *match = NULL;
1039 ret = add_display_components(&pdev->dev, &match);
1043 ret = add_gpu_components(&pdev->dev, &match);
1047 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
1048 return component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
1051 static int msm_pdev_remove(struct platform_device *pdev)
1053 component_master_del(&pdev->dev, &msm_drm_ops);
1054 of_platform_depopulate(&pdev->dev);
1059 static const struct of_device_id dt_match[] = {
1060 { .compatible = "qcom,mdp4", .data = (void *)4 }, /* MDP4 */
1061 { .compatible = "qcom,mdss", .data = (void *)5 }, /* MDP5 MDSS */
1064 MODULE_DEVICE_TABLE(of, dt_match);
1066 static struct platform_driver msm_platform_driver = {
1067 .probe = msm_pdev_probe,
1068 .remove = msm_pdev_remove,
1071 .of_match_table = dt_match,
1076 static int __init msm_drm_register(void)
1082 msm_hdmi_register();
1084 return platform_driver_register(&msm_platform_driver);
1087 static void __exit msm_drm_unregister(void)
1090 platform_driver_unregister(&msm_platform_driver);
1091 msm_hdmi_unregister();
1092 adreno_unregister();
1093 msm_edp_unregister();
1094 msm_dsi_unregister();
1095 msm_mdp_unregister();
1098 module_init(msm_drm_register);
1099 module_exit(msm_drm_unregister);
1101 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1102 MODULE_DESCRIPTION("MSM DRM Driver");
1103 MODULE_LICENSE("GPL");