2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/of_irq.h>
26 static const char *iommu_ports[] = {
30 static int mdp5_hw_init(struct msm_kms *kms)
32 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
33 struct device *dev = &mdp5_kms->pdev->dev;
36 pm_runtime_get_sync(dev);
38 /* Magic unknown register writes:
40 * W VBIF:0x004 00000001 (mdss_mdp.c:839)
41 * W MDP5:0x2e0 0xe9 (mdss_mdp.c:839)
42 * W MDP5:0x2e4 0x55 (mdss_mdp.c:839)
43 * W MDP5:0x3ac 0xc0000ccc (mdss_mdp.c:839)
44 * W MDP5:0x3b4 0xc0000ccc (mdss_mdp.c:839)
45 * W MDP5:0x3bc 0xcccccc (mdss_mdp.c:839)
46 * W MDP5:0x4a8 0xcccc0c0 (mdss_mdp.c:839)
47 * W MDP5:0x4b0 0xccccc0c0 (mdss_mdp.c:839)
48 * W MDP5:0x4b8 0xccccc000 (mdss_mdp.c:839)
50 * Downstream fbdev driver gets these register offsets/values
51 * from DT.. not really sure what these registers are or if
52 * different values for different boards/SoC's, etc. I guess
53 * they are the golden registers.
55 * Not setting these does not seem to cause any problem. But
56 * we may be getting lucky with the bootloader initializing
57 * them for us. OTOH, if we can always count on the bootloader
58 * setting the golden registers, then perhaps we don't need to
62 spin_lock_irqsave(&mdp5_kms->resource_lock, flags);
63 mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0);
64 spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags);
66 mdp5_ctlm_hw_reset(mdp5_kms->ctlm);
68 pm_runtime_put_sync(dev);
73 struct mdp5_state *mdp5_get_state(struct drm_atomic_state *s)
75 struct msm_drm_private *priv = s->dev->dev_private;
76 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
77 struct msm_kms_state *state = to_kms_state(s);
78 struct mdp5_state *new_state;
84 ret = drm_modeset_lock(&mdp5_kms->state_lock, s->acquire_ctx);
88 new_state = kmalloc(sizeof(*mdp5_kms->state), GFP_KERNEL);
90 return ERR_PTR(-ENOMEM);
93 new_state->hwpipe = mdp5_kms->state->hwpipe;
94 new_state->hwmixer = mdp5_kms->state->hwmixer;
96 new_state->smp = mdp5_kms->state->smp;
98 state->state = new_state;
103 static void mdp5_swap_state(struct msm_kms *kms, struct drm_atomic_state *state)
105 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
106 swap(to_kms_state(state)->state, mdp5_kms->state);
109 static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state)
111 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
112 struct device *dev = &mdp5_kms->pdev->dev;
114 pm_runtime_get_sync(dev);
117 mdp5_smp_prepare_commit(mdp5_kms->smp, &mdp5_kms->state->smp);
120 static void mdp5_complete_commit(struct msm_kms *kms, struct drm_atomic_state *state)
122 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
123 struct device *dev = &mdp5_kms->pdev->dev;
126 mdp5_smp_complete_commit(mdp5_kms->smp, &mdp5_kms->state->smp);
128 pm_runtime_put_autosuspend(dev);
131 static void mdp5_wait_for_crtc_commit_done(struct msm_kms *kms,
132 struct drm_crtc *crtc)
134 mdp5_crtc_wait_for_commit_done(crtc);
137 static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate,
138 struct drm_encoder *encoder)
143 static int mdp5_set_split_display(struct msm_kms *kms,
144 struct drm_encoder *encoder,
145 struct drm_encoder *slave_encoder,
149 return mdp5_cmd_encoder_set_split_display(encoder,
152 return mdp5_vid_encoder_set_split_display(encoder,
156 static void mdp5_set_encoder_mode(struct msm_kms *kms,
157 struct drm_encoder *encoder,
160 mdp5_encoder_set_intf_mode(encoder, cmd_mode);
163 static void mdp5_kms_destroy(struct msm_kms *kms)
165 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
166 struct msm_gem_address_space *aspace = kms->aspace;
169 for (i = 0; i < mdp5_kms->num_hwmixers; i++)
170 mdp5_mixer_destroy(mdp5_kms->hwmixers[i]);
172 for (i = 0; i < mdp5_kms->num_hwpipes; i++)
173 mdp5_pipe_destroy(mdp5_kms->hwpipes[i]);
176 aspace->mmu->funcs->detach(aspace->mmu,
177 iommu_ports, ARRAY_SIZE(iommu_ports));
178 msm_gem_address_space_put(aspace);
182 #ifdef CONFIG_DEBUG_FS
183 static int smp_show(struct seq_file *m, void *arg)
185 struct drm_info_node *node = (struct drm_info_node *) m->private;
186 struct drm_device *dev = node->minor->dev;
187 struct msm_drm_private *priv = dev->dev_private;
188 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
189 struct drm_printer p = drm_seq_file_printer(m);
191 if (!mdp5_kms->smp) {
192 drm_printf(&p, "no SMP pool\n");
196 mdp5_smp_dump(mdp5_kms->smp, &p);
201 static struct drm_info_list mdp5_debugfs_list[] = {
205 static int mdp5_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor)
207 struct drm_device *dev = minor->dev;
210 ret = drm_debugfs_create_files(mdp5_debugfs_list,
211 ARRAY_SIZE(mdp5_debugfs_list),
212 minor->debugfs_root, minor);
215 dev_err(dev->dev, "could not install mdp5_debugfs_list\n");
223 static const struct mdp_kms_funcs kms_funcs = {
225 .hw_init = mdp5_hw_init,
226 .irq_preinstall = mdp5_irq_preinstall,
227 .irq_postinstall = mdp5_irq_postinstall,
228 .irq_uninstall = mdp5_irq_uninstall,
230 .enable_vblank = mdp5_enable_vblank,
231 .disable_vblank = mdp5_disable_vblank,
232 .swap_state = mdp5_swap_state,
233 .prepare_commit = mdp5_prepare_commit,
234 .complete_commit = mdp5_complete_commit,
235 .wait_for_crtc_commit_done = mdp5_wait_for_crtc_commit_done,
236 .get_format = mdp_get_format,
237 .round_pixclk = mdp5_round_pixclk,
238 .set_split_display = mdp5_set_split_display,
239 .set_encoder_mode = mdp5_set_encoder_mode,
240 .destroy = mdp5_kms_destroy,
241 #ifdef CONFIG_DEBUG_FS
242 .debugfs_init = mdp5_kms_debugfs_init,
245 .set_irqmask = mdp5_set_irqmask,
248 int mdp5_disable(struct mdp5_kms *mdp5_kms)
252 mdp5_kms->enable_count--;
253 WARN_ON(mdp5_kms->enable_count < 0);
255 clk_disable_unprepare(mdp5_kms->ahb_clk);
256 clk_disable_unprepare(mdp5_kms->axi_clk);
257 clk_disable_unprepare(mdp5_kms->core_clk);
258 if (mdp5_kms->lut_clk)
259 clk_disable_unprepare(mdp5_kms->lut_clk);
264 int mdp5_enable(struct mdp5_kms *mdp5_kms)
268 mdp5_kms->enable_count++;
270 clk_prepare_enable(mdp5_kms->ahb_clk);
271 clk_prepare_enable(mdp5_kms->axi_clk);
272 clk_prepare_enable(mdp5_kms->core_clk);
273 if (mdp5_kms->lut_clk)
274 clk_prepare_enable(mdp5_kms->lut_clk);
279 static struct drm_encoder *construct_encoder(struct mdp5_kms *mdp5_kms,
280 struct mdp5_interface *intf,
281 struct mdp5_ctl *ctl)
283 struct drm_device *dev = mdp5_kms->dev;
284 struct msm_drm_private *priv = dev->dev_private;
285 struct drm_encoder *encoder;
287 encoder = mdp5_encoder_init(dev, intf, ctl);
288 if (IS_ERR(encoder)) {
289 dev_err(dev->dev, "failed to construct encoder\n");
293 priv->encoders[priv->num_encoders++] = encoder;
298 static int get_dsi_id_from_intf(const struct mdp5_cfg_hw *hw_cfg, int intf_num)
300 const enum mdp5_intf_type *intfs = hw_cfg->intf.connect;
301 const int intf_cnt = ARRAY_SIZE(hw_cfg->intf.connect);
304 for (i = 0; i < intf_cnt; i++) {
305 if (intfs[i] == INTF_DSI) {
316 static int modeset_init_intf(struct mdp5_kms *mdp5_kms,
317 struct mdp5_interface *intf)
319 struct drm_device *dev = mdp5_kms->dev;
320 struct msm_drm_private *priv = dev->dev_private;
321 struct mdp5_ctl_manager *ctlm = mdp5_kms->ctlm;
322 struct mdp5_ctl *ctl;
323 struct drm_encoder *encoder;
326 switch (intf->type) {
331 ctl = mdp5_ctlm_request(ctlm, intf->num);
337 encoder = construct_encoder(mdp5_kms, intf, ctl);
338 if (IS_ERR(encoder)) {
339 ret = PTR_ERR(encoder);
343 ret = msm_edp_modeset_init(priv->edp, dev, encoder);
349 ctl = mdp5_ctlm_request(ctlm, intf->num);
355 encoder = construct_encoder(mdp5_kms, intf, ctl);
356 if (IS_ERR(encoder)) {
357 ret = PTR_ERR(encoder);
361 ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder);
365 const struct mdp5_cfg_hw *hw_cfg =
366 mdp5_cfg_get_hw_config(mdp5_kms->cfg);
367 int dsi_id = get_dsi_id_from_intf(hw_cfg, intf->num);
369 if ((dsi_id >= ARRAY_SIZE(priv->dsi)) || (dsi_id < 0)) {
370 dev_err(dev->dev, "failed to find dsi from intf %d\n",
376 if (!priv->dsi[dsi_id])
379 ctl = mdp5_ctlm_request(ctlm, intf->num);
385 encoder = construct_encoder(mdp5_kms, intf, ctl);
386 if (IS_ERR(encoder)) {
387 ret = PTR_ERR(encoder);
391 ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder);
395 dev_err(dev->dev, "unknown intf: %d\n", intf->type);
403 static int modeset_init(struct mdp5_kms *mdp5_kms)
405 struct drm_device *dev = mdp5_kms->dev;
406 struct msm_drm_private *priv = dev->dev_private;
407 const struct mdp5_cfg_hw *hw_cfg;
408 unsigned int num_crtcs;
409 int i, ret, pi = 0, ci = 0;
410 struct drm_plane *primary[MAX_BASES] = { NULL };
411 struct drm_plane *cursor[MAX_BASES] = { NULL };
413 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
416 * Construct encoders and modeset initialize connector devices
417 * for each external display interface.
419 for (i = 0; i < mdp5_kms->num_intfs; i++) {
420 ret = modeset_init_intf(mdp5_kms, mdp5_kms->intfs[i]);
426 * We should ideally have less number of encoders (set up by parsing
427 * the MDP5 interfaces) than the number of layer mixers present in HW,
428 * but let's be safe here anyway
430 num_crtcs = min(priv->num_encoders, mdp5_kms->num_hwmixers);
433 * Construct planes equaling the number of hw pipes, and CRTCs for the
434 * N encoders set up by the driver. The first N planes become primary
435 * planes for the CRTCs, with the remainder as overlay planes:
437 for (i = 0; i < mdp5_kms->num_hwpipes; i++) {
438 struct mdp5_hw_pipe *hwpipe = mdp5_kms->hwpipes[i];
439 struct drm_plane *plane;
440 enum drm_plane_type type;
443 type = DRM_PLANE_TYPE_PRIMARY;
444 else if (hwpipe->caps & MDP_PIPE_CAP_CURSOR)
445 type = DRM_PLANE_TYPE_CURSOR;
447 type = DRM_PLANE_TYPE_OVERLAY;
449 plane = mdp5_plane_init(dev, type);
451 ret = PTR_ERR(plane);
452 dev_err(dev->dev, "failed to construct plane %d (%d)\n", i, ret);
455 priv->planes[priv->num_planes++] = plane;
457 if (type == DRM_PLANE_TYPE_PRIMARY)
458 primary[pi++] = plane;
459 if (type == DRM_PLANE_TYPE_CURSOR)
460 cursor[ci++] = plane;
463 for (i = 0; i < num_crtcs; i++) {
464 struct drm_crtc *crtc;
466 crtc = mdp5_crtc_init(dev, primary[i], cursor[i], i);
469 dev_err(dev->dev, "failed to construct crtc %d (%d)\n", i, ret);
472 priv->crtcs[priv->num_crtcs++] = crtc;
476 * Now that we know the number of crtcs we've created, set the possible
477 * crtcs for the encoders
479 for (i = 0; i < priv->num_encoders; i++) {
480 struct drm_encoder *encoder = priv->encoders[i];
482 encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;
491 static void read_mdp_hw_revision(struct mdp5_kms *mdp5_kms,
492 u32 *major, u32 *minor)
494 struct device *dev = &mdp5_kms->pdev->dev;
497 pm_runtime_get_sync(dev);
498 version = mdp5_read(mdp5_kms, REG_MDP5_HW_VERSION);
499 pm_runtime_put_autosuspend(dev);
501 *major = FIELD(version, MDP5_HW_VERSION_MAJOR);
502 *minor = FIELD(version, MDP5_HW_VERSION_MINOR);
504 DBG("MDP5 version v%d.%d", *major, *minor);
507 static int get_clk(struct platform_device *pdev, struct clk **clkp,
508 const char *name, bool mandatory)
510 struct device *dev = &pdev->dev;
511 struct clk *clk = msm_clk_get(pdev, name);
512 if (IS_ERR(clk) && mandatory) {
513 dev_err(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk));
517 DBG("skipping %s", name);
524 static struct drm_encoder *get_encoder_from_crtc(struct drm_crtc *crtc)
526 struct drm_device *dev = crtc->dev;
527 struct drm_encoder *encoder;
529 drm_for_each_encoder(encoder, dev)
530 if (encoder->crtc == crtc)
536 static bool mdp5_get_scanoutpos(struct drm_device *dev, unsigned int pipe,
537 bool in_vblank_irq, int *vpos, int *hpos,
538 ktime_t *stime, ktime_t *etime,
539 const struct drm_display_mode *mode)
541 struct msm_drm_private *priv = dev->dev_private;
542 struct drm_crtc *crtc;
543 struct drm_encoder *encoder;
544 int line, vsw, vbp, vactive_start, vactive_end, vfp_end;
546 crtc = priv->crtcs[pipe];
548 DRM_ERROR("Invalid crtc %d\n", pipe);
552 encoder = get_encoder_from_crtc(crtc);
554 DRM_ERROR("no encoder found for crtc %d\n", pipe);
558 vsw = mode->crtc_vsync_end - mode->crtc_vsync_start;
559 vbp = mode->crtc_vtotal - mode->crtc_vsync_end;
562 * the line counter is 1 at the start of the VSYNC pulse and VTOTAL at
563 * the end of VFP. Translate the porch values relative to the line
567 vactive_start = vsw + vbp + 1;
569 vactive_end = vactive_start + mode->crtc_vdisplay;
571 /* last scan line before VSYNC */
572 vfp_end = mode->crtc_vtotal;
575 *stime = ktime_get();
577 line = mdp5_encoder_get_linecount(encoder);
579 if (line < vactive_start) {
580 line -= vactive_start;
581 } else if (line > vactive_end) {
582 line = line - vfp_end - vactive_start;
584 line -= vactive_start;
591 *etime = ktime_get();
596 static u32 mdp5_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
598 struct msm_drm_private *priv = dev->dev_private;
599 struct drm_crtc *crtc;
600 struct drm_encoder *encoder;
602 if (pipe < 0 || pipe >= priv->num_crtcs)
605 crtc = priv->crtcs[pipe];
609 encoder = get_encoder_from_crtc(crtc);
613 return mdp5_encoder_get_framecount(encoder);
616 struct msm_kms *mdp5_kms_init(struct drm_device *dev)
618 struct msm_drm_private *priv = dev->dev_private;
619 struct platform_device *pdev;
620 struct mdp5_kms *mdp5_kms;
621 struct mdp5_cfg *config;
623 struct msm_gem_address_space *aspace;
626 /* priv->kms would have been populated by the MDP5 driver */
631 mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
633 mdp_kms_init(&mdp5_kms->base, &kms_funcs);
635 pdev = mdp5_kms->pdev;
637 irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
640 dev_err(&pdev->dev, "failed to get irq: %d\n", ret);
646 config = mdp5_cfg_get_config(mdp5_kms->cfg);
648 /* make sure things are off before attaching iommu (bootloader could
649 * have left things on, in which case we'll start getting faults if
652 pm_runtime_get_sync(&pdev->dev);
653 for (i = 0; i < MDP5_INTF_NUM_MAX; i++) {
654 if (mdp5_cfg_intf_is_virtual(config->hw->intf.connect[i]) ||
655 !config->hw->intf.base[i])
657 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0);
659 mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(i), 0x3);
663 if (config->platform.iommu) {
664 aspace = msm_gem_address_space_create(&pdev->dev,
665 config->platform.iommu, "mdp5");
666 if (IS_ERR(aspace)) {
667 ret = PTR_ERR(aspace);
671 kms->aspace = aspace;
673 ret = aspace->mmu->funcs->attach(aspace->mmu, iommu_ports,
674 ARRAY_SIZE(iommu_ports));
676 dev_err(&pdev->dev, "failed to attach iommu: %d\n",
682 "no iommu, fallback to phys contig buffers for scanout\n");
686 pm_runtime_put_autosuspend(&pdev->dev);
688 ret = modeset_init(mdp5_kms);
690 dev_err(&pdev->dev, "modeset_init failed: %d\n", ret);
694 dev->mode_config.min_width = 0;
695 dev->mode_config.min_height = 0;
696 dev->mode_config.max_width = 0xffff;
697 dev->mode_config.max_height = 0xffff;
699 dev->driver->get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos;
700 dev->driver->get_scanout_position = mdp5_get_scanoutpos;
701 dev->driver->get_vblank_counter = mdp5_get_vblank_counter;
702 dev->max_vblank_count = 0xffffffff;
703 dev->vblank_disable_immediate = true;
708 mdp5_kms_destroy(kms);
712 static void mdp5_destroy(struct platform_device *pdev)
714 struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev);
718 mdp5_ctlm_destroy(mdp5_kms->ctlm);
720 mdp5_smp_destroy(mdp5_kms->smp);
722 mdp5_cfg_destroy(mdp5_kms->cfg);
724 for (i = 0; i < mdp5_kms->num_intfs; i++)
725 kfree(mdp5_kms->intfs[i]);
727 if (mdp5_kms->rpm_enabled)
728 pm_runtime_disable(&pdev->dev);
730 kfree(mdp5_kms->state);
733 static int construct_pipes(struct mdp5_kms *mdp5_kms, int cnt,
734 const enum mdp5_pipe *pipes, const uint32_t *offsets,
737 struct drm_device *dev = mdp5_kms->dev;
740 for (i = 0; i < cnt; i++) {
741 struct mdp5_hw_pipe *hwpipe;
743 hwpipe = mdp5_pipe_init(pipes[i], offsets[i], caps);
744 if (IS_ERR(hwpipe)) {
745 ret = PTR_ERR(hwpipe);
746 dev_err(dev->dev, "failed to construct pipe for %s (%d)\n",
747 pipe2name(pipes[i]), ret);
750 hwpipe->idx = mdp5_kms->num_hwpipes;
751 mdp5_kms->hwpipes[mdp5_kms->num_hwpipes++] = hwpipe;
757 static int hwpipe_init(struct mdp5_kms *mdp5_kms)
759 static const enum mdp5_pipe rgb_planes[] = {
760 SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3,
762 static const enum mdp5_pipe vig_planes[] = {
763 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3,
765 static const enum mdp5_pipe dma_planes[] = {
766 SSPP_DMA0, SSPP_DMA1,
768 static const enum mdp5_pipe cursor_planes[] = {
769 SSPP_CURSOR0, SSPP_CURSOR1,
771 const struct mdp5_cfg_hw *hw_cfg;
774 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
776 /* Construct RGB pipes: */
777 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_rgb.count, rgb_planes,
778 hw_cfg->pipe_rgb.base, hw_cfg->pipe_rgb.caps);
782 /* Construct video (VIG) pipes: */
783 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_vig.count, vig_planes,
784 hw_cfg->pipe_vig.base, hw_cfg->pipe_vig.caps);
788 /* Construct DMA pipes: */
789 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_dma.count, dma_planes,
790 hw_cfg->pipe_dma.base, hw_cfg->pipe_dma.caps);
794 /* Construct cursor pipes: */
795 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_cursor.count,
796 cursor_planes, hw_cfg->pipe_cursor.base,
797 hw_cfg->pipe_cursor.caps);
804 static int hwmixer_init(struct mdp5_kms *mdp5_kms)
806 struct drm_device *dev = mdp5_kms->dev;
807 const struct mdp5_cfg_hw *hw_cfg;
810 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
812 for (i = 0; i < hw_cfg->lm.count; i++) {
813 struct mdp5_hw_mixer *mixer;
815 mixer = mdp5_mixer_init(&hw_cfg->lm.instances[i]);
817 ret = PTR_ERR(mixer);
818 dev_err(dev->dev, "failed to construct LM%d (%d)\n",
823 mixer->idx = mdp5_kms->num_hwmixers;
824 mdp5_kms->hwmixers[mdp5_kms->num_hwmixers++] = mixer;
830 static int interface_init(struct mdp5_kms *mdp5_kms)
832 struct drm_device *dev = mdp5_kms->dev;
833 const struct mdp5_cfg_hw *hw_cfg;
834 const enum mdp5_intf_type *intf_types;
837 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
838 intf_types = hw_cfg->intf.connect;
840 for (i = 0; i < ARRAY_SIZE(hw_cfg->intf.connect); i++) {
841 struct mdp5_interface *intf;
843 if (intf_types[i] == INTF_DISABLED)
846 intf = kzalloc(sizeof(*intf), GFP_KERNEL);
848 dev_err(dev->dev, "failed to construct INTF%d\n", i);
853 intf->type = intf_types[i];
854 intf->mode = MDP5_INTF_MODE_NONE;
855 intf->idx = mdp5_kms->num_intfs;
856 mdp5_kms->intfs[mdp5_kms->num_intfs++] = intf;
862 static int mdp5_init(struct platform_device *pdev, struct drm_device *dev)
864 struct msm_drm_private *priv = dev->dev_private;
865 struct mdp5_kms *mdp5_kms;
866 struct mdp5_cfg *config;
870 mdp5_kms = devm_kzalloc(&pdev->dev, sizeof(*mdp5_kms), GFP_KERNEL);
876 platform_set_drvdata(pdev, mdp5_kms);
878 spin_lock_init(&mdp5_kms->resource_lock);
881 mdp5_kms->pdev = pdev;
883 drm_modeset_lock_init(&mdp5_kms->state_lock);
884 mdp5_kms->state = kzalloc(sizeof(*mdp5_kms->state), GFP_KERNEL);
885 if (!mdp5_kms->state) {
890 mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5");
891 if (IS_ERR(mdp5_kms->mmio)) {
892 ret = PTR_ERR(mdp5_kms->mmio);
896 /* mandatory clocks: */
897 ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus", true);
900 ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface", true);
903 ret = get_clk(pdev, &mdp5_kms->core_clk, "core", true);
906 ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync", true);
910 /* optional clocks: */
911 get_clk(pdev, &mdp5_kms->lut_clk, "lut", false);
913 /* we need to set a default rate before enabling. Set a safe
914 * rate first, then figure out hw revision, and then set a
917 clk_set_rate(mdp5_kms->core_clk, 200000000);
919 pm_runtime_enable(&pdev->dev);
920 mdp5_kms->rpm_enabled = true;
922 read_mdp_hw_revision(mdp5_kms, &major, &minor);
924 mdp5_kms->cfg = mdp5_cfg_init(mdp5_kms, major, minor);
925 if (IS_ERR(mdp5_kms->cfg)) {
926 ret = PTR_ERR(mdp5_kms->cfg);
927 mdp5_kms->cfg = NULL;
931 config = mdp5_cfg_get_config(mdp5_kms->cfg);
932 mdp5_kms->caps = config->hw->mdp.caps;
934 /* TODO: compute core clock rate at runtime */
935 clk_set_rate(mdp5_kms->core_clk, config->hw->max_clk);
938 * Some chipsets have a Shared Memory Pool (SMP), while others
939 * have dedicated latency buffering per source pipe instead;
940 * this section initializes the SMP:
942 if (mdp5_kms->caps & MDP_CAP_SMP) {
943 mdp5_kms->smp = mdp5_smp_init(mdp5_kms, &config->hw->smp);
944 if (IS_ERR(mdp5_kms->smp)) {
945 ret = PTR_ERR(mdp5_kms->smp);
946 mdp5_kms->smp = NULL;
951 mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, mdp5_kms->cfg);
952 if (IS_ERR(mdp5_kms->ctlm)) {
953 ret = PTR_ERR(mdp5_kms->ctlm);
954 mdp5_kms->ctlm = NULL;
958 ret = hwpipe_init(mdp5_kms);
962 ret = hwmixer_init(mdp5_kms);
966 ret = interface_init(mdp5_kms);
970 /* set uninit-ed kms */
971 priv->kms = &mdp5_kms->base.base;
980 static int mdp5_bind(struct device *dev, struct device *master, void *data)
982 struct drm_device *ddev = dev_get_drvdata(master);
983 struct platform_device *pdev = to_platform_device(dev);
987 return mdp5_init(pdev, ddev);
990 static void mdp5_unbind(struct device *dev, struct device *master,
993 struct platform_device *pdev = to_platform_device(dev);
998 static const struct component_ops mdp5_ops = {
1000 .unbind = mdp5_unbind,
1003 static int mdp5_dev_probe(struct platform_device *pdev)
1006 return component_add(&pdev->dev, &mdp5_ops);
1009 static int mdp5_dev_remove(struct platform_device *pdev)
1012 component_del(&pdev->dev, &mdp5_ops);
1016 static __maybe_unused int mdp5_runtime_suspend(struct device *dev)
1018 struct platform_device *pdev = to_platform_device(dev);
1019 struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev);
1023 return mdp5_disable(mdp5_kms);
1026 static __maybe_unused int mdp5_runtime_resume(struct device *dev)
1028 struct platform_device *pdev = to_platform_device(dev);
1029 struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev);
1033 return mdp5_enable(mdp5_kms);
1036 static const struct dev_pm_ops mdp5_pm_ops = {
1037 SET_RUNTIME_PM_OPS(mdp5_runtime_suspend, mdp5_runtime_resume, NULL)
1040 static const struct of_device_id mdp5_dt_match[] = {
1041 { .compatible = "qcom,mdp5", },
1042 /* to support downstream DT files */
1043 { .compatible = "qcom,mdss_mdp", },
1046 MODULE_DEVICE_TABLE(of, mdp5_dt_match);
1048 static struct platform_driver mdp5_driver = {
1049 .probe = mdp5_dev_probe,
1050 .remove = mdp5_dev_remove,
1053 .of_match_table = mdp5_dt_match,
1058 void __init msm_mdp_register(void)
1061 platform_driver_register(&mdp5_driver);
1064 void __exit msm_mdp_unregister(void)
1067 platform_driver_unregister(&mdp5_driver);