2 * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/sort.h>
22 #include <drm/drm_mode.h>
24 #include "drm_crtc_helper.h"
25 #include "drm_flip_work.h"
27 #define CURSOR_WIDTH 64
28 #define CURSOR_HEIGHT 64
30 #define SSPP_MAX (SSPP_RGB3 + 1) /* TODO: Add SSPP_MAX in mdp5.xml.h */
38 /* layer mixer used for this CRTC (+ its lock): */
39 #define GET_LM_ID(crtc_id) ((crtc_id == 3) ? 5 : crtc_id)
41 spinlock_t lm_lock; /* protect REG_MDP5_LM_* registers */
43 /* CTL used for this CRTC: */
46 /* if there is a pending flip, these will be non-null: */
47 struct drm_pending_vblank_event *event;
49 /* Bits have been flushed at the last commit,
50 * used to decide if a vsync has happened since last commit.
54 #define PENDING_CURSOR 0x1
55 #define PENDING_FLIP 0x2
58 /* for unref'ing cursor bo's after scanout completes: */
59 struct drm_flip_work unref_cursor_work;
61 struct mdp_irq vblank;
63 struct mdp_irq pp_done;
65 struct completion pp_completion;
70 /* protect REG_MDP5_LM_CURSOR* registers and cursor scanout_bo*/
73 /* current cursor being scanned out: */
74 struct drm_gem_object *scanout_bo;
75 uint32_t width, height;
79 #define to_mdp5_crtc(x) container_of(x, struct mdp5_crtc, base)
81 static struct mdp5_kms *get_kms(struct drm_crtc *crtc)
83 struct msm_drm_private *priv = crtc->dev->dev_private;
84 return to_mdp5_kms(to_mdp_kms(priv->kms));
87 static void request_pending(struct drm_crtc *crtc, uint32_t pending)
89 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
91 atomic_or(pending, &mdp5_crtc->pending);
92 mdp_irq_register(&get_kms(crtc)->base, &mdp5_crtc->vblank);
95 static void request_pp_done_pending(struct drm_crtc *crtc)
97 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
98 reinit_completion(&mdp5_crtc->pp_completion);
101 static u32 crtc_flush(struct drm_crtc *crtc, u32 flush_mask)
103 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
105 DBG("%s: flush=%08x", mdp5_crtc->name, flush_mask);
106 return mdp5_ctl_commit(mdp5_crtc->ctl, flush_mask);
110 * flush updates, to make sure hw is updated to new scanout fb,
111 * so that we can safely queue unref to current fb (ie. next
112 * vblank we know hw is done w/ previous scanout_fb).
114 static u32 crtc_flush_all(struct drm_crtc *crtc)
116 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
117 struct drm_plane *plane;
118 uint32_t flush_mask = 0;
120 /* this should not happen: */
121 if (WARN_ON(!mdp5_crtc->ctl))
124 drm_atomic_crtc_for_each_plane(plane, crtc) {
125 flush_mask |= mdp5_plane_get_flush(plane);
128 flush_mask |= mdp_ctl_flush_mask_lm(mdp5_crtc->lm);
130 return crtc_flush(crtc, flush_mask);
133 /* if file!=NULL, this is preclose potential cancel-flip path */
134 static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
136 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
137 struct drm_device *dev = crtc->dev;
138 struct drm_pending_vblank_event *event;
139 struct drm_plane *plane;
142 spin_lock_irqsave(&dev->event_lock, flags);
143 event = mdp5_crtc->event;
145 /* if regular vblank case (!file) or if cancel-flip from
146 * preclose on file that requested flip, then send the
149 if (!file || (event->base.file_priv == file)) {
150 mdp5_crtc->event = NULL;
151 DBG("%s: send event: %p", mdp5_crtc->name, event);
152 drm_crtc_send_vblank_event(crtc, event);
155 spin_unlock_irqrestore(&dev->event_lock, flags);
157 drm_atomic_crtc_for_each_plane(plane, crtc) {
158 mdp5_plane_complete_flip(plane);
161 if (mdp5_crtc->ctl && !crtc->state->enable) {
162 /* set STAGE_UNUSED for all layers */
163 mdp5_ctl_blend(mdp5_crtc->ctl, NULL, 0, 0);
164 mdp5_crtc->ctl = NULL;
168 static void unref_cursor_worker(struct drm_flip_work *work, void *val)
170 struct mdp5_crtc *mdp5_crtc =
171 container_of(work, struct mdp5_crtc, unref_cursor_work);
172 struct mdp5_kms *mdp5_kms = get_kms(&mdp5_crtc->base);
174 msm_gem_put_iova(val, mdp5_kms->id);
175 drm_gem_object_unreference_unlocked(val);
178 static void mdp5_crtc_destroy(struct drm_crtc *crtc)
180 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
182 drm_crtc_cleanup(crtc);
183 drm_flip_work_cleanup(&mdp5_crtc->unref_cursor_work);
189 * blend_setup() - blend all the planes of a CRTC
191 * If no base layer is available, border will be enabled as the base layer.
192 * Otherwise all layers will be blended based on their stage calculated
193 * in mdp5_crtc_atomic_check.
195 static void blend_setup(struct drm_crtc *crtc)
197 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
198 struct mdp5_kms *mdp5_kms = get_kms(crtc);
199 struct drm_plane *plane;
200 const struct mdp5_cfg_hw *hw_cfg;
201 struct mdp5_plane_state *pstate, *pstates[STAGE_MAX + 1] = {NULL};
202 const struct mdp_format *format;
203 uint32_t lm = mdp5_crtc->lm;
204 uint32_t blend_op, fg_alpha, bg_alpha, ctl_blend_flags = 0;
206 uint8_t stage[STAGE_MAX + 1];
207 int i, plane_cnt = 0;
208 #define blender(stage) ((stage) - STAGE0)
210 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
212 spin_lock_irqsave(&mdp5_crtc->lm_lock, flags);
214 /* ctl could be released already when we are shutting down: */
218 /* Collect all plane information */
219 drm_atomic_crtc_for_each_plane(plane, crtc) {
220 pstate = to_mdp5_plane_state(plane->state);
221 pstates[pstate->stage] = pstate;
222 stage[pstate->stage] = mdp5_plane_pipe(plane);
226 if (!pstates[STAGE_BASE]) {
227 ctl_blend_flags |= MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT;
228 DBG("Border Color is enabled");
231 /* The reset for blending */
232 for (i = STAGE0; i <= STAGE_MAX; i++) {
236 format = to_mdp_format(
237 msm_framebuffer_format(pstates[i]->base.fb));
238 plane = pstates[i]->base.plane;
239 blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
240 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(BG_CONST);
241 fg_alpha = pstates[i]->alpha;
242 bg_alpha = 0xFF - pstates[i]->alpha;
243 DBG("Stage %d fg_alpha %x bg_alpha %x", i, fg_alpha, bg_alpha);
245 if (format->alpha_enable && pstates[i]->premultiplied) {
246 blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
247 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
248 if (fg_alpha != 0xff) {
251 MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA |
252 MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA;
254 blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA;
256 } else if (format->alpha_enable) {
257 blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_PIXEL) |
258 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
259 if (fg_alpha != 0xff) {
262 MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA |
263 MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA |
264 MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA |
265 MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA;
267 blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA;
271 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(lm,
272 blender(i)), blend_op);
273 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(lm,
274 blender(i)), fg_alpha);
275 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(lm,
276 blender(i)), bg_alpha);
279 mdp5_ctl_blend(mdp5_crtc->ctl, stage, plane_cnt, ctl_blend_flags);
282 spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);
285 static void mdp5_crtc_mode_set_nofb(struct drm_crtc *crtc)
287 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
288 struct mdp5_kms *mdp5_kms = get_kms(crtc);
290 struct drm_display_mode *mode;
292 if (WARN_ON(!crtc->state))
295 mode = &crtc->state->adjusted_mode;
297 DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
298 mdp5_crtc->name, mode->base.id, mode->name,
299 mode->vrefresh, mode->clock,
300 mode->hdisplay, mode->hsync_start,
301 mode->hsync_end, mode->htotal,
302 mode->vdisplay, mode->vsync_start,
303 mode->vsync_end, mode->vtotal,
304 mode->type, mode->flags);
306 spin_lock_irqsave(&mdp5_crtc->lm_lock, flags);
307 mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(mdp5_crtc->lm),
308 MDP5_LM_OUT_SIZE_WIDTH(mode->hdisplay) |
309 MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay));
310 spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);
313 static void mdp5_crtc_disable(struct drm_crtc *crtc)
315 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
316 struct mdp5_kms *mdp5_kms = get_kms(crtc);
318 DBG("%s", mdp5_crtc->name);
320 if (WARN_ON(!mdp5_crtc->enabled))
323 if (mdp5_crtc->cmd_mode)
324 mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->pp_done);
326 mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->err);
327 mdp5_disable(mdp5_kms);
329 mdp5_crtc->enabled = false;
332 static void mdp5_crtc_enable(struct drm_crtc *crtc)
334 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
335 struct mdp5_kms *mdp5_kms = get_kms(crtc);
337 DBG("%s", mdp5_crtc->name);
339 if (WARN_ON(mdp5_crtc->enabled))
342 mdp5_enable(mdp5_kms);
343 mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->err);
345 if (mdp5_crtc->cmd_mode)
346 mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->pp_done);
348 mdp5_crtc->enabled = true;
352 struct drm_plane *plane;
353 struct mdp5_plane_state *state;
356 static int pstate_cmp(const void *a, const void *b)
358 struct plane_state *pa = (struct plane_state *)a;
359 struct plane_state *pb = (struct plane_state *)b;
360 return pa->state->zpos - pb->state->zpos;
363 /* is there a helper for this? */
364 static bool is_fullscreen(struct drm_crtc_state *cstate,
365 struct drm_plane_state *pstate)
367 return (pstate->crtc_x <= 0) && (pstate->crtc_y <= 0) &&
368 ((pstate->crtc_x + pstate->crtc_w) >= cstate->mode.hdisplay) &&
369 ((pstate->crtc_y + pstate->crtc_h) >= cstate->mode.vdisplay);
372 static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
373 struct drm_crtc_state *state)
375 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
376 struct mdp5_kms *mdp5_kms = get_kms(crtc);
377 struct drm_plane *plane;
378 struct drm_device *dev = crtc->dev;
379 struct plane_state pstates[STAGE_MAX + 1];
380 const struct mdp5_cfg_hw *hw_cfg;
381 const struct drm_plane_state *pstate;
382 int cnt = 0, base = 0, i;
384 DBG("%s: check", mdp5_crtc->name);
386 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
387 pstates[cnt].plane = plane;
388 pstates[cnt].state = to_mdp5_plane_state(pstate);
393 /* assign a stage based on sorted zpos property */
394 sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
396 /* if the bottom-most layer is not fullscreen, we need to use
397 * it for solid-color:
399 if ((cnt > 0) && !is_fullscreen(state, &pstates[0].state->base))
402 /* verify that there are not too many planes attached to crtc
403 * and that we don't have conflicting mixer stages:
405 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
407 if ((cnt + base) >= hw_cfg->lm.nb_stages) {
408 dev_err(dev->dev, "too many planes!\n");
412 for (i = 0; i < cnt; i++) {
413 pstates[i].state->stage = STAGE_BASE + i + base;
414 DBG("%s: assign pipe %s on stage=%d", mdp5_crtc->name,
415 pipe2name(mdp5_plane_pipe(pstates[i].plane)),
416 pstates[i].state->stage);
422 static void mdp5_crtc_atomic_begin(struct drm_crtc *crtc,
423 struct drm_crtc_state *old_crtc_state)
425 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
426 DBG("%s: begin", mdp5_crtc->name);
429 static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc,
430 struct drm_crtc_state *old_crtc_state)
432 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
433 struct drm_device *dev = crtc->dev;
436 DBG("%s: event: %p", mdp5_crtc->name, crtc->state->event);
438 WARN_ON(mdp5_crtc->event);
440 spin_lock_irqsave(&dev->event_lock, flags);
441 mdp5_crtc->event = crtc->state->event;
442 spin_unlock_irqrestore(&dev->event_lock, flags);
445 * If no CTL has been allocated in mdp5_crtc_atomic_check(),
446 * it means we are trying to flush a CRTC whose state is disabled:
447 * nothing else needs to be done.
449 if (unlikely(!mdp5_crtc->ctl))
454 /* PP_DONE irq is only used by command mode for now.
455 * It is better to request pending before FLUSH and START trigger
456 * to make sure no pp_done irq missed.
457 * This is safe because no pp_done will happen before SW trigger
460 if (mdp5_crtc->cmd_mode)
461 request_pp_done_pending(crtc);
463 mdp5_crtc->flushed_mask = crtc_flush_all(crtc);
465 request_pending(crtc, PENDING_FLIP);
468 static void get_roi(struct drm_crtc *crtc, uint32_t *roi_w, uint32_t *roi_h)
470 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
471 uint32_t xres = crtc->mode.hdisplay;
472 uint32_t yres = crtc->mode.vdisplay;
475 * Cursor Region Of Interest (ROI) is a plane read from cursor
476 * buffer to render. The ROI region is determined by the visibility of
477 * the cursor point. In the default Cursor image the cursor point will
478 * be at the top left of the cursor image, unless it is specified
479 * otherwise using hotspot feature.
481 * If the cursor point reaches the right (xres - x < cursor.width) or
482 * bottom (yres - y < cursor.height) boundary of the screen, then ROI
483 * width and ROI height need to be evaluated to crop the cursor image
485 * (xres-x) will be new cursor width when x > (xres - cursor.width)
486 * (yres-y) will be new cursor height when y > (yres - cursor.height)
488 *roi_w = min(mdp5_crtc->cursor.width, xres -
489 mdp5_crtc->cursor.x);
490 *roi_h = min(mdp5_crtc->cursor.height, yres -
491 mdp5_crtc->cursor.y);
494 static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,
495 struct drm_file *file, uint32_t handle,
496 uint32_t width, uint32_t height)
498 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
499 struct drm_device *dev = crtc->dev;
500 struct mdp5_kms *mdp5_kms = get_kms(crtc);
501 struct drm_gem_object *cursor_bo, *old_bo = NULL;
502 uint32_t blendcfg, cursor_addr, stride;
504 enum mdp5_cursor_alpha cur_alpha = CURSOR_ALPHA_PER_PIXEL;
505 uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
506 uint32_t roi_w, roi_h;
507 bool cursor_enable = true;
510 if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
511 dev_err(dev->dev, "bad cursor size: %dx%d\n", width, height);
515 if (NULL == mdp5_crtc->ctl)
520 cursor_enable = false;
524 cursor_bo = drm_gem_object_lookup(file, handle);
528 ret = msm_gem_get_iova(cursor_bo, mdp5_kms->id, &cursor_addr);
533 stride = width * drm_format_plane_cpp(DRM_FORMAT_ARGB8888, 0);
535 spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
536 old_bo = mdp5_crtc->cursor.scanout_bo;
538 mdp5_crtc->cursor.scanout_bo = cursor_bo;
539 mdp5_crtc->cursor.width = width;
540 mdp5_crtc->cursor.height = height;
542 get_roi(crtc, &roi_w, &roi_h);
544 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_STRIDE(lm), stride);
545 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_FORMAT(lm),
546 MDP5_LM_CURSOR_FORMAT_FORMAT(CURSOR_FMT_ARGB8888));
547 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_IMG_SIZE(lm),
548 MDP5_LM_CURSOR_IMG_SIZE_SRC_H(height) |
549 MDP5_LM_CURSOR_IMG_SIZE_SRC_W(width));
550 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm),
551 MDP5_LM_CURSOR_SIZE_ROI_H(roi_h) |
552 MDP5_LM_CURSOR_SIZE_ROI_W(roi_w));
553 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BASE_ADDR(lm), cursor_addr);
555 blendcfg = MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN;
556 blendcfg |= MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(cur_alpha);
557 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BLEND_CONFIG(lm), blendcfg);
559 spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
562 ret = mdp5_ctl_set_cursor(mdp5_crtc->ctl, 0, cursor_enable);
564 dev_err(dev->dev, "failed to %sable cursor: %d\n",
565 cursor_enable ? "en" : "dis", ret);
569 crtc_flush(crtc, flush_mask);
573 drm_flip_work_queue(&mdp5_crtc->unref_cursor_work, old_bo);
574 /* enable vblank to complete cursor work: */
575 request_pending(crtc, PENDING_CURSOR);
580 static int mdp5_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
582 struct mdp5_kms *mdp5_kms = get_kms(crtc);
583 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
584 uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
589 /* In case the CRTC is disabled, just drop the cursor update */
590 if (unlikely(!crtc->state->enable))
593 mdp5_crtc->cursor.x = x = max(x, 0);
594 mdp5_crtc->cursor.y = y = max(y, 0);
596 get_roi(crtc, &roi_w, &roi_h);
598 spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
599 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(mdp5_crtc->lm),
600 MDP5_LM_CURSOR_SIZE_ROI_H(roi_h) |
601 MDP5_LM_CURSOR_SIZE_ROI_W(roi_w));
602 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_START_XY(mdp5_crtc->lm),
603 MDP5_LM_CURSOR_START_XY_Y_START(y) |
604 MDP5_LM_CURSOR_START_XY_X_START(x));
605 spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
607 crtc_flush(crtc, flush_mask);
612 static const struct drm_crtc_funcs mdp5_crtc_funcs = {
613 .set_config = drm_atomic_helper_set_config,
614 .destroy = mdp5_crtc_destroy,
615 .page_flip = drm_atomic_helper_page_flip,
616 .set_property = drm_atomic_helper_crtc_set_property,
617 .reset = drm_atomic_helper_crtc_reset,
618 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
619 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
620 .cursor_set = mdp5_crtc_cursor_set,
621 .cursor_move = mdp5_crtc_cursor_move,
624 static const struct drm_crtc_helper_funcs mdp5_crtc_helper_funcs = {
625 .mode_set_nofb = mdp5_crtc_mode_set_nofb,
626 .disable = mdp5_crtc_disable,
627 .enable = mdp5_crtc_enable,
628 .atomic_check = mdp5_crtc_atomic_check,
629 .atomic_begin = mdp5_crtc_atomic_begin,
630 .atomic_flush = mdp5_crtc_atomic_flush,
633 static void mdp5_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus)
635 struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, vblank);
636 struct drm_crtc *crtc = &mdp5_crtc->base;
637 struct msm_drm_private *priv = crtc->dev->dev_private;
640 mdp_irq_unregister(&get_kms(crtc)->base, &mdp5_crtc->vblank);
642 pending = atomic_xchg(&mdp5_crtc->pending, 0);
644 if (pending & PENDING_FLIP) {
645 complete_flip(crtc, NULL);
648 if (pending & PENDING_CURSOR)
649 drm_flip_work_commit(&mdp5_crtc->unref_cursor_work, priv->wq);
652 static void mdp5_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
654 struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, err);
656 DBG("%s: error: %08x", mdp5_crtc->name, irqstatus);
659 static void mdp5_crtc_pp_done_irq(struct mdp_irq *irq, uint32_t irqstatus)
661 struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc,
664 complete(&mdp5_crtc->pp_completion);
667 static void mdp5_crtc_wait_for_pp_done(struct drm_crtc *crtc)
669 struct drm_device *dev = crtc->dev;
670 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
673 ret = wait_for_completion_timeout(&mdp5_crtc->pp_completion,
674 msecs_to_jiffies(50));
676 dev_warn(dev->dev, "pp done time out, lm=%d\n", mdp5_crtc->lm);
679 static void mdp5_crtc_wait_for_flush_done(struct drm_crtc *crtc)
681 struct drm_device *dev = crtc->dev;
682 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
685 /* Should not call this function if crtc is disabled. */
689 ret = drm_crtc_vblank_get(crtc);
693 ret = wait_event_timeout(dev->vblank[drm_crtc_index(crtc)].queue,
694 ((mdp5_ctl_get_commit_status(mdp5_crtc->ctl) &
695 mdp5_crtc->flushed_mask) == 0),
696 msecs_to_jiffies(50));
698 dev_warn(dev->dev, "vblank time out, crtc=%d\n", mdp5_crtc->id);
700 mdp5_crtc->flushed_mask = 0;
702 drm_crtc_vblank_put(crtc);
705 uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc)
707 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
708 return mdp5_crtc->vblank.irqmask;
711 void mdp5_crtc_set_pipeline(struct drm_crtc *crtc,
712 struct mdp5_interface *intf, struct mdp5_ctl *ctl)
714 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
715 struct mdp5_kms *mdp5_kms = get_kms(crtc);
716 int lm = mdp5_crtc_get_lm(crtc);
718 /* now that we know what irq's we want: */
719 mdp5_crtc->err.irqmask = intf2err(intf->num);
720 mdp5_crtc->vblank.irqmask = intf2vblank(lm, intf);
722 if ((intf->type == INTF_DSI) &&
723 (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)) {
724 mdp5_crtc->pp_done.irqmask = lm2ppdone(lm);
725 mdp5_crtc->pp_done.irq = mdp5_crtc_pp_done_irq;
726 mdp5_crtc->cmd_mode = true;
728 mdp5_crtc->pp_done.irqmask = 0;
729 mdp5_crtc->pp_done.irq = NULL;
730 mdp5_crtc->cmd_mode = false;
733 mdp_irq_update(&mdp5_kms->base);
735 mdp5_crtc->ctl = ctl;
736 mdp5_ctl_set_pipeline(ctl, intf, lm);
739 int mdp5_crtc_get_lm(struct drm_crtc *crtc)
741 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
742 return WARN_ON(!crtc) ? -EINVAL : mdp5_crtc->lm;
745 void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc)
747 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
749 if (mdp5_crtc->cmd_mode)
750 mdp5_crtc_wait_for_pp_done(crtc);
752 mdp5_crtc_wait_for_flush_done(crtc);
755 /* initialize crtc */
756 struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
757 struct drm_plane *plane, int id)
759 struct drm_crtc *crtc = NULL;
760 struct mdp5_crtc *mdp5_crtc;
762 mdp5_crtc = kzalloc(sizeof(*mdp5_crtc), GFP_KERNEL);
764 return ERR_PTR(-ENOMEM);
766 crtc = &mdp5_crtc->base;
769 mdp5_crtc->lm = GET_LM_ID(id);
771 spin_lock_init(&mdp5_crtc->lm_lock);
772 spin_lock_init(&mdp5_crtc->cursor.lock);
773 init_completion(&mdp5_crtc->pp_completion);
775 mdp5_crtc->vblank.irq = mdp5_crtc_vblank_irq;
776 mdp5_crtc->err.irq = mdp5_crtc_err_irq;
778 snprintf(mdp5_crtc->name, sizeof(mdp5_crtc->name), "%s:%d",
779 pipe2name(mdp5_plane_pipe(plane)), id);
781 drm_crtc_init_with_planes(dev, crtc, plane, NULL, &mdp5_crtc_funcs,
784 drm_flip_work_init(&mdp5_crtc->unref_cursor_work,
785 "unref cursor", unref_cursor_worker);
787 drm_crtc_helper_add(crtc, &mdp5_crtc_helper_funcs);