2 * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
17 struct mdp5_cfg_handler {
19 struct mdp5_cfg config;
22 /* mdp5_cfg must be exposed (used in mdp5.xml.h) */
23 const struct mdp5_cfg_hw *mdp5_cfg = NULL;
25 const struct mdp5_cfg_hw msm8x74v1_config = {
36 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
37 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
38 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
43 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
44 .flush_hw_mask = 0x0003ffff,
48 .base = { 0x01100, 0x01500, 0x01900 },
49 .caps = MDP_PIPE_CAP_HFLIP |
57 .base = { 0x01d00, 0x02100, 0x02500 },
58 .caps = MDP_PIPE_CAP_HFLIP |
65 .base = { 0x02900, 0x02d00 },
66 .caps = MDP_PIPE_CAP_HFLIP |
72 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
77 .base = { 0x04500, 0x04900, 0x04d00 },
81 .base = { 0x21a00, 0x21b00, 0x21c00 },
84 .base = { 0x21000, 0x21200, 0x21400, 0x21600 },
95 const struct mdp5_cfg_hw msm8x74v2_config = {
106 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
107 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
108 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
113 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
114 .flush_hw_mask = 0x0003ffff,
118 .base = { 0x01100, 0x01500, 0x01900 },
119 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
120 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
121 MDP_PIPE_CAP_DECIMATION,
125 .base = { 0x01d00, 0x02100, 0x02500 },
126 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
127 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
131 .base = { 0x02900, 0x02d00 },
132 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
136 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
139 .max_height = 0xFFFF,
143 .base = { 0x04500, 0x04900, 0x04d00 },
147 .base = { 0x13000, 0x13200 },
151 .base = { 0x12c00, 0x12d00, 0x12e00 },
154 .base = { 0x12400, 0x12600, 0x12800, 0x12a00 },
162 .max_clk = 200000000,
165 const struct mdp5_cfg_hw apq8084_config = {
169 .caps = MDP_CAP_SMP |
176 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
177 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
178 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
179 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
180 [SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
182 .reserved_state[0] = GENMASK(7, 0), /* first 8 MMBs */
184 /* Two SMP blocks are statically tied to RGB pipes: */
185 [16] = 2, [17] = 2, [18] = 2, [22] = 2,
190 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
191 .flush_hw_mask = 0x003fffff,
195 .base = { 0x01100, 0x01500, 0x01900, 0x01d00 },
196 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
197 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
198 MDP_PIPE_CAP_DECIMATION,
202 .base = { 0x02100, 0x02500, 0x02900, 0x02d00 },
203 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
204 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
208 .base = { 0x03100, 0x03500 },
209 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
213 .base = { 0x03900, 0x03d00, 0x04100, 0x04500, 0x04900, 0x04d00 },
216 .max_height = 0xFFFF,
220 .base = { 0x05100, 0x05500, 0x05900, 0x05d00 },
225 .base = { 0x13400, 0x13600, 0x13800 },
229 .base = { 0x12e00, 0x12f00, 0x13000, 0x13100 },
232 .base = { 0x12400, 0x12600, 0x12800, 0x12a00, 0x12c00 },
240 .max_clk = 320000000,
243 const struct mdp5_cfg_hw msm8x16_config = {
248 .caps = MDP_CAP_SMP |
255 [SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
256 [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
261 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
262 .flush_hw_mask = 0x4003ffff,
267 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
268 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
269 MDP_PIPE_CAP_DECIMATION,
273 .base = { 0x14000, 0x16000 },
274 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
275 MDP_PIPE_CAP_DECIMATION,
280 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
283 .count = 2, /* LM0 and LM3 */
284 .base = { 0x44000, 0x47000 },
287 .max_height = 0xFFFF,
295 .base = { 0x00000, 0x6a800 },
301 .max_clk = 320000000,
304 const struct mdp5_cfg_hw msm8x94_config = {
308 .caps = MDP_CAP_SMP |
315 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
316 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
317 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
318 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
319 [SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
321 .reserved_state[0] = GENMASK(23, 0), /* first 24 MMBs */
323 [1] = 1, [4] = 1, [7] = 1, [19] = 1,
324 [16] = 5, [17] = 5, [18] = 5, [22] = 5,
329 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
330 .flush_hw_mask = 0xf0ffffff,
334 .base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
335 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
336 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
337 MDP_PIPE_CAP_DECIMATION,
341 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
342 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
343 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
347 .base = { 0x24000, 0x26000 },
348 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
352 .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
355 .max_height = 0xFFFF,
359 .base = { 0x54000, 0x56000, 0x58000, 0x5a000 },
364 .base = { 0x78000, 0x78800, 0x79000 },
368 .base = { 0x70000, 0x70800, 0x71000, 0x71800 },
371 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
379 .max_clk = 400000000,
382 const struct mdp5_cfg_hw msm8x96_config = {
386 .caps = MDP_CAP_DSC |
392 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
393 .flush_hw_mask = 0xf4ffffff,
397 .base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
398 .caps = MDP_PIPE_CAP_HFLIP |
402 MDP_PIPE_CAP_DECIMATION |
403 MDP_PIPE_CAP_SW_PIX_EXT |
408 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
409 .caps = MDP_PIPE_CAP_HFLIP |
412 MDP_PIPE_CAP_DECIMATION |
413 MDP_PIPE_CAP_SW_PIX_EXT |
418 .base = { 0x24000, 0x26000 },
419 .caps = MDP_PIPE_CAP_HFLIP |
421 MDP_PIPE_CAP_SW_PIX_EXT |
426 .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
429 .max_height = 0xFFFF,
433 .base = { 0x54000, 0x56000 },
437 .base = { 0x78000, 0x78800, 0x79000 },
441 .base = { 0x70000, 0x70800, 0x71000, 0x71800 },
449 .base = { 0x80000, 0x80400 },
452 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
460 .max_clk = 412500000,
463 static const struct mdp5_cfg_handler cfg_handlers[] = {
464 { .revision = 0, .config = { .hw = &msm8x74v1_config } },
465 { .revision = 2, .config = { .hw = &msm8x74v2_config } },
466 { .revision = 3, .config = { .hw = &apq8084_config } },
467 { .revision = 6, .config = { .hw = &msm8x16_config } },
468 { .revision = 9, .config = { .hw = &msm8x94_config } },
469 { .revision = 7, .config = { .hw = &msm8x96_config } },
472 static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev);
474 const struct mdp5_cfg_hw *mdp5_cfg_get_hw_config(struct mdp5_cfg_handler *cfg_handler)
476 return cfg_handler->config.hw;
479 struct mdp5_cfg *mdp5_cfg_get_config(struct mdp5_cfg_handler *cfg_handler)
481 return &cfg_handler->config;
484 int mdp5_cfg_get_hw_rev(struct mdp5_cfg_handler *cfg_handler)
486 return cfg_handler->revision;
489 void mdp5_cfg_destroy(struct mdp5_cfg_handler *cfg_handler)
494 struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,
495 uint32_t major, uint32_t minor)
497 struct drm_device *dev = mdp5_kms->dev;
498 struct platform_device *pdev = dev->platformdev;
499 struct mdp5_cfg_handler *cfg_handler;
500 struct mdp5_cfg_platform *pconfig;
503 cfg_handler = kzalloc(sizeof(*cfg_handler), GFP_KERNEL);
504 if (unlikely(!cfg_handler)) {
510 dev_err(dev->dev, "unexpected MDP major version: v%d.%d\n",
516 /* only after mdp5_cfg global pointer's init can we access the hw */
517 for (i = 0; i < ARRAY_SIZE(cfg_handlers); i++) {
518 if (cfg_handlers[i].revision != minor)
520 mdp5_cfg = cfg_handlers[i].config.hw;
524 if (unlikely(!mdp5_cfg)) {
525 dev_err(dev->dev, "unexpected MDP minor revision: v%d.%d\n",
531 cfg_handler->revision = minor;
532 cfg_handler->config.hw = mdp5_cfg;
534 pconfig = mdp5_get_config(pdev);
535 memcpy(&cfg_handler->config.platform, pconfig, sizeof(*pconfig));
537 DBG("MDP5: %s hw config selected", mdp5_cfg->name);
543 mdp5_cfg_destroy(cfg_handler);
548 static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev)
550 static struct mdp5_cfg_platform config = {};
552 config.iommu = iommu_domain_alloc(&platform_bus_type);