GNU Linux-libre 4.19.211-gnu1
[releases.git] / drivers / gpu / drm / msm / hdmi / hdmi_audio.c
1 /*
2  * Copyright (C) 2013 Red Hat
3  * Author: Rob Clark <robdclark@gmail.com>
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of the GNU General Public License version 2 as published by
7  * the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program.  If not, see <http://www.gnu.org/licenses/>.
16  */
17
18 #include <linux/hdmi.h>
19 #include "hdmi.h"
20
21 /* maps MSM_HDMI_AUDIO_CHANNEL_n consts used by audio driver to # of channels: */
22 static int nchannels[] = { 2, 4, 6, 8 };
23
24 /* Supported HDMI Audio sample rates */
25 #define MSM_HDMI_SAMPLE_RATE_32KHZ              0
26 #define MSM_HDMI_SAMPLE_RATE_44_1KHZ            1
27 #define MSM_HDMI_SAMPLE_RATE_48KHZ              2
28 #define MSM_HDMI_SAMPLE_RATE_88_2KHZ            3
29 #define MSM_HDMI_SAMPLE_RATE_96KHZ              4
30 #define MSM_HDMI_SAMPLE_RATE_176_4KHZ           5
31 #define MSM_HDMI_SAMPLE_RATE_192KHZ             6
32 #define MSM_HDMI_SAMPLE_RATE_MAX                7
33
34
35 struct hdmi_msm_audio_acr {
36         uint32_t n;     /* N parameter for clock regeneration */
37         uint32_t cts;   /* CTS parameter for clock regeneration */
38 };
39
40 struct hdmi_msm_audio_arcs {
41         unsigned long int pixclock;
42         struct hdmi_msm_audio_acr lut[MSM_HDMI_SAMPLE_RATE_MAX];
43 };
44
45 #define HDMI_MSM_AUDIO_ARCS(pclk, ...) { (1000 * (pclk)), __VA_ARGS__ }
46
47 /* Audio constants lookup table for hdmi_msm_audio_acr_setup */
48 /* Valid Pixel-Clock rates: 25.2MHz, 27MHz, 27.03MHz, 74.25MHz, 148.5MHz */
49 static const struct hdmi_msm_audio_arcs acr_lut[] = {
50         /*  25.200MHz  */
51         HDMI_MSM_AUDIO_ARCS(25200, {
52                 {4096, 25200}, {6272, 28000}, {6144, 25200}, {12544, 28000},
53                 {12288, 25200}, {25088, 28000}, {24576, 25200} }),
54         /*  27.000MHz  */
55         HDMI_MSM_AUDIO_ARCS(27000, {
56                 {4096, 27000}, {6272, 30000}, {6144, 27000}, {12544, 30000},
57                 {12288, 27000}, {25088, 30000}, {24576, 27000} }),
58         /*  27.027MHz */
59         HDMI_MSM_AUDIO_ARCS(27030, {
60                 {4096, 27027}, {6272, 30030}, {6144, 27027}, {12544, 30030},
61                 {12288, 27027}, {25088, 30030}, {24576, 27027} }),
62         /*  74.250MHz */
63         HDMI_MSM_AUDIO_ARCS(74250, {
64                 {4096, 74250}, {6272, 82500}, {6144, 74250}, {12544, 82500},
65                 {12288, 74250}, {25088, 82500}, {24576, 74250} }),
66         /* 148.500MHz */
67         HDMI_MSM_AUDIO_ARCS(148500, {
68                 {4096, 148500}, {6272, 165000}, {6144, 148500}, {12544, 165000},
69                 {12288, 148500}, {25088, 165000}, {24576, 148500} }),
70 };
71
72 static const struct hdmi_msm_audio_arcs *get_arcs(unsigned long int pixclock)
73 {
74         int i;
75
76         for (i = 0; i < ARRAY_SIZE(acr_lut); i++) {
77                 const struct hdmi_msm_audio_arcs *arcs = &acr_lut[i];
78                 if (arcs->pixclock == pixclock)
79                         return arcs;
80         }
81
82         return NULL;
83 }
84
85 int msm_hdmi_audio_update(struct hdmi *hdmi)
86 {
87         struct hdmi_audio *audio = &hdmi->audio;
88         struct hdmi_audio_infoframe *info = &audio->infoframe;
89         const struct hdmi_msm_audio_arcs *arcs = NULL;
90         bool enabled = audio->enabled;
91         uint32_t acr_pkt_ctrl, vbi_pkt_ctrl, aud_pkt_ctrl;
92         uint32_t infofrm_ctrl, audio_config;
93
94         DBG("audio: enabled=%d, channels=%d, channel_allocation=0x%x, "
95                 "level_shift_value=%d, downmix_inhibit=%d, rate=%d",
96                 audio->enabled, info->channels,  info->channel_allocation,
97                 info->level_shift_value, info->downmix_inhibit, audio->rate);
98         DBG("video: power_on=%d, pixclock=%lu", hdmi->power_on, hdmi->pixclock);
99
100         if (enabled && !(hdmi->power_on && hdmi->pixclock)) {
101                 DBG("disabling audio: no video");
102                 enabled = false;
103         }
104
105         if (enabled) {
106                 arcs = get_arcs(hdmi->pixclock);
107                 if (!arcs) {
108                         DBG("disabling audio: unsupported pixclock: %lu",
109                                         hdmi->pixclock);
110                         enabled = false;
111                 }
112         }
113
114         /* Read first before writing */
115         acr_pkt_ctrl = hdmi_read(hdmi, REG_HDMI_ACR_PKT_CTRL);
116         vbi_pkt_ctrl = hdmi_read(hdmi, REG_HDMI_VBI_PKT_CTRL);
117         aud_pkt_ctrl = hdmi_read(hdmi, REG_HDMI_AUDIO_PKT_CTRL1);
118         infofrm_ctrl = hdmi_read(hdmi, REG_HDMI_INFOFRAME_CTRL0);
119         audio_config = hdmi_read(hdmi, REG_HDMI_AUDIO_CFG);
120
121         /* Clear N/CTS selection bits */
122         acr_pkt_ctrl &= ~HDMI_ACR_PKT_CTRL_SELECT__MASK;
123
124         if (enabled) {
125                 uint32_t n, cts, multiplier;
126                 enum hdmi_acr_cts select;
127                 uint8_t buf[14];
128
129                 n   = arcs->lut[audio->rate].n;
130                 cts = arcs->lut[audio->rate].cts;
131
132                 if ((MSM_HDMI_SAMPLE_RATE_192KHZ == audio->rate) ||
133                                 (MSM_HDMI_SAMPLE_RATE_176_4KHZ == audio->rate)) {
134                         multiplier = 4;
135                         n >>= 2; /* divide N by 4 and use multiplier */
136                 } else if ((MSM_HDMI_SAMPLE_RATE_96KHZ == audio->rate) ||
137                                 (MSM_HDMI_SAMPLE_RATE_88_2KHZ == audio->rate)) {
138                         multiplier = 2;
139                         n >>= 1; /* divide N by 2 and use multiplier */
140                 } else {
141                         multiplier = 1;
142                 }
143
144                 DBG("n=%u, cts=%u, multiplier=%u", n, cts, multiplier);
145
146                 acr_pkt_ctrl |= HDMI_ACR_PKT_CTRL_SOURCE;
147                 acr_pkt_ctrl |= HDMI_ACR_PKT_CTRL_AUDIO_PRIORITY;
148                 acr_pkt_ctrl |= HDMI_ACR_PKT_CTRL_N_MULTIPLIER(multiplier);
149
150                 if ((MSM_HDMI_SAMPLE_RATE_48KHZ == audio->rate) ||
151                                 (MSM_HDMI_SAMPLE_RATE_96KHZ == audio->rate) ||
152                                 (MSM_HDMI_SAMPLE_RATE_192KHZ == audio->rate))
153                         select = ACR_48;
154                 else if ((MSM_HDMI_SAMPLE_RATE_44_1KHZ == audio->rate) ||
155                                 (MSM_HDMI_SAMPLE_RATE_88_2KHZ == audio->rate) ||
156                                 (MSM_HDMI_SAMPLE_RATE_176_4KHZ == audio->rate))
157                         select = ACR_44;
158                 else /* default to 32k */
159                         select = ACR_32;
160
161                 acr_pkt_ctrl |= HDMI_ACR_PKT_CTRL_SELECT(select);
162
163                 hdmi_write(hdmi, REG_HDMI_ACR_0(select - 1),
164                                 HDMI_ACR_0_CTS(cts));
165                 hdmi_write(hdmi, REG_HDMI_ACR_1(select - 1),
166                                 HDMI_ACR_1_N(n));
167
168                 hdmi_write(hdmi, REG_HDMI_AUDIO_PKT_CTRL2,
169                                 COND(info->channels != 2, HDMI_AUDIO_PKT_CTRL2_LAYOUT) |
170                                 HDMI_AUDIO_PKT_CTRL2_OVERRIDE);
171
172                 acr_pkt_ctrl |= HDMI_ACR_PKT_CTRL_CONT;
173                 acr_pkt_ctrl |= HDMI_ACR_PKT_CTRL_SEND;
174
175                 /* configure infoframe: */
176                 hdmi_audio_infoframe_pack(info, buf, sizeof(buf));
177                 hdmi_write(hdmi, REG_HDMI_AUDIO_INFO0,
178                                 (buf[3] <<  0) | (buf[4] <<  8) |
179                                 (buf[5] << 16) | (buf[6] << 24));
180                 hdmi_write(hdmi, REG_HDMI_AUDIO_INFO1,
181                                 (buf[7] <<  0) | (buf[8] << 8));
182
183                 hdmi_write(hdmi, REG_HDMI_GC, 0);
184
185                 vbi_pkt_ctrl |= HDMI_VBI_PKT_CTRL_GC_ENABLE;
186                 vbi_pkt_ctrl |= HDMI_VBI_PKT_CTRL_GC_EVERY_FRAME;
187
188                 aud_pkt_ctrl |= HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND;
189
190                 infofrm_ctrl |= HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SEND;
191                 infofrm_ctrl |= HDMI_INFOFRAME_CTRL0_AUDIO_INFO_CONT;
192                 infofrm_ctrl |= HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE;
193                 infofrm_ctrl |= HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE;
194
195                 audio_config &= ~HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK;
196                 audio_config |= HDMI_AUDIO_CFG_FIFO_WATERMARK(4);
197                 audio_config |= HDMI_AUDIO_CFG_ENGINE_ENABLE;
198         } else {
199                 acr_pkt_ctrl &= ~HDMI_ACR_PKT_CTRL_CONT;
200                 acr_pkt_ctrl &= ~HDMI_ACR_PKT_CTRL_SEND;
201                 vbi_pkt_ctrl &= ~HDMI_VBI_PKT_CTRL_GC_ENABLE;
202                 vbi_pkt_ctrl &= ~HDMI_VBI_PKT_CTRL_GC_EVERY_FRAME;
203                 aud_pkt_ctrl &= ~HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND;
204                 infofrm_ctrl &= ~HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SEND;
205                 infofrm_ctrl &= ~HDMI_INFOFRAME_CTRL0_AUDIO_INFO_CONT;
206                 infofrm_ctrl &= ~HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE;
207                 infofrm_ctrl &= ~HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE;
208                 audio_config &= ~HDMI_AUDIO_CFG_ENGINE_ENABLE;
209         }
210
211         hdmi_write(hdmi, REG_HDMI_ACR_PKT_CTRL, acr_pkt_ctrl);
212         hdmi_write(hdmi, REG_HDMI_VBI_PKT_CTRL, vbi_pkt_ctrl);
213         hdmi_write(hdmi, REG_HDMI_AUDIO_PKT_CTRL1, aud_pkt_ctrl);
214         hdmi_write(hdmi, REG_HDMI_INFOFRAME_CTRL0, infofrm_ctrl);
215
216         hdmi_write(hdmi, REG_HDMI_AUD_INT,
217                         COND(enabled, HDMI_AUD_INT_AUD_FIFO_URUN_INT) |
218                         COND(enabled, HDMI_AUD_INT_AUD_SAM_DROP_INT));
219
220         hdmi_write(hdmi, REG_HDMI_AUDIO_CFG, audio_config);
221
222
223         DBG("audio %sabled", enabled ? "en" : "dis");
224
225         return 0;
226 }
227
228 int msm_hdmi_audio_info_setup(struct hdmi *hdmi, bool enabled,
229         uint32_t num_of_channels, uint32_t channel_allocation,
230         uint32_t level_shift, bool down_mix)
231 {
232         struct hdmi_audio *audio;
233
234         if (!hdmi)
235                 return -ENXIO;
236
237         audio = &hdmi->audio;
238
239         if (num_of_channels >= ARRAY_SIZE(nchannels))
240                 return -EINVAL;
241
242         audio->enabled = enabled;
243         audio->infoframe.channels = nchannels[num_of_channels];
244         audio->infoframe.channel_allocation = channel_allocation;
245         audio->infoframe.level_shift_value = level_shift;
246         audio->infoframe.downmix_inhibit = down_mix;
247
248         return msm_hdmi_audio_update(hdmi);
249 }
250
251 void msm_hdmi_audio_set_sample_rate(struct hdmi *hdmi, int rate)
252 {
253         struct hdmi_audio *audio;
254
255         if (!hdmi)
256                 return;
257
258         audio = &hdmi->audio;
259
260         if ((rate < 0) || (rate >= MSM_HDMI_SAMPLE_RATE_MAX))
261                 return;
262
263         audio->rate = rate;
264         msm_hdmi_audio_update(hdmi);
265 }