2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/interrupt.h>
20 #include <linux/of_device.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_irq.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/of_graph.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/spinlock.h>
27 #include <linux/mfd/syscon.h>
28 #include <linux/regmap.h>
29 #include <video/mipi_display.h>
36 #define DSI_RESET_TOGGLE_DELAY_MS 20
38 static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
46 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0
47 * makes all other registers 4-byte shifted down.
49 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and
50 * older, we read the DSI_VERSION register without any shift(offset
51 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In
52 * the case of DSI6G, this has to be zero (the offset points to a
53 * scratch register which we never touch)
56 ver = msm_readl(base + REG_DSI_VERSION);
58 /* older dsi host, there is no register shift */
59 ver = FIELD(ver, DSI_VERSION_MAJOR);
60 if (ver <= MSM_DSI_VER_MAJOR_V2) {
70 * newer host, offset 0 has 6G_HW_VERSION, the rest of the
71 * registers are shifted down, read DSI_VERSION again with
74 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION);
75 ver = FIELD(ver, DSI_VERSION_MAJOR);
76 if (ver == MSM_DSI_VER_MAJOR_6G) {
79 *minor = msm_readl(base + REG_DSI_6G_HW_VERSION);
87 #define DSI_ERR_STATE_ACK 0x0000
88 #define DSI_ERR_STATE_TIMEOUT 0x0001
89 #define DSI_ERR_STATE_DLN0_PHY 0x0002
90 #define DSI_ERR_STATE_FIFO 0x0004
91 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008
92 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010
93 #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020
95 #define DSI_CLK_CTRL_ENABLE_CLKS \
96 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \
97 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \
98 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \
99 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK)
101 struct msm_dsi_host {
102 struct mipi_dsi_host base;
104 struct platform_device *pdev;
105 struct drm_device *dev;
109 void __iomem *ctrl_base;
110 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
112 struct clk *bus_clks[DSI_BUS_CLK_MAX];
114 struct clk *byte_clk;
116 struct clk *pixel_clk;
117 struct clk *byte_clk_src;
118 struct clk *pixel_clk_src;
123 /* DSI v2 specific clocks */
125 struct clk *esc_clk_src;
126 struct clk *dsi_clk_src;
130 struct gpio_desc *disp_en_gpio;
131 struct gpio_desc *te_gpio;
133 const struct msm_dsi_cfg_handler *cfg_hnd;
135 struct completion dma_comp;
136 struct completion video_comp;
137 struct mutex dev_mutex;
138 struct mutex cmd_mutex;
139 struct mutex clk_mutex;
140 spinlock_t intr_lock; /* Protect interrupt ctrl register */
143 struct work_struct err_work;
144 struct work_struct hpd_work;
145 struct workqueue_struct *workqueue;
147 /* DSI 6G TX buffer*/
148 struct drm_gem_object *tx_gem_obj;
150 /* DSI v2 TX buffer */
152 dma_addr_t tx_buf_paddr;
160 struct drm_display_mode *mode;
162 /* connected device info */
163 struct device_node *device_node;
164 unsigned int channel;
166 enum mipi_dsi_pixel_format format;
167 unsigned long mode_flags;
169 /* lane data parsed via DT */
173 u32 dma_cmd_ctrl_restore;
180 static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt)
183 case MIPI_DSI_FMT_RGB565: return 16;
184 case MIPI_DSI_FMT_RGB666_PACKED: return 18;
185 case MIPI_DSI_FMT_RGB666:
186 case MIPI_DSI_FMT_RGB888:
191 static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg)
193 return msm_readl(msm_host->ctrl_base + reg);
195 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data)
197 msm_writel(data, msm_host->ctrl_base + reg);
200 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host);
201 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host);
203 static const struct msm_dsi_cfg_handler *dsi_get_config(
204 struct msm_dsi_host *msm_host)
206 const struct msm_dsi_cfg_handler *cfg_hnd = NULL;
207 struct device *dev = &msm_host->pdev->dev;
208 struct regulator *gdsc_reg;
211 u32 major = 0, minor = 0;
213 gdsc_reg = regulator_get(dev, "gdsc");
214 if (IS_ERR(gdsc_reg)) {
215 pr_err("%s: cannot get gdsc\n", __func__);
219 ahb_clk = clk_get(dev, "iface_clk");
220 if (IS_ERR(ahb_clk)) {
221 pr_err("%s: cannot get interface clock\n", __func__);
225 ret = regulator_enable(gdsc_reg);
227 pr_err("%s: unable to enable gdsc\n", __func__);
231 ret = clk_prepare_enable(ahb_clk);
233 pr_err("%s: unable to enable ahb_clk\n", __func__);
237 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor);
239 pr_err("%s: Invalid version\n", __func__);
243 cfg_hnd = msm_dsi_cfg_get(major, minor);
245 DBG("%s: Version %x:%x\n", __func__, major, minor);
248 clk_disable_unprepare(ahb_clk);
250 regulator_disable(gdsc_reg);
254 regulator_put(gdsc_reg);
259 static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host)
261 return container_of(host, struct msm_dsi_host, base);
264 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host)
266 struct regulator_bulk_data *s = msm_host->supplies;
267 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
268 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
272 for (i = num - 1; i >= 0; i--)
273 if (regs[i].disable_load >= 0)
274 regulator_set_load(s[i].consumer,
275 regs[i].disable_load);
277 regulator_bulk_disable(num, s);
280 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host)
282 struct regulator_bulk_data *s = msm_host->supplies;
283 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
284 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
288 for (i = 0; i < num; i++) {
289 if (regs[i].enable_load >= 0) {
290 ret = regulator_set_load(s[i].consumer,
291 regs[i].enable_load);
293 pr_err("regulator %d set op mode failed, %d\n",
300 ret = regulator_bulk_enable(num, s);
302 pr_err("regulator enable failed, %d\n", ret);
309 for (i--; i >= 0; i--)
310 regulator_set_load(s[i].consumer, regs[i].disable_load);
314 static int dsi_regulator_init(struct msm_dsi_host *msm_host)
316 struct regulator_bulk_data *s = msm_host->supplies;
317 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
318 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
321 for (i = 0; i < num; i++)
322 s[i].supply = regs[i].name;
324 ret = devm_regulator_bulk_get(&msm_host->pdev->dev, num, s);
326 pr_err("%s: failed to init regulator, ret=%d\n",
334 static int dsi_clk_init(struct msm_dsi_host *msm_host)
336 struct device *dev = &msm_host->pdev->dev;
337 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
338 const struct msm_dsi_config *cfg = cfg_hnd->cfg;
342 for (i = 0; i < cfg->num_bus_clks; i++) {
343 msm_host->bus_clks[i] = devm_clk_get(dev,
344 cfg->bus_clk_names[i]);
345 if (IS_ERR(msm_host->bus_clks[i])) {
346 ret = PTR_ERR(msm_host->bus_clks[i]);
347 pr_err("%s: Unable to get %s, ret = %d\n",
348 __func__, cfg->bus_clk_names[i], ret);
353 /* get link and source clocks */
354 msm_host->byte_clk = devm_clk_get(dev, "byte_clk");
355 if (IS_ERR(msm_host->byte_clk)) {
356 ret = PTR_ERR(msm_host->byte_clk);
357 pr_err("%s: can't find dsi_byte_clk. ret=%d\n",
359 msm_host->byte_clk = NULL;
363 msm_host->pixel_clk = devm_clk_get(dev, "pixel_clk");
364 if (IS_ERR(msm_host->pixel_clk)) {
365 ret = PTR_ERR(msm_host->pixel_clk);
366 pr_err("%s: can't find dsi_pixel_clk. ret=%d\n",
368 msm_host->pixel_clk = NULL;
372 msm_host->esc_clk = devm_clk_get(dev, "core_clk");
373 if (IS_ERR(msm_host->esc_clk)) {
374 ret = PTR_ERR(msm_host->esc_clk);
375 pr_err("%s: can't find dsi_esc_clk. ret=%d\n",
377 msm_host->esc_clk = NULL;
381 msm_host->byte_clk_src = clk_get_parent(msm_host->byte_clk);
382 if (!msm_host->byte_clk_src) {
384 pr_err("%s: can't find byte_clk_src. ret=%d\n", __func__, ret);
388 msm_host->pixel_clk_src = clk_get_parent(msm_host->pixel_clk);
389 if (!msm_host->pixel_clk_src) {
391 pr_err("%s: can't find pixel_clk_src. ret=%d\n", __func__, ret);
395 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) {
396 msm_host->src_clk = devm_clk_get(dev, "src_clk");
397 if (IS_ERR(msm_host->src_clk)) {
398 ret = PTR_ERR(msm_host->src_clk);
399 pr_err("%s: can't find dsi_src_clk. ret=%d\n",
401 msm_host->src_clk = NULL;
405 msm_host->esc_clk_src = clk_get_parent(msm_host->esc_clk);
406 if (!msm_host->esc_clk_src) {
408 pr_err("%s: can't get esc_clk_src. ret=%d\n",
413 msm_host->dsi_clk_src = clk_get_parent(msm_host->src_clk);
414 if (!msm_host->dsi_clk_src) {
416 pr_err("%s: can't get dsi_clk_src. ret=%d\n",
424 static int dsi_bus_clk_enable(struct msm_dsi_host *msm_host)
426 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
429 DBG("id=%d", msm_host->id);
431 for (i = 0; i < cfg->num_bus_clks; i++) {
432 ret = clk_prepare_enable(msm_host->bus_clks[i]);
434 pr_err("%s: failed to enable bus clock %d ret %d\n",
443 clk_disable_unprepare(msm_host->bus_clks[i]);
448 static void dsi_bus_clk_disable(struct msm_dsi_host *msm_host)
450 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
455 for (i = cfg->num_bus_clks - 1; i >= 0; i--)
456 clk_disable_unprepare(msm_host->bus_clks[i]);
459 static int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
463 DBG("Set clk rates: pclk=%d, byteclk=%d",
464 msm_host->mode->clock, msm_host->byte_clk_rate);
466 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
468 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
472 ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000);
474 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
478 ret = clk_prepare_enable(msm_host->esc_clk);
480 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
484 ret = clk_prepare_enable(msm_host->byte_clk);
486 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
490 ret = clk_prepare_enable(msm_host->pixel_clk);
492 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
499 clk_disable_unprepare(msm_host->byte_clk);
501 clk_disable_unprepare(msm_host->esc_clk);
506 static int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host)
510 DBG("Set clk rates: pclk=%d, byteclk=%d, esc_clk=%d, dsi_src_clk=%d",
511 msm_host->mode->clock, msm_host->byte_clk_rate,
512 msm_host->esc_clk_rate, msm_host->src_clk_rate);
514 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
516 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
520 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate);
522 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret);
526 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate);
528 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret);
532 ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000);
534 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
538 ret = clk_prepare_enable(msm_host->byte_clk);
540 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
544 ret = clk_prepare_enable(msm_host->esc_clk);
546 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
550 ret = clk_prepare_enable(msm_host->src_clk);
552 pr_err("%s: Failed to enable dsi src clk\n", __func__);
556 ret = clk_prepare_enable(msm_host->pixel_clk);
558 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
565 clk_disable_unprepare(msm_host->src_clk);
567 clk_disable_unprepare(msm_host->esc_clk);
569 clk_disable_unprepare(msm_host->byte_clk);
574 static int dsi_link_clk_enable(struct msm_dsi_host *msm_host)
576 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
578 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G)
579 return dsi_link_clk_enable_6g(msm_host);
581 return dsi_link_clk_enable_v2(msm_host);
584 static void dsi_link_clk_disable(struct msm_dsi_host *msm_host)
586 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
588 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
589 clk_disable_unprepare(msm_host->esc_clk);
590 clk_disable_unprepare(msm_host->pixel_clk);
591 clk_disable_unprepare(msm_host->byte_clk);
593 clk_disable_unprepare(msm_host->pixel_clk);
594 clk_disable_unprepare(msm_host->src_clk);
595 clk_disable_unprepare(msm_host->esc_clk);
596 clk_disable_unprepare(msm_host->byte_clk);
600 static int dsi_clk_ctrl(struct msm_dsi_host *msm_host, bool enable)
604 mutex_lock(&msm_host->clk_mutex);
606 ret = dsi_bus_clk_enable(msm_host);
608 pr_err("%s: Can not enable bus clk, %d\n",
612 ret = dsi_link_clk_enable(msm_host);
614 pr_err("%s: Can not enable link clk, %d\n",
616 dsi_bus_clk_disable(msm_host);
620 dsi_link_clk_disable(msm_host);
621 dsi_bus_clk_disable(msm_host);
625 mutex_unlock(&msm_host->clk_mutex);
629 static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host)
631 struct drm_display_mode *mode = msm_host->mode;
632 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
633 u8 lanes = msm_host->lanes;
634 u32 bpp = dsi_get_bpp(msm_host->format);
638 pr_err("%s: mode not set\n", __func__);
642 pclk_rate = mode->clock * 1000;
644 msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);
646 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
647 msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;
650 DBG("pclk=%d, bclk=%d", pclk_rate, msm_host->byte_clk_rate);
652 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk);
654 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) {
655 unsigned int esc_mhz, esc_div;
656 unsigned long byte_mhz;
658 msm_host->src_clk_rate = (pclk_rate * bpp) / 8;
661 * esc clock is byte clock followed by a 4 bit divider,
662 * we need to find an escape clock frequency within the
663 * mipi DSI spec range within the maximum divider limit
664 * We iterate here between an escape clock frequencey
665 * between 20 Mhz to 5 Mhz and pick up the first one
666 * that can be supported by our divider
669 byte_mhz = msm_host->byte_clk_rate / 1000000;
671 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) {
672 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz);
675 * TODO: Ideally, we shouldn't know what sort of divider
676 * is available in mmss_cc, we're just assuming that
677 * it'll always be a 4 bit divider. Need to come up with
680 if (esc_div >= 1 && esc_div <= 16)
687 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div;
689 DBG("esc=%d, src=%d", msm_host->esc_clk_rate,
690 msm_host->src_clk_rate);
696 static void dsi_phy_sw_reset(struct msm_dsi_host *msm_host)
699 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET);
700 /* Make sure fully reset */
703 dsi_write(msm_host, REG_DSI_PHY_RESET, 0);
707 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable)
712 spin_lock_irqsave(&msm_host->intr_lock, flags);
713 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
720 DBG("intr=%x enable=%d", intr, enable);
722 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr);
723 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
726 static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags)
728 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
730 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
731 return NON_BURST_SYNCH_PULSE;
733 return NON_BURST_SYNCH_EVENT;
736 static inline enum dsi_vid_dst_format dsi_get_vid_fmt(
737 const enum mipi_dsi_pixel_format mipi_fmt)
740 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888;
741 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE;
742 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666;
743 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565;
744 default: return VID_DST_FORMAT_RGB888;
748 static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt(
749 const enum mipi_dsi_pixel_format mipi_fmt)
752 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888;
753 case MIPI_DSI_FMT_RGB666_PACKED:
754 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666;
755 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565;
756 default: return CMD_DST_FORMAT_RGB888;
760 static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
761 u32 clk_pre, u32 clk_post)
763 u32 flags = msm_host->mode_flags;
764 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format;
765 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
769 dsi_write(msm_host, REG_DSI_CTRL, 0);
773 if (flags & MIPI_DSI_MODE_VIDEO) {
774 if (flags & MIPI_DSI_MODE_VIDEO_HSE)
775 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE;
776 if (flags & MIPI_DSI_MODE_VIDEO_HFP)
777 data |= DSI_VID_CFG0_HFP_POWER_STOP;
778 if (flags & MIPI_DSI_MODE_VIDEO_HBP)
779 data |= DSI_VID_CFG0_HBP_POWER_STOP;
780 if (flags & MIPI_DSI_MODE_VIDEO_HSA)
781 data |= DSI_VID_CFG0_HSA_POWER_STOP;
782 /* Always set low power stop mode for BLLP
783 * to let command engine send packets
785 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP |
786 DSI_VID_CFG0_BLLP_POWER_STOP;
787 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags));
788 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt));
789 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel);
790 dsi_write(msm_host, REG_DSI_VID_CFG0, data);
792 /* Do not swap RGB colors */
793 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB);
794 dsi_write(msm_host, REG_DSI_VID_CFG1, 0);
796 /* Do not swap RGB colors */
797 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB);
798 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt));
799 dsi_write(msm_host, REG_DSI_CMD_CFG0, data);
801 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) |
802 DSI_CMD_CFG1_WR_MEM_CONTINUE(
803 MIPI_DCS_WRITE_MEMORY_CONTINUE);
804 /* Always insert DCS command */
805 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND;
806 dsi_write(msm_host, REG_DSI_CMD_CFG1, data);
809 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL,
810 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER |
811 DSI_CMD_DMA_CTRL_LOW_POWER);
814 /* Always assume dedicated TE pin */
815 data |= DSI_TRIG_CTRL_TE;
816 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE);
817 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW);
818 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel);
819 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
820 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2))
821 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME;
822 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data);
824 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(clk_post) |
825 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(clk_pre);
826 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data);
829 if (!(flags & MIPI_DSI_MODE_EOT_PACKET))
830 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND;
831 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data);
833 /* allow only ack-err-status to generate interrupt */
834 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0);
836 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
838 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
840 data = DSI_CTRL_CLK_EN;
842 DBG("lane number=%d", msm_host->lanes);
843 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0);
845 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
846 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap));
848 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
849 dsi_write(msm_host, REG_DSI_LANE_CTRL,
850 DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST);
852 data |= DSI_CTRL_ENABLE;
854 dsi_write(msm_host, REG_DSI_CTRL, data);
857 static void dsi_timing_setup(struct msm_dsi_host *msm_host)
859 struct drm_display_mode *mode = msm_host->mode;
860 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */
861 u32 h_total = mode->htotal;
862 u32 v_total = mode->vtotal;
863 u32 hs_end = mode->hsync_end - mode->hsync_start;
864 u32 vs_end = mode->vsync_end - mode->vsync_start;
865 u32 ha_start = h_total - mode->hsync_start;
866 u32 ha_end = ha_start + mode->hdisplay;
867 u32 va_start = v_total - mode->vsync_start;
868 u32 va_end = va_start + mode->vdisplay;
873 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
874 dsi_write(msm_host, REG_DSI_ACTIVE_H,
875 DSI_ACTIVE_H_START(ha_start) |
876 DSI_ACTIVE_H_END(ha_end));
877 dsi_write(msm_host, REG_DSI_ACTIVE_V,
878 DSI_ACTIVE_V_START(va_start) |
879 DSI_ACTIVE_V_END(va_end));
880 dsi_write(msm_host, REG_DSI_TOTAL,
881 DSI_TOTAL_H_TOTAL(h_total - 1) |
882 DSI_TOTAL_V_TOTAL(v_total - 1));
884 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC,
885 DSI_ACTIVE_HSYNC_START(hs_start) |
886 DSI_ACTIVE_HSYNC_END(hs_end));
887 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0);
888 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS,
889 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
890 DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
891 } else { /* command mode */
892 /* image data and 1 byte write_memory_start cmd */
893 wc = mode->hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
895 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_CTRL,
896 DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(wc) |
897 DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(
899 DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(
900 MIPI_DSI_DCS_LONG_WRITE));
902 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_TOTAL,
903 DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(mode->hdisplay) |
904 DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(mode->vdisplay));
908 static void dsi_sw_reset(struct msm_dsi_host *msm_host)
910 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
911 wmb(); /* clocks need to be enabled before reset */
913 dsi_write(msm_host, REG_DSI_RESET, 1);
914 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */
915 dsi_write(msm_host, REG_DSI_RESET, 0);
918 static void dsi_op_mode_config(struct msm_dsi_host *msm_host,
919 bool video_mode, bool enable)
923 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL);
926 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN |
927 DSI_CTRL_CMD_MODE_EN);
928 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE |
929 DSI_IRQ_MASK_VIDEO_DONE, 0);
932 dsi_ctrl |= DSI_CTRL_VID_MODE_EN;
933 } else { /* command mode */
934 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN;
935 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1);
937 dsi_ctrl |= DSI_CTRL_ENABLE;
940 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl);
943 static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host)
947 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL);
950 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER;
952 data |= DSI_CMD_DMA_CTRL_LOW_POWER;
954 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data);
957 static void dsi_wait4video_done(struct msm_dsi_host *msm_host)
959 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1);
961 reinit_completion(&msm_host->video_comp);
963 wait_for_completion_timeout(&msm_host->video_comp,
964 msecs_to_jiffies(70));
966 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0);
969 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host)
971 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
974 if (msm_host->power_on) {
975 dsi_wait4video_done(msm_host);
976 /* delay 4 ms to skip BLLP */
977 usleep_range(2000, 4000);
982 static int dsi_tx_buf_alloc(struct msm_dsi_host *msm_host, int size)
984 struct drm_device *dev = msm_host->dev;
985 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
989 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
990 mutex_lock(&dev->struct_mutex);
991 msm_host->tx_gem_obj = msm_gem_new(dev, size, MSM_BO_UNCACHED);
992 if (IS_ERR(msm_host->tx_gem_obj)) {
993 ret = PTR_ERR(msm_host->tx_gem_obj);
994 pr_err("%s: failed to allocate gem, %d\n",
996 msm_host->tx_gem_obj = NULL;
997 mutex_unlock(&dev->struct_mutex);
1001 ret = msm_gem_get_iova_locked(msm_host->tx_gem_obj, 0, &iova);
1002 mutex_unlock(&dev->struct_mutex);
1004 pr_err("%s: failed to get iova, %d\n", __func__, ret);
1009 pr_err("%s: buf NOT 8 bytes aligned\n", __func__);
1013 msm_host->tx_size = msm_host->tx_gem_obj->size;
1015 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size,
1016 &msm_host->tx_buf_paddr, GFP_KERNEL);
1017 if (!msm_host->tx_buf) {
1019 pr_err("%s: failed to allocate tx buf, %d\n",
1024 msm_host->tx_size = size;
1030 static void dsi_tx_buf_free(struct msm_dsi_host *msm_host)
1032 struct drm_device *dev = msm_host->dev;
1034 if (msm_host->tx_gem_obj) {
1035 msm_gem_put_iova(msm_host->tx_gem_obj, 0);
1036 mutex_lock(&dev->struct_mutex);
1037 msm_gem_free_object(msm_host->tx_gem_obj);
1038 msm_host->tx_gem_obj = NULL;
1039 mutex_unlock(&dev->struct_mutex);
1042 if (msm_host->tx_buf)
1043 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf,
1044 msm_host->tx_buf_paddr);
1048 * prepare cmd buffer to be txed
1050 static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host,
1051 const struct mipi_dsi_msg *msg)
1053 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1054 struct mipi_dsi_packet packet;
1059 ret = mipi_dsi_create_packet(&packet, msg);
1061 pr_err("%s: create packet failed, %d\n", __func__, ret);
1064 len = (packet.size + 3) & (~0x3);
1066 if (len > msm_host->tx_size) {
1067 pr_err("%s: packet size is too big\n", __func__);
1071 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
1072 data = msm_gem_get_vaddr(msm_host->tx_gem_obj);
1074 ret = PTR_ERR(data);
1075 pr_err("%s: get vaddr failed, %d\n", __func__, ret);
1079 data = msm_host->tx_buf;
1082 /* MSM specific command format in memory */
1083 data[0] = packet.header[1];
1084 data[1] = packet.header[2];
1085 data[2] = packet.header[0];
1086 data[3] = BIT(7); /* Last packet */
1087 if (mipi_dsi_packet_format_is_long(msg->type))
1089 if (msg->rx_buf && msg->rx_len)
1093 if (packet.payload && packet.payload_length)
1094 memcpy(data + 4, packet.payload, packet.payload_length);
1096 /* Append 0xff to the end */
1097 if (packet.size < len)
1098 memset(data + packet.size, 0xff, len - packet.size);
1100 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G)
1101 msm_gem_put_vaddr(msm_host->tx_gem_obj);
1107 * dsi_short_read1_resp: 1 parameter
1109 static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1111 u8 *data = msg->rx_buf;
1112 if (data && (msg->rx_len >= 1)) {
1113 *data = buf[1]; /* strip out dcs type */
1116 pr_err("%s: read data does not match with rx_buf len %zu\n",
1117 __func__, msg->rx_len);
1123 * dsi_short_read2_resp: 2 parameter
1125 static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1127 u8 *data = msg->rx_buf;
1128 if (data && (msg->rx_len >= 2)) {
1129 data[0] = buf[1]; /* strip out dcs type */
1133 pr_err("%s: read data does not match with rx_buf len %zu\n",
1134 __func__, msg->rx_len);
1139 static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1141 /* strip out 4 byte dcs header */
1142 if (msg->rx_buf && msg->rx_len)
1143 memcpy(msg->rx_buf, buf + 4, msg->rx_len);
1148 static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len)
1150 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1155 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
1156 ret = msm_gem_get_iova(msm_host->tx_gem_obj, 0, &dma_base);
1158 pr_err("%s: failed to get iova: %d\n", __func__, ret);
1162 dma_base = msm_host->tx_buf_paddr;
1165 reinit_completion(&msm_host->dma_comp);
1167 dsi_wait4video_eng_busy(msm_host);
1169 triggered = msm_dsi_manager_cmd_xfer_trigger(
1170 msm_host->id, dma_base, len);
1172 ret = wait_for_completion_timeout(&msm_host->dma_comp,
1173 msecs_to_jiffies(200));
1185 static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host,
1186 u8 *buf, int rx_byte, int pkt_size)
1188 u32 *lp, *temp, data;
1192 int repeated_bytes = 0;
1193 int buf_offset = buf - msm_host->rx_buf;
1197 cnt = (rx_byte + 3) >> 2;
1199 cnt = 4; /* 4 x 32 bits registers only */
1204 read_cnt = pkt_size + 6;
1207 * In case of multiple reads from the panel, after the first read, there
1208 * is possibility that there are some bytes in the payload repeating in
1209 * the RDBK_DATA registers. Since we read all the parameters from the
1210 * panel right from the first byte for every pass. We need to skip the
1211 * repeating bytes and then append the new parameters to the rx buffer.
1213 if (read_cnt > 16) {
1215 /* Any data more than 16 bytes will be shifted out.
1216 * The temp read buffer should already contain these bytes.
1217 * The remaining bytes in read buffer are the repeated bytes.
1219 bytes_shifted = read_cnt - 16;
1220 repeated_bytes = buf_offset - bytes_shifted;
1223 for (i = cnt - 1; i >= 0; i--) {
1224 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i));
1225 *temp++ = ntohl(data); /* to host byte order */
1226 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data));
1229 for (i = repeated_bytes; i < 16; i++)
1235 static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host,
1236 const struct mipi_dsi_msg *msg)
1239 int bllp_len = msm_host->mode->hdisplay *
1240 dsi_get_bpp(msm_host->format) / 8;
1242 len = dsi_cmd_dma_add(msm_host, msg);
1244 pr_err("%s: failed to add cmd type = 0x%x\n",
1245 __func__, msg->type);
1249 /* for video mode, do not send cmds more than
1250 * one pixel line, since it only transmit it
1253 /* TODO: if the command is sent in LP mode, the bit rate is only
1254 * half of esc clk rate. In this case, if the video is already
1255 * actively streaming, we need to check more carefully if the
1256 * command can be fit into one BLLP.
1258 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) {
1259 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n",
1264 ret = dsi_cmd_dma_tx(msm_host, len);
1266 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d, ret=%d\n",
1267 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len, ret);
1269 } else if (ret < len) {
1270 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, ret=%d len=%d\n",
1271 __func__, msg->type, (*(u8 *)(msg->tx_buf)), ret, len);
1278 static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host)
1282 data0 = dsi_read(msm_host, REG_DSI_CTRL);
1284 data1 &= ~DSI_CTRL_ENABLE;
1285 dsi_write(msm_host, REG_DSI_CTRL, data1);
1287 * dsi controller need to be disabled before
1292 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
1293 wmb(); /* make sure clocks enabled */
1295 /* dsi controller can only be reset while clocks are running */
1296 dsi_write(msm_host, REG_DSI_RESET, 1);
1297 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */
1298 dsi_write(msm_host, REG_DSI_RESET, 0);
1299 wmb(); /* controller out of reset */
1300 dsi_write(msm_host, REG_DSI_CTRL, data0);
1301 wmb(); /* make sure dsi controller enabled again */
1304 static void dsi_hpd_worker(struct work_struct *work)
1306 struct msm_dsi_host *msm_host =
1307 container_of(work, struct msm_dsi_host, hpd_work);
1309 drm_helper_hpd_irq_event(msm_host->dev);
1312 static void dsi_err_worker(struct work_struct *work)
1314 struct msm_dsi_host *msm_host =
1315 container_of(work, struct msm_dsi_host, err_work);
1316 u32 status = msm_host->err_work_state;
1318 pr_err_ratelimited("%s: status=%x\n", __func__, status);
1319 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW)
1320 dsi_sw_reset_restore(msm_host);
1322 /* It is safe to clear here because error irq is disabled. */
1323 msm_host->err_work_state = 0;
1325 /* enable dsi error interrupt */
1326 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
1329 static void dsi_ack_err_status(struct msm_dsi_host *msm_host)
1333 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS);
1336 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status);
1337 /* Writing of an extra 0 needed to clear error bits */
1338 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0);
1339 msm_host->err_work_state |= DSI_ERR_STATE_ACK;
1343 static void dsi_timeout_status(struct msm_dsi_host *msm_host)
1347 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS);
1350 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status);
1351 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT;
1355 static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host)
1359 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR);
1361 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC |
1362 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC |
1363 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL |
1364 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 |
1365 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) {
1366 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status);
1367 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY;
1371 static void dsi_fifo_status(struct msm_dsi_host *msm_host)
1375 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS);
1377 /* fifo underflow, overflow */
1379 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status);
1380 msm_host->err_work_state |= DSI_ERR_STATE_FIFO;
1381 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW)
1382 msm_host->err_work_state |=
1383 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW;
1387 static void dsi_status(struct msm_dsi_host *msm_host)
1391 status = dsi_read(msm_host, REG_DSI_STATUS0);
1393 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) {
1394 dsi_write(msm_host, REG_DSI_STATUS0, status);
1395 msm_host->err_work_state |=
1396 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION;
1400 static void dsi_clk_status(struct msm_dsi_host *msm_host)
1404 status = dsi_read(msm_host, REG_DSI_CLK_STATUS);
1406 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) {
1407 dsi_write(msm_host, REG_DSI_CLK_STATUS, status);
1408 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED;
1412 static void dsi_error(struct msm_dsi_host *msm_host)
1414 /* disable dsi error interrupt */
1415 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0);
1417 dsi_clk_status(msm_host);
1418 dsi_fifo_status(msm_host);
1419 dsi_ack_err_status(msm_host);
1420 dsi_timeout_status(msm_host);
1421 dsi_status(msm_host);
1422 dsi_dln0_phy_err(msm_host);
1424 queue_work(msm_host->workqueue, &msm_host->err_work);
1427 static irqreturn_t dsi_host_irq(int irq, void *ptr)
1429 struct msm_dsi_host *msm_host = ptr;
1431 unsigned long flags;
1433 if (!msm_host->ctrl_base)
1436 spin_lock_irqsave(&msm_host->intr_lock, flags);
1437 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
1438 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr);
1439 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
1441 DBG("isr=0x%x, id=%d", isr, msm_host->id);
1443 if (isr & DSI_IRQ_ERROR)
1444 dsi_error(msm_host);
1446 if (isr & DSI_IRQ_VIDEO_DONE)
1447 complete(&msm_host->video_comp);
1449 if (isr & DSI_IRQ_CMD_DMA_DONE)
1450 complete(&msm_host->dma_comp);
1455 static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host,
1456 struct device *panel_device)
1458 msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device,
1461 if (IS_ERR(msm_host->disp_en_gpio)) {
1462 DBG("cannot get disp-enable-gpios %ld",
1463 PTR_ERR(msm_host->disp_en_gpio));
1464 return PTR_ERR(msm_host->disp_en_gpio);
1467 msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te",
1469 if (IS_ERR(msm_host->te_gpio)) {
1470 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio));
1471 return PTR_ERR(msm_host->te_gpio);
1477 static int dsi_host_attach(struct mipi_dsi_host *host,
1478 struct mipi_dsi_device *dsi)
1480 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1483 if (dsi->lanes > msm_host->num_data_lanes)
1486 msm_host->channel = dsi->channel;
1487 msm_host->lanes = dsi->lanes;
1488 msm_host->format = dsi->format;
1489 msm_host->mode_flags = dsi->mode_flags;
1491 /* Some gpios defined in panel DT need to be controlled by host */
1492 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev);
1496 DBG("id=%d", msm_host->id);
1498 queue_work(msm_host->workqueue, &msm_host->hpd_work);
1503 static int dsi_host_detach(struct mipi_dsi_host *host,
1504 struct mipi_dsi_device *dsi)
1506 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1508 msm_host->device_node = NULL;
1510 DBG("id=%d", msm_host->id);
1512 queue_work(msm_host->workqueue, &msm_host->hpd_work);
1517 static ssize_t dsi_host_transfer(struct mipi_dsi_host *host,
1518 const struct mipi_dsi_msg *msg)
1520 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1523 if (!msg || !msm_host->power_on)
1526 mutex_lock(&msm_host->cmd_mutex);
1527 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg);
1528 mutex_unlock(&msm_host->cmd_mutex);
1533 static struct mipi_dsi_host_ops dsi_host_ops = {
1534 .attach = dsi_host_attach,
1535 .detach = dsi_host_detach,
1536 .transfer = dsi_host_transfer,
1540 * List of supported physical to logical lane mappings.
1541 * For example, the 2nd entry represents the following mapping:
1543 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3;
1545 static const int supported_data_lane_swaps[][4] = {
1556 static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host,
1557 struct device_node *ep)
1559 struct device *dev = &msm_host->pdev->dev;
1560 struct property *prop;
1562 int ret, i, len, num_lanes;
1564 prop = of_find_property(ep, "data-lanes", &len);
1566 dev_dbg(dev, "failed to find data lane mapping\n");
1570 num_lanes = len / sizeof(u32);
1572 if (num_lanes < 1 || num_lanes > 4) {
1573 dev_err(dev, "bad number of data lanes\n");
1577 msm_host->num_data_lanes = num_lanes;
1579 ret = of_property_read_u32_array(ep, "data-lanes", lane_map,
1582 dev_err(dev, "failed to read lane data\n");
1587 * compare DT specified physical-logical lane mappings with the ones
1588 * supported by hardware
1590 for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) {
1591 const int *swap = supported_data_lane_swaps[i];
1595 * the data-lanes array we get from DT has a logical->physical
1596 * mapping. The "data lane swap" register field represents
1597 * supported configurations in a physical->logical mapping.
1598 * Translate the DT mapping to what we understand and find a
1599 * configuration that works.
1601 for (j = 0; j < num_lanes; j++) {
1602 if (lane_map[j] < 0 || lane_map[j] > 3)
1603 dev_err(dev, "bad physical lane entry %u\n",
1606 if (swap[lane_map[j]] != j)
1610 if (j == num_lanes) {
1611 msm_host->dlane_swap = i;
1619 static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
1621 struct device *dev = &msm_host->pdev->dev;
1622 struct device_node *np = dev->of_node;
1623 struct device_node *endpoint, *device_node;
1627 * Get the endpoint of the output port of the DSI host. In our case,
1628 * this is mapped to port number with reg = 1. Don't return an error if
1629 * the remote endpoint isn't defined. It's possible that there is
1630 * nothing connected to the dsi output.
1632 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
1634 dev_dbg(dev, "%s: no endpoint\n", __func__);
1638 ret = dsi_host_parse_lane_data(msm_host, endpoint);
1640 dev_err(dev, "%s: invalid lane configuration %d\n",
1645 /* Get panel node from the output port's endpoint data */
1646 device_node = of_graph_get_remote_port_parent(endpoint);
1648 dev_err(dev, "%s: no valid device\n", __func__);
1653 msm_host->device_node = device_node;
1655 if (of_property_read_bool(np, "syscon-sfpb")) {
1656 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np,
1658 if (IS_ERR(msm_host->sfpb)) {
1659 dev_err(dev, "%s: failed to get sfpb regmap\n",
1661 ret = PTR_ERR(msm_host->sfpb);
1665 of_node_put(device_node);
1668 of_node_put(endpoint);
1673 static int dsi_host_get_id(struct msm_dsi_host *msm_host)
1675 struct platform_device *pdev = msm_host->pdev;
1676 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
1677 struct resource *res;
1680 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl");
1684 for (i = 0; i < cfg->num_dsi; i++) {
1685 if (cfg->io_start[i] == res->start)
1692 int msm_dsi_host_init(struct msm_dsi *msm_dsi)
1694 struct msm_dsi_host *msm_host = NULL;
1695 struct platform_device *pdev = msm_dsi->pdev;
1698 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL);
1700 pr_err("%s: FAILED: cannot alloc dsi host\n",
1706 msm_host->pdev = pdev;
1708 ret = dsi_host_parse_dt(msm_host);
1710 pr_err("%s: failed to parse dt\n", __func__);
1714 msm_host->ctrl_base = msm_ioremap(pdev, "dsi_ctrl", "DSI CTRL");
1715 if (IS_ERR(msm_host->ctrl_base)) {
1716 pr_err("%s: unable to map Dsi ctrl base\n", __func__);
1717 ret = PTR_ERR(msm_host->ctrl_base);
1721 msm_host->cfg_hnd = dsi_get_config(msm_host);
1722 if (!msm_host->cfg_hnd) {
1724 pr_err("%s: get config failed\n", __func__);
1728 msm_host->id = dsi_host_get_id(msm_host);
1729 if (msm_host->id < 0) {
1731 pr_err("%s: unable to identify DSI host index\n", __func__);
1735 /* fixup base address by io offset */
1736 msm_host->ctrl_base += msm_host->cfg_hnd->cfg->io_offset;
1738 ret = dsi_regulator_init(msm_host);
1740 pr_err("%s: regulator init failed\n", __func__);
1744 ret = dsi_clk_init(msm_host);
1746 pr_err("%s: unable to initialize dsi clks\n", __func__);
1750 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL);
1751 if (!msm_host->rx_buf) {
1752 pr_err("%s: alloc rx temp buf failed\n", __func__);
1756 init_completion(&msm_host->dma_comp);
1757 init_completion(&msm_host->video_comp);
1758 mutex_init(&msm_host->dev_mutex);
1759 mutex_init(&msm_host->cmd_mutex);
1760 mutex_init(&msm_host->clk_mutex);
1761 spin_lock_init(&msm_host->intr_lock);
1763 /* setup workqueue */
1764 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0);
1765 INIT_WORK(&msm_host->err_work, dsi_err_worker);
1766 INIT_WORK(&msm_host->hpd_work, dsi_hpd_worker);
1768 msm_dsi->host = &msm_host->base;
1769 msm_dsi->id = msm_host->id;
1771 DBG("Dsi Host %d initialized", msm_host->id);
1778 void msm_dsi_host_destroy(struct mipi_dsi_host *host)
1780 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1783 dsi_tx_buf_free(msm_host);
1784 if (msm_host->workqueue) {
1785 flush_workqueue(msm_host->workqueue);
1786 destroy_workqueue(msm_host->workqueue);
1787 msm_host->workqueue = NULL;
1790 mutex_destroy(&msm_host->clk_mutex);
1791 mutex_destroy(&msm_host->cmd_mutex);
1792 mutex_destroy(&msm_host->dev_mutex);
1795 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
1796 struct drm_device *dev)
1798 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1799 struct platform_device *pdev = msm_host->pdev;
1802 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1803 if (msm_host->irq < 0) {
1804 ret = msm_host->irq;
1805 dev_err(dev->dev, "failed to get irq: %d\n", ret);
1809 ret = devm_request_irq(&pdev->dev, msm_host->irq,
1810 dsi_host_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1811 "dsi_isr", msm_host);
1813 dev_err(&pdev->dev, "failed to request IRQ%u: %d\n",
1814 msm_host->irq, ret);
1818 msm_host->dev = dev;
1819 ret = dsi_tx_buf_alloc(msm_host, SZ_4K);
1821 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
1828 int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer)
1830 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1833 /* Register mipi dsi host */
1834 if (!msm_host->registered) {
1835 host->dev = &msm_host->pdev->dev;
1836 host->ops = &dsi_host_ops;
1837 ret = mipi_dsi_host_register(host);
1841 msm_host->registered = true;
1843 /* If the panel driver has not been probed after host register,
1844 * we should defer the host's probe.
1845 * It makes sure panel is connected when fbcon detects
1846 * connector status and gets the proper display mode to
1847 * create framebuffer.
1848 * Don't try to defer if there is nothing connected to the dsi
1851 if (check_defer && msm_host->device_node) {
1852 if (!of_drm_find_panel(msm_host->device_node))
1853 if (!of_drm_find_bridge(msm_host->device_node))
1854 return -EPROBE_DEFER;
1861 void msm_dsi_host_unregister(struct mipi_dsi_host *host)
1863 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1865 if (msm_host->registered) {
1866 mipi_dsi_host_unregister(host);
1869 msm_host->registered = false;
1873 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,
1874 const struct mipi_dsi_msg *msg)
1876 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1878 /* TODO: make sure dsi_cmd_mdp is idle.
1879 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME
1880 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed.
1881 * How to handle the old versions? Wait for mdp cmd done?
1885 * mdss interrupt is generated in mdp core clock domain
1886 * mdp clock need to be enabled to receive dsi interrupt
1888 dsi_clk_ctrl(msm_host, 1);
1890 /* TODO: vote for bus bandwidth */
1892 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
1893 dsi_set_tx_power_mode(0, msm_host);
1895 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL);
1896 dsi_write(msm_host, REG_DSI_CTRL,
1897 msm_host->dma_cmd_ctrl_restore |
1898 DSI_CTRL_CMD_MODE_EN |
1900 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1);
1905 void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host,
1906 const struct mipi_dsi_msg *msg)
1908 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1910 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0);
1911 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore);
1913 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
1914 dsi_set_tx_power_mode(1, msm_host);
1916 /* TODO: unvote for bus bandwidth */
1918 dsi_clk_ctrl(msm_host, 0);
1921 int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host,
1922 const struct mipi_dsi_msg *msg)
1924 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1926 return dsi_cmds2buf_tx(msm_host, msg);
1929 int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host,
1930 const struct mipi_dsi_msg *msg)
1932 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1933 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1934 int data_byte, rx_byte, dlen, end;
1935 int short_response, diff, pkt_size, ret = 0;
1937 int rlen = msg->rx_len;
1946 data_byte = 10; /* first read */
1947 if (rlen < data_byte)
1950 pkt_size = data_byte;
1951 rx_byte = data_byte + 6; /* 4 header + 2 crc */
1954 buf = msm_host->rx_buf;
1957 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8};
1958 struct mipi_dsi_msg max_pkt_size_msg = {
1959 .channel = msg->channel,
1960 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
1965 DBG("rlen=%d pkt_size=%d rx_byte=%d",
1966 rlen, pkt_size, rx_byte);
1968 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg);
1970 pr_err("%s: Set max pkt size failed, %d\n",
1975 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
1976 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) {
1977 /* Clear the RDBK_DATA registers */
1978 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL,
1979 DSI_RDBK_DATA_CTRL_CLR);
1980 wmb(); /* make sure the RDBK registers are cleared */
1981 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0);
1982 wmb(); /* release cleared status before transfer */
1985 ret = dsi_cmds2buf_tx(msm_host, msg);
1987 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret);
1989 } else if (ret < msg->tx_len) {
1990 pr_err("%s: Read cmd Tx failed, too short: %d\n", __func__, ret);
1995 * once cmd_dma_done interrupt received,
1996 * return data from client is ready and stored
1997 * at RDBK_DATA register already
1998 * since rx fifo is 16 bytes, dcs header is kept at first loop,
1999 * after that dcs header lost during shift into registers
2001 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size);
2009 if (rlen <= data_byte) {
2010 diff = data_byte - rlen;
2018 dlen -= 2; /* 2 crc */
2020 buf += dlen; /* next start position */
2021 data_byte = 14; /* NOT first read */
2022 if (rlen < data_byte)
2025 pkt_size += data_byte;
2026 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff);
2031 * For single Long read, if the requested rlen < 10,
2032 * we need to shift the start position of rx
2033 * data buffer to skip the bytes which are not
2036 if (pkt_size < 10 && !short_response)
2037 buf = msm_host->rx_buf + (10 - rlen);
2039 buf = msm_host->rx_buf;
2043 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
2044 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__);
2047 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
2048 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
2049 ret = dsi_short_read1_resp(buf, msg);
2051 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
2052 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
2053 ret = dsi_short_read2_resp(buf, msg);
2055 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
2056 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
2057 ret = dsi_long_read_resp(buf, msg);
2060 pr_warn("%s:Invalid response cmd\n", __func__);
2067 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base,
2070 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2072 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base);
2073 dsi_write(msm_host, REG_DSI_DMA_LEN, len);
2074 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1);
2076 /* Make sure trigger happens */
2080 int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
2081 struct msm_dsi_pll *src_pll)
2083 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2084 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2085 struct clk *byte_clk_provider, *pixel_clk_provider;
2088 ret = msm_dsi_pll_get_clk_provider(src_pll,
2089 &byte_clk_provider, &pixel_clk_provider);
2091 pr_info("%s: can't get provider from pll, don't set parent\n",
2096 ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider);
2098 pr_err("%s: can't set parent to byte_clk_src. ret=%d\n",
2103 ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider);
2105 pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n",
2110 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) {
2111 ret = clk_set_parent(msm_host->dsi_clk_src, pixel_clk_provider);
2113 pr_err("%s: can't set parent to dsi_clk_src. ret=%d\n",
2118 ret = clk_set_parent(msm_host->esc_clk_src, byte_clk_provider);
2120 pr_err("%s: can't set parent to esc_clk_src. ret=%d\n",
2130 int msm_dsi_host_enable(struct mipi_dsi_host *host)
2132 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2134 dsi_op_mode_config(msm_host,
2135 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true);
2137 /* TODO: clock should be turned off for command mode,
2138 * and only turned on before MDP START.
2139 * This part of code should be enabled once mdp driver support it.
2141 /* if (msm_panel->mode == MSM_DSI_CMD_MODE)
2142 dsi_clk_ctrl(msm_host, 0); */
2147 int msm_dsi_host_disable(struct mipi_dsi_host *host)
2149 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2151 dsi_op_mode_config(msm_host,
2152 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false);
2154 /* Since we have disabled INTF, the video engine won't stop so that
2155 * the cmd engine will be blocked.
2156 * Reset to disable video engine so that we can send off cmd.
2158 dsi_sw_reset(msm_host);
2163 static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable)
2165 enum sfpb_ahb_arb_master_port_en en;
2167 if (!msm_host->sfpb)
2170 en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE;
2172 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG,
2173 SFPB_GPREG_MASTER_PORT_EN__MASK,
2174 SFPB_GPREG_MASTER_PORT_EN(en));
2177 int msm_dsi_host_power_on(struct mipi_dsi_host *host)
2179 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2180 u32 clk_pre = 0, clk_post = 0;
2183 mutex_lock(&msm_host->dev_mutex);
2184 if (msm_host->power_on) {
2185 DBG("dsi host already on");
2189 msm_dsi_sfpb_config(msm_host, true);
2191 ret = dsi_calc_clk_rate(msm_host);
2193 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret);
2197 ret = dsi_host_regulator_enable(msm_host);
2199 pr_err("%s:Failed to enable vregs.ret=%d\n",
2204 ret = dsi_bus_clk_enable(msm_host);
2206 pr_err("%s: failed to enable bus clocks, %d\n", __func__, ret);
2207 goto fail_disable_reg;
2210 dsi_phy_sw_reset(msm_host);
2211 ret = msm_dsi_manager_phy_enable(msm_host->id,
2212 msm_host->byte_clk_rate * 8,
2213 msm_host->esc_clk_rate,
2214 &clk_pre, &clk_post);
2215 dsi_bus_clk_disable(msm_host);
2217 pr_err("%s: failed to enable phy, %d\n", __func__, ret);
2218 goto fail_disable_reg;
2221 ret = dsi_clk_ctrl(msm_host, 1);
2223 pr_err("%s: failed to enable clocks. ret=%d\n", __func__, ret);
2224 goto fail_disable_reg;
2227 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev);
2229 pr_err("%s: failed to set pinctrl default state, %d\n",
2231 goto fail_disable_clk;
2234 dsi_timing_setup(msm_host);
2235 dsi_sw_reset(msm_host);
2236 dsi_ctrl_config(msm_host, true, clk_pre, clk_post);
2238 if (msm_host->disp_en_gpio)
2239 gpiod_set_value(msm_host->disp_en_gpio, 1);
2241 msm_host->power_on = true;
2242 mutex_unlock(&msm_host->dev_mutex);
2247 dsi_clk_ctrl(msm_host, 0);
2249 dsi_host_regulator_disable(msm_host);
2251 mutex_unlock(&msm_host->dev_mutex);
2255 int msm_dsi_host_power_off(struct mipi_dsi_host *host)
2257 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2259 mutex_lock(&msm_host->dev_mutex);
2260 if (!msm_host->power_on) {
2261 DBG("dsi host already off");
2265 dsi_ctrl_config(msm_host, false, 0, 0);
2267 if (msm_host->disp_en_gpio)
2268 gpiod_set_value(msm_host->disp_en_gpio, 0);
2270 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev);
2272 msm_dsi_manager_phy_disable(msm_host->id);
2274 dsi_clk_ctrl(msm_host, 0);
2276 dsi_host_regulator_disable(msm_host);
2278 msm_dsi_sfpb_config(msm_host, false);
2282 msm_host->power_on = false;
2285 mutex_unlock(&msm_host->dev_mutex);
2289 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
2290 struct drm_display_mode *mode)
2292 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2294 if (msm_host->mode) {
2295 drm_mode_destroy(msm_host->dev, msm_host->mode);
2296 msm_host->mode = NULL;
2299 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode);
2300 if (!msm_host->mode) {
2301 pr_err("%s: cannot duplicate mode\n", __func__);
2308 struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host,
2309 unsigned long *panel_flags)
2311 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2312 struct drm_panel *panel;
2314 panel = of_drm_find_panel(msm_host->device_node);
2316 *panel_flags = msm_host->mode_flags;
2321 struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host)
2323 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2325 return of_drm_find_bridge(msm_host->device_node);