2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/interrupt.h>
20 #include <linux/of_device.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_irq.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/of_graph.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/spinlock.h>
27 #include <video/mipi_display.h>
33 #define DSI_RESET_TOGGLE_DELAY_MS 20
35 static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
43 /* From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0
44 * makes all other registers 4-byte shifted down.
46 ver_6g = msm_readl(base + REG_DSI_6G_HW_VERSION);
48 ver = msm_readl(base + REG_DSI_VERSION);
49 ver = FIELD(ver, DSI_VERSION_MAJOR);
50 if (ver <= MSM_DSI_VER_MAJOR_V2) {
59 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION);
60 ver = FIELD(ver, DSI_VERSION_MAJOR);
61 if (ver == MSM_DSI_VER_MAJOR_6G) {
72 #define DSI_ERR_STATE_ACK 0x0000
73 #define DSI_ERR_STATE_TIMEOUT 0x0001
74 #define DSI_ERR_STATE_DLN0_PHY 0x0002
75 #define DSI_ERR_STATE_FIFO 0x0004
76 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008
77 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010
78 #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020
80 #define DSI_CLK_CTRL_ENABLE_CLKS \
81 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \
82 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \
83 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \
84 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK)
87 struct mipi_dsi_host base;
89 struct platform_device *pdev;
90 struct drm_device *dev;
94 void __iomem *ctrl_base;
95 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
96 struct clk *mdp_core_clk;
99 struct clk *mmss_misc_ahb_clk;
100 struct clk *byte_clk;
102 struct clk *pixel_clk;
103 struct clk *byte_clk_src;
104 struct clk *pixel_clk_src;
108 struct gpio_desc *disp_en_gpio;
109 struct gpio_desc *te_gpio;
111 const struct msm_dsi_cfg_handler *cfg_hnd;
113 struct completion dma_comp;
114 struct completion video_comp;
115 struct mutex dev_mutex;
116 struct mutex cmd_mutex;
117 struct mutex clk_mutex;
118 spinlock_t intr_lock; /* Protect interrupt ctrl register */
121 struct work_struct err_work;
122 struct workqueue_struct *workqueue;
124 struct drm_gem_object *tx_gem_obj;
127 struct drm_display_mode *mode;
129 /* connected device info */
130 struct device_node *device_node;
131 unsigned int channel;
133 enum mipi_dsi_pixel_format format;
134 unsigned long mode_flags;
136 u32 dma_cmd_ctrl_restore;
143 static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt)
146 case MIPI_DSI_FMT_RGB565: return 16;
147 case MIPI_DSI_FMT_RGB666_PACKED: return 18;
148 case MIPI_DSI_FMT_RGB666:
149 case MIPI_DSI_FMT_RGB888:
154 static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg)
156 return msm_readl(msm_host->ctrl_base + reg);
158 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data)
160 msm_writel(data, msm_host->ctrl_base + reg);
163 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host);
164 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host);
166 static const struct msm_dsi_cfg_handler *dsi_get_config(
167 struct msm_dsi_host *msm_host)
169 const struct msm_dsi_cfg_handler *cfg_hnd = NULL;
170 struct regulator *gdsc_reg;
172 u32 major = 0, minor = 0;
174 gdsc_reg = regulator_get(&msm_host->pdev->dev, "gdsc");
175 if (IS_ERR(gdsc_reg)) {
176 pr_err("%s: cannot get gdsc\n", __func__);
179 ret = regulator_enable(gdsc_reg);
181 pr_err("%s: unable to enable gdsc\n", __func__);
184 ret = clk_prepare_enable(msm_host->ahb_clk);
186 pr_err("%s: unable to enable ahb_clk\n", __func__);
190 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor);
192 pr_err("%s: Invalid version\n", __func__);
196 cfg_hnd = msm_dsi_cfg_get(major, minor);
198 DBG("%s: Version %x:%x\n", __func__, major, minor);
201 clk_disable_unprepare(msm_host->ahb_clk);
203 regulator_disable(gdsc_reg);
205 regulator_put(gdsc_reg);
210 static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host)
212 return container_of(host, struct msm_dsi_host, base);
215 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host)
217 struct regulator_bulk_data *s = msm_host->supplies;
218 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
219 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
223 for (i = num - 1; i >= 0; i--)
224 if (regs[i].disable_load >= 0)
225 regulator_set_load(s[i].consumer,
226 regs[i].disable_load);
228 regulator_bulk_disable(num, s);
231 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host)
233 struct regulator_bulk_data *s = msm_host->supplies;
234 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
235 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
239 for (i = 0; i < num; i++) {
240 if (regs[i].enable_load >= 0) {
241 ret = regulator_set_load(s[i].consumer,
242 regs[i].enable_load);
244 pr_err("regulator %d set op mode failed, %d\n",
251 ret = regulator_bulk_enable(num, s);
253 pr_err("regulator enable failed, %d\n", ret);
260 for (i--; i >= 0; i--)
261 regulator_set_load(s[i].consumer, regs[i].disable_load);
265 static int dsi_regulator_init(struct msm_dsi_host *msm_host)
267 struct regulator_bulk_data *s = msm_host->supplies;
268 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
269 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
272 for (i = 0; i < num; i++)
273 s[i].supply = regs[i].name;
275 ret = devm_regulator_bulk_get(&msm_host->pdev->dev, num, s);
277 pr_err("%s: failed to init regulator, ret=%d\n",
282 for (i = 0; i < num; i++) {
283 if (regulator_can_change_voltage(s[i].consumer)) {
284 ret = regulator_set_voltage(s[i].consumer,
285 regs[i].min_voltage, regs[i].max_voltage);
287 pr_err("regulator %d set voltage failed, %d\n",
297 static int dsi_clk_init(struct msm_dsi_host *msm_host)
299 struct device *dev = &msm_host->pdev->dev;
302 msm_host->mdp_core_clk = devm_clk_get(dev, "mdp_core_clk");
303 if (IS_ERR(msm_host->mdp_core_clk)) {
304 ret = PTR_ERR(msm_host->mdp_core_clk);
305 pr_err("%s: Unable to get mdp core clk. ret=%d\n",
310 msm_host->ahb_clk = devm_clk_get(dev, "iface_clk");
311 if (IS_ERR(msm_host->ahb_clk)) {
312 ret = PTR_ERR(msm_host->ahb_clk);
313 pr_err("%s: Unable to get mdss ahb clk. ret=%d\n",
318 msm_host->axi_clk = devm_clk_get(dev, "bus_clk");
319 if (IS_ERR(msm_host->axi_clk)) {
320 ret = PTR_ERR(msm_host->axi_clk);
321 pr_err("%s: Unable to get axi bus clk. ret=%d\n",
326 msm_host->mmss_misc_ahb_clk = devm_clk_get(dev, "core_mmss_clk");
327 if (IS_ERR(msm_host->mmss_misc_ahb_clk)) {
328 ret = PTR_ERR(msm_host->mmss_misc_ahb_clk);
329 pr_err("%s: Unable to get mmss misc ahb clk. ret=%d\n",
334 msm_host->byte_clk = devm_clk_get(dev, "byte_clk");
335 if (IS_ERR(msm_host->byte_clk)) {
336 ret = PTR_ERR(msm_host->byte_clk);
337 pr_err("%s: can't find dsi_byte_clk. ret=%d\n",
339 msm_host->byte_clk = NULL;
343 msm_host->pixel_clk = devm_clk_get(dev, "pixel_clk");
344 if (IS_ERR(msm_host->pixel_clk)) {
345 ret = PTR_ERR(msm_host->pixel_clk);
346 pr_err("%s: can't find dsi_pixel_clk. ret=%d\n",
348 msm_host->pixel_clk = NULL;
352 msm_host->esc_clk = devm_clk_get(dev, "core_clk");
353 if (IS_ERR(msm_host->esc_clk)) {
354 ret = PTR_ERR(msm_host->esc_clk);
355 pr_err("%s: can't find dsi_esc_clk. ret=%d\n",
357 msm_host->esc_clk = NULL;
361 msm_host->byte_clk_src = devm_clk_get(dev, "byte_clk_src");
362 if (IS_ERR(msm_host->byte_clk_src)) {
363 ret = PTR_ERR(msm_host->byte_clk_src);
364 pr_err("%s: can't find byte_clk_src. ret=%d\n", __func__, ret);
365 msm_host->byte_clk_src = NULL;
369 msm_host->pixel_clk_src = devm_clk_get(dev, "pixel_clk_src");
370 if (IS_ERR(msm_host->pixel_clk_src)) {
371 ret = PTR_ERR(msm_host->pixel_clk_src);
372 pr_err("%s: can't find pixel_clk_src. ret=%d\n", __func__, ret);
373 msm_host->pixel_clk_src = NULL;
381 static int dsi_bus_clk_enable(struct msm_dsi_host *msm_host)
385 DBG("id=%d", msm_host->id);
387 ret = clk_prepare_enable(msm_host->mdp_core_clk);
389 pr_err("%s: failed to enable mdp_core_clock, %d\n",
394 ret = clk_prepare_enable(msm_host->ahb_clk);
396 pr_err("%s: failed to enable ahb clock, %d\n", __func__, ret);
400 ret = clk_prepare_enable(msm_host->axi_clk);
402 pr_err("%s: failed to enable ahb clock, %d\n", __func__, ret);
406 ret = clk_prepare_enable(msm_host->mmss_misc_ahb_clk);
408 pr_err("%s: failed to enable mmss misc ahb clk, %d\n",
410 goto misc_ahb_clk_err;
416 clk_disable_unprepare(msm_host->axi_clk);
418 clk_disable_unprepare(msm_host->ahb_clk);
420 clk_disable_unprepare(msm_host->mdp_core_clk);
425 static void dsi_bus_clk_disable(struct msm_dsi_host *msm_host)
428 clk_disable_unprepare(msm_host->mmss_misc_ahb_clk);
429 clk_disable_unprepare(msm_host->axi_clk);
430 clk_disable_unprepare(msm_host->ahb_clk);
431 clk_disable_unprepare(msm_host->mdp_core_clk);
434 static int dsi_link_clk_enable(struct msm_dsi_host *msm_host)
438 DBG("Set clk rates: pclk=%d, byteclk=%d",
439 msm_host->mode->clock, msm_host->byte_clk_rate);
441 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
443 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
447 ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000);
449 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
453 ret = clk_prepare_enable(msm_host->esc_clk);
455 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
459 ret = clk_prepare_enable(msm_host->byte_clk);
461 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
465 ret = clk_prepare_enable(msm_host->pixel_clk);
467 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
474 clk_disable_unprepare(msm_host->byte_clk);
476 clk_disable_unprepare(msm_host->esc_clk);
481 static void dsi_link_clk_disable(struct msm_dsi_host *msm_host)
483 clk_disable_unprepare(msm_host->esc_clk);
484 clk_disable_unprepare(msm_host->pixel_clk);
485 clk_disable_unprepare(msm_host->byte_clk);
488 static int dsi_clk_ctrl(struct msm_dsi_host *msm_host, bool enable)
492 mutex_lock(&msm_host->clk_mutex);
494 ret = dsi_bus_clk_enable(msm_host);
496 pr_err("%s: Can not enable bus clk, %d\n",
500 ret = dsi_link_clk_enable(msm_host);
502 pr_err("%s: Can not enable link clk, %d\n",
504 dsi_bus_clk_disable(msm_host);
508 dsi_link_clk_disable(msm_host);
509 dsi_bus_clk_disable(msm_host);
513 mutex_unlock(&msm_host->clk_mutex);
517 static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host)
519 struct drm_display_mode *mode = msm_host->mode;
520 u8 lanes = msm_host->lanes;
521 u32 bpp = dsi_get_bpp(msm_host->format);
525 pr_err("%s: mode not set\n", __func__);
529 pclk_rate = mode->clock * 1000;
531 msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);
533 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
534 msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;
537 DBG("pclk=%d, bclk=%d", pclk_rate, msm_host->byte_clk_rate);
542 static void dsi_phy_sw_reset(struct msm_dsi_host *msm_host)
545 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET);
546 /* Make sure fully reset */
549 dsi_write(msm_host, REG_DSI_PHY_RESET, 0);
553 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable)
558 spin_lock_irqsave(&msm_host->intr_lock, flags);
559 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
566 DBG("intr=%x enable=%d", intr, enable);
568 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr);
569 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
572 static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags)
574 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
576 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
577 return NON_BURST_SYNCH_PULSE;
579 return NON_BURST_SYNCH_EVENT;
582 static inline enum dsi_vid_dst_format dsi_get_vid_fmt(
583 const enum mipi_dsi_pixel_format mipi_fmt)
586 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888;
587 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE;
588 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666;
589 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565;
590 default: return VID_DST_FORMAT_RGB888;
594 static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt(
595 const enum mipi_dsi_pixel_format mipi_fmt)
598 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888;
599 case MIPI_DSI_FMT_RGB666_PACKED:
600 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666;
601 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565;
602 default: return CMD_DST_FORMAT_RGB888;
606 static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
607 u32 clk_pre, u32 clk_post)
609 u32 flags = msm_host->mode_flags;
610 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format;
611 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
615 dsi_write(msm_host, REG_DSI_CTRL, 0);
619 if (flags & MIPI_DSI_MODE_VIDEO) {
620 if (flags & MIPI_DSI_MODE_VIDEO_HSE)
621 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE;
622 if (flags & MIPI_DSI_MODE_VIDEO_HFP)
623 data |= DSI_VID_CFG0_HFP_POWER_STOP;
624 if (flags & MIPI_DSI_MODE_VIDEO_HBP)
625 data |= DSI_VID_CFG0_HBP_POWER_STOP;
626 if (flags & MIPI_DSI_MODE_VIDEO_HSA)
627 data |= DSI_VID_CFG0_HSA_POWER_STOP;
628 /* Always set low power stop mode for BLLP
629 * to let command engine send packets
631 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP |
632 DSI_VID_CFG0_BLLP_POWER_STOP;
633 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags));
634 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt));
635 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel);
636 dsi_write(msm_host, REG_DSI_VID_CFG0, data);
638 /* Do not swap RGB colors */
639 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB);
640 dsi_write(msm_host, REG_DSI_VID_CFG1, 0);
642 /* Do not swap RGB colors */
643 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB);
644 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt));
645 dsi_write(msm_host, REG_DSI_CMD_CFG0, data);
647 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) |
648 DSI_CMD_CFG1_WR_MEM_CONTINUE(
649 MIPI_DCS_WRITE_MEMORY_CONTINUE);
650 /* Always insert DCS command */
651 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND;
652 dsi_write(msm_host, REG_DSI_CMD_CFG1, data);
655 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL,
656 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER |
657 DSI_CMD_DMA_CTRL_LOW_POWER);
660 /* Always assume dedicated TE pin */
661 data |= DSI_TRIG_CTRL_TE;
662 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE);
663 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW);
664 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel);
665 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
666 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2))
667 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME;
668 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data);
670 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(clk_post) |
671 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(clk_pre);
672 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data);
675 if (!(flags & MIPI_DSI_MODE_EOT_PACKET))
676 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND;
677 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data);
679 /* allow only ack-err-status to generate interrupt */
680 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0);
682 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
684 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
686 data = DSI_CTRL_CLK_EN;
688 DBG("lane number=%d", msm_host->lanes);
689 if (msm_host->lanes == 2) {
690 data |= DSI_CTRL_LANE1 | DSI_CTRL_LANE2;
691 /* swap lanes for 2-lane panel for better performance */
692 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
693 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(LANE_SWAP_1230));
695 /* Take 4 lanes as default */
696 data |= DSI_CTRL_LANE0 | DSI_CTRL_LANE1 | DSI_CTRL_LANE2 |
698 /* Do not swap lanes for 4-lane panel */
699 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
700 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(LANE_SWAP_0123));
703 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
704 dsi_write(msm_host, REG_DSI_LANE_CTRL,
705 DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST);
707 data |= DSI_CTRL_ENABLE;
709 dsi_write(msm_host, REG_DSI_CTRL, data);
712 static void dsi_timing_setup(struct msm_dsi_host *msm_host)
714 struct drm_display_mode *mode = msm_host->mode;
715 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */
716 u32 h_total = mode->htotal;
717 u32 v_total = mode->vtotal;
718 u32 hs_end = mode->hsync_end - mode->hsync_start;
719 u32 vs_end = mode->vsync_end - mode->vsync_start;
720 u32 ha_start = h_total - mode->hsync_start;
721 u32 ha_end = ha_start + mode->hdisplay;
722 u32 va_start = v_total - mode->vsync_start;
723 u32 va_end = va_start + mode->vdisplay;
728 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
729 dsi_write(msm_host, REG_DSI_ACTIVE_H,
730 DSI_ACTIVE_H_START(ha_start) |
731 DSI_ACTIVE_H_END(ha_end));
732 dsi_write(msm_host, REG_DSI_ACTIVE_V,
733 DSI_ACTIVE_V_START(va_start) |
734 DSI_ACTIVE_V_END(va_end));
735 dsi_write(msm_host, REG_DSI_TOTAL,
736 DSI_TOTAL_H_TOTAL(h_total - 1) |
737 DSI_TOTAL_V_TOTAL(v_total - 1));
739 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC,
740 DSI_ACTIVE_HSYNC_START(hs_start) |
741 DSI_ACTIVE_HSYNC_END(hs_end));
742 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0);
743 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS,
744 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
745 DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
746 } else { /* command mode */
747 /* image data and 1 byte write_memory_start cmd */
748 wc = mode->hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
750 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_CTRL,
751 DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(wc) |
752 DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(
754 DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(
755 MIPI_DSI_DCS_LONG_WRITE));
757 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_TOTAL,
758 DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(mode->hdisplay) |
759 DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(mode->vdisplay));
763 static void dsi_sw_reset(struct msm_dsi_host *msm_host)
765 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
766 wmb(); /* clocks need to be enabled before reset */
768 dsi_write(msm_host, REG_DSI_RESET, 1);
769 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */
770 dsi_write(msm_host, REG_DSI_RESET, 0);
773 static void dsi_op_mode_config(struct msm_dsi_host *msm_host,
774 bool video_mode, bool enable)
778 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL);
781 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN |
782 DSI_CTRL_CMD_MODE_EN);
783 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE |
784 DSI_IRQ_MASK_VIDEO_DONE, 0);
787 dsi_ctrl |= DSI_CTRL_VID_MODE_EN;
788 } else { /* command mode */
789 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN;
790 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1);
792 dsi_ctrl |= DSI_CTRL_ENABLE;
795 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl);
798 static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host)
802 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL);
805 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER;
807 data |= DSI_CMD_DMA_CTRL_LOW_POWER;
809 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data);
812 static void dsi_wait4video_done(struct msm_dsi_host *msm_host)
814 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1);
816 reinit_completion(&msm_host->video_comp);
818 wait_for_completion_timeout(&msm_host->video_comp,
819 msecs_to_jiffies(70));
821 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0);
824 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host)
826 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
829 if (msm_host->power_on) {
830 dsi_wait4video_done(msm_host);
831 /* delay 4 ms to skip BLLP */
832 usleep_range(2000, 4000);
837 static int dsi_tx_buf_alloc(struct msm_dsi_host *msm_host, int size)
839 struct drm_device *dev = msm_host->dev;
843 mutex_lock(&dev->struct_mutex);
844 msm_host->tx_gem_obj = msm_gem_new(dev, size, MSM_BO_UNCACHED);
845 if (IS_ERR(msm_host->tx_gem_obj)) {
846 ret = PTR_ERR(msm_host->tx_gem_obj);
847 pr_err("%s: failed to allocate gem, %d\n", __func__, ret);
848 msm_host->tx_gem_obj = NULL;
849 mutex_unlock(&dev->struct_mutex);
853 ret = msm_gem_get_iova_locked(msm_host->tx_gem_obj, 0, &iova);
855 pr_err("%s: failed to get iova, %d\n", __func__, ret);
858 mutex_unlock(&dev->struct_mutex);
861 pr_err("%s: buf NOT 8 bytes aligned\n", __func__);
868 static void dsi_tx_buf_free(struct msm_dsi_host *msm_host)
870 struct drm_device *dev = msm_host->dev;
872 if (msm_host->tx_gem_obj) {
873 msm_gem_put_iova(msm_host->tx_gem_obj, 0);
874 mutex_lock(&dev->struct_mutex);
875 msm_gem_free_object(msm_host->tx_gem_obj);
876 msm_host->tx_gem_obj = NULL;
877 mutex_unlock(&dev->struct_mutex);
882 * prepare cmd buffer to be txed
884 static int dsi_cmd_dma_add(struct drm_gem_object *tx_gem,
885 const struct mipi_dsi_msg *msg)
887 struct mipi_dsi_packet packet;
892 ret = mipi_dsi_create_packet(&packet, msg);
894 pr_err("%s: create packet failed, %d\n", __func__, ret);
897 len = (packet.size + 3) & (~0x3);
899 if (len > tx_gem->size) {
900 pr_err("%s: packet size is too big\n", __func__);
904 data = msm_gem_vaddr(tx_gem);
908 pr_err("%s: get vaddr failed, %d\n", __func__, ret);
912 /* MSM specific command format in memory */
913 data[0] = packet.header[1];
914 data[1] = packet.header[2];
915 data[2] = packet.header[0];
916 data[3] = BIT(7); /* Last packet */
917 if (mipi_dsi_packet_format_is_long(msg->type))
919 if (msg->rx_buf && msg->rx_len)
923 if (packet.payload && packet.payload_length)
924 memcpy(data + 4, packet.payload, packet.payload_length);
926 /* Append 0xff to the end */
927 if (packet.size < len)
928 memset(data + packet.size, 0xff, len - packet.size);
934 * dsi_short_read1_resp: 1 parameter
936 static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg)
938 u8 *data = msg->rx_buf;
939 if (data && (msg->rx_len >= 1)) {
940 *data = buf[1]; /* strip out dcs type */
943 pr_err("%s: read data does not match with rx_buf len %zu\n",
944 __func__, msg->rx_len);
950 * dsi_short_read2_resp: 2 parameter
952 static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg)
954 u8 *data = msg->rx_buf;
955 if (data && (msg->rx_len >= 2)) {
956 data[0] = buf[1]; /* strip out dcs type */
960 pr_err("%s: read data does not match with rx_buf len %zu\n",
961 __func__, msg->rx_len);
966 static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg)
968 /* strip out 4 byte dcs header */
969 if (msg->rx_buf && msg->rx_len)
970 memcpy(msg->rx_buf, buf + 4, msg->rx_len);
976 static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len)
982 ret = msm_gem_get_iova(msm_host->tx_gem_obj, 0, &iova);
984 pr_err("%s: failed to get iova: %d\n", __func__, ret);
988 reinit_completion(&msm_host->dma_comp);
990 dsi_wait4video_eng_busy(msm_host);
992 triggered = msm_dsi_manager_cmd_xfer_trigger(
993 msm_host->id, iova, len);
995 ret = wait_for_completion_timeout(&msm_host->dma_comp,
996 msecs_to_jiffies(200));
1008 static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host,
1009 u8 *buf, int rx_byte, int pkt_size)
1011 u32 *lp, *temp, data;
1015 int repeated_bytes = 0;
1016 int buf_offset = buf - msm_host->rx_buf;
1020 cnt = (rx_byte + 3) >> 2;
1022 cnt = 4; /* 4 x 32 bits registers only */
1027 read_cnt = pkt_size + 6;
1030 * In case of multiple reads from the panel, after the first read, there
1031 * is possibility that there are some bytes in the payload repeating in
1032 * the RDBK_DATA registers. Since we read all the parameters from the
1033 * panel right from the first byte for every pass. We need to skip the
1034 * repeating bytes and then append the new parameters to the rx buffer.
1036 if (read_cnt > 16) {
1038 /* Any data more than 16 bytes will be shifted out.
1039 * The temp read buffer should already contain these bytes.
1040 * The remaining bytes in read buffer are the repeated bytes.
1042 bytes_shifted = read_cnt - 16;
1043 repeated_bytes = buf_offset - bytes_shifted;
1046 for (i = cnt - 1; i >= 0; i--) {
1047 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i));
1048 *temp++ = ntohl(data); /* to host byte order */
1049 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data));
1052 for (i = repeated_bytes; i < 16; i++)
1058 static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host,
1059 const struct mipi_dsi_msg *msg)
1062 int bllp_len = msm_host->mode->hdisplay *
1063 dsi_get_bpp(msm_host->format) / 8;
1065 len = dsi_cmd_dma_add(msm_host->tx_gem_obj, msg);
1067 pr_err("%s: failed to add cmd type = 0x%x\n",
1068 __func__, msg->type);
1072 /* for video mode, do not send cmds more than
1073 * one pixel line, since it only transmit it
1076 /* TODO: if the command is sent in LP mode, the bit rate is only
1077 * half of esc clk rate. In this case, if the video is already
1078 * actively streaming, we need to check more carefully if the
1079 * command can be fit into one BLLP.
1081 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) {
1082 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n",
1087 ret = dsi_cmd_dma_tx(msm_host, len);
1089 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d\n",
1090 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len);
1097 static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host)
1101 data0 = dsi_read(msm_host, REG_DSI_CTRL);
1103 data1 &= ~DSI_CTRL_ENABLE;
1104 dsi_write(msm_host, REG_DSI_CTRL, data1);
1106 * dsi controller need to be disabled before
1111 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
1112 wmb(); /* make sure clocks enabled */
1114 /* dsi controller can only be reset while clocks are running */
1115 dsi_write(msm_host, REG_DSI_RESET, 1);
1116 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */
1117 dsi_write(msm_host, REG_DSI_RESET, 0);
1118 wmb(); /* controller out of reset */
1119 dsi_write(msm_host, REG_DSI_CTRL, data0);
1120 wmb(); /* make sure dsi controller enabled again */
1123 static void dsi_err_worker(struct work_struct *work)
1125 struct msm_dsi_host *msm_host =
1126 container_of(work, struct msm_dsi_host, err_work);
1127 u32 status = msm_host->err_work_state;
1129 pr_err_ratelimited("%s: status=%x\n", __func__, status);
1130 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW)
1131 dsi_sw_reset_restore(msm_host);
1133 /* It is safe to clear here because error irq is disabled. */
1134 msm_host->err_work_state = 0;
1136 /* enable dsi error interrupt */
1137 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
1140 static void dsi_ack_err_status(struct msm_dsi_host *msm_host)
1144 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS);
1147 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status);
1148 /* Writing of an extra 0 needed to clear error bits */
1149 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0);
1150 msm_host->err_work_state |= DSI_ERR_STATE_ACK;
1154 static void dsi_timeout_status(struct msm_dsi_host *msm_host)
1158 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS);
1161 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status);
1162 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT;
1166 static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host)
1170 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR);
1172 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC |
1173 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC |
1174 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL |
1175 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 |
1176 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) {
1177 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status);
1178 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY;
1182 static void dsi_fifo_status(struct msm_dsi_host *msm_host)
1186 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS);
1188 /* fifo underflow, overflow */
1190 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status);
1191 msm_host->err_work_state |= DSI_ERR_STATE_FIFO;
1192 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW)
1193 msm_host->err_work_state |=
1194 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW;
1198 static void dsi_status(struct msm_dsi_host *msm_host)
1202 status = dsi_read(msm_host, REG_DSI_STATUS0);
1204 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) {
1205 dsi_write(msm_host, REG_DSI_STATUS0, status);
1206 msm_host->err_work_state |=
1207 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION;
1211 static void dsi_clk_status(struct msm_dsi_host *msm_host)
1215 status = dsi_read(msm_host, REG_DSI_CLK_STATUS);
1217 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) {
1218 dsi_write(msm_host, REG_DSI_CLK_STATUS, status);
1219 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED;
1223 static void dsi_error(struct msm_dsi_host *msm_host)
1225 /* disable dsi error interrupt */
1226 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0);
1228 dsi_clk_status(msm_host);
1229 dsi_fifo_status(msm_host);
1230 dsi_ack_err_status(msm_host);
1231 dsi_timeout_status(msm_host);
1232 dsi_status(msm_host);
1233 dsi_dln0_phy_err(msm_host);
1235 queue_work(msm_host->workqueue, &msm_host->err_work);
1238 static irqreturn_t dsi_host_irq(int irq, void *ptr)
1240 struct msm_dsi_host *msm_host = ptr;
1242 unsigned long flags;
1244 if (!msm_host->ctrl_base)
1247 spin_lock_irqsave(&msm_host->intr_lock, flags);
1248 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
1249 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr);
1250 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
1252 DBG("isr=0x%x, id=%d", isr, msm_host->id);
1254 if (isr & DSI_IRQ_ERROR)
1255 dsi_error(msm_host);
1257 if (isr & DSI_IRQ_VIDEO_DONE)
1258 complete(&msm_host->video_comp);
1260 if (isr & DSI_IRQ_CMD_DMA_DONE)
1261 complete(&msm_host->dma_comp);
1266 static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host,
1267 struct device *panel_device)
1269 msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device,
1272 if (IS_ERR(msm_host->disp_en_gpio)) {
1273 DBG("cannot get disp-enable-gpios %ld",
1274 PTR_ERR(msm_host->disp_en_gpio));
1275 return PTR_ERR(msm_host->disp_en_gpio);
1278 msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te",
1280 if (IS_ERR(msm_host->te_gpio)) {
1281 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio));
1282 return PTR_ERR(msm_host->te_gpio);
1288 static int dsi_host_attach(struct mipi_dsi_host *host,
1289 struct mipi_dsi_device *dsi)
1291 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1294 msm_host->channel = dsi->channel;
1295 msm_host->lanes = dsi->lanes;
1296 msm_host->format = dsi->format;
1297 msm_host->mode_flags = dsi->mode_flags;
1299 WARN_ON(dsi->dev.of_node != msm_host->device_node);
1301 /* Some gpios defined in panel DT need to be controlled by host */
1302 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev);
1306 DBG("id=%d", msm_host->id);
1308 drm_helper_hpd_irq_event(msm_host->dev);
1313 static int dsi_host_detach(struct mipi_dsi_host *host,
1314 struct mipi_dsi_device *dsi)
1316 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1318 msm_host->device_node = NULL;
1320 DBG("id=%d", msm_host->id);
1322 drm_helper_hpd_irq_event(msm_host->dev);
1327 static ssize_t dsi_host_transfer(struct mipi_dsi_host *host,
1328 const struct mipi_dsi_msg *msg)
1330 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1333 if (!msg || !msm_host->power_on)
1336 mutex_lock(&msm_host->cmd_mutex);
1337 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg);
1338 mutex_unlock(&msm_host->cmd_mutex);
1343 static struct mipi_dsi_host_ops dsi_host_ops = {
1344 .attach = dsi_host_attach,
1345 .detach = dsi_host_detach,
1346 .transfer = dsi_host_transfer,
1349 static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
1351 struct device *dev = &msm_host->pdev->dev;
1352 struct device_node *np = dev->of_node;
1353 struct device_node *endpoint, *device_node;
1356 ret = of_property_read_u32(np, "qcom,dsi-host-index", &msm_host->id);
1358 dev_err(dev, "%s: host index not specified, ret=%d\n",
1364 * Get the first endpoint node. In our case, dsi has one output port
1365 * to which the panel is connected. Don't return an error if a port
1366 * isn't defined. It's possible that there is nothing connected to
1369 endpoint = of_graph_get_next_endpoint(np, NULL);
1371 dev_dbg(dev, "%s: no endpoint\n", __func__);
1375 /* Get panel node from the output port's endpoint data */
1376 device_node = of_graph_get_remote_port_parent(endpoint);
1378 dev_err(dev, "%s: no valid device\n", __func__);
1379 of_node_put(endpoint);
1383 of_node_put(endpoint);
1384 of_node_put(device_node);
1386 msm_host->device_node = device_node;
1391 int msm_dsi_host_init(struct msm_dsi *msm_dsi)
1393 struct msm_dsi_host *msm_host = NULL;
1394 struct platform_device *pdev = msm_dsi->pdev;
1397 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL);
1399 pr_err("%s: FAILED: cannot alloc dsi host\n",
1405 msm_host->pdev = pdev;
1407 ret = dsi_host_parse_dt(msm_host);
1409 pr_err("%s: failed to parse dt\n", __func__);
1413 ret = dsi_clk_init(msm_host);
1415 pr_err("%s: unable to initialize dsi clks\n", __func__);
1419 msm_host->ctrl_base = msm_ioremap(pdev, "dsi_ctrl", "DSI CTRL");
1420 if (IS_ERR(msm_host->ctrl_base)) {
1421 pr_err("%s: unable to map Dsi ctrl base\n", __func__);
1422 ret = PTR_ERR(msm_host->ctrl_base);
1426 msm_host->cfg_hnd = dsi_get_config(msm_host);
1427 if (!msm_host->cfg_hnd) {
1429 pr_err("%s: get config failed\n", __func__);
1433 /* fixup base address by io offset */
1434 msm_host->ctrl_base += msm_host->cfg_hnd->cfg->io_offset;
1436 ret = dsi_regulator_init(msm_host);
1438 pr_err("%s: regulator init failed\n", __func__);
1442 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL);
1443 if (!msm_host->rx_buf) {
1444 pr_err("%s: alloc rx temp buf failed\n", __func__);
1448 init_completion(&msm_host->dma_comp);
1449 init_completion(&msm_host->video_comp);
1450 mutex_init(&msm_host->dev_mutex);
1451 mutex_init(&msm_host->cmd_mutex);
1452 mutex_init(&msm_host->clk_mutex);
1453 spin_lock_init(&msm_host->intr_lock);
1455 /* setup workqueue */
1456 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0);
1457 INIT_WORK(&msm_host->err_work, dsi_err_worker);
1459 msm_dsi->host = &msm_host->base;
1460 msm_dsi->id = msm_host->id;
1462 DBG("Dsi Host %d initialized", msm_host->id);
1469 void msm_dsi_host_destroy(struct mipi_dsi_host *host)
1471 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1474 dsi_tx_buf_free(msm_host);
1475 if (msm_host->workqueue) {
1476 flush_workqueue(msm_host->workqueue);
1477 destroy_workqueue(msm_host->workqueue);
1478 msm_host->workqueue = NULL;
1481 mutex_destroy(&msm_host->clk_mutex);
1482 mutex_destroy(&msm_host->cmd_mutex);
1483 mutex_destroy(&msm_host->dev_mutex);
1486 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
1487 struct drm_device *dev)
1489 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1490 struct platform_device *pdev = msm_host->pdev;
1493 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1494 if (msm_host->irq < 0) {
1495 ret = msm_host->irq;
1496 dev_err(dev->dev, "failed to get irq: %d\n", ret);
1500 ret = devm_request_irq(&pdev->dev, msm_host->irq,
1501 dsi_host_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1502 "dsi_isr", msm_host);
1504 dev_err(&pdev->dev, "failed to request IRQ%u: %d\n",
1505 msm_host->irq, ret);
1509 msm_host->dev = dev;
1510 ret = dsi_tx_buf_alloc(msm_host, SZ_4K);
1512 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
1519 int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer)
1521 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1524 /* Register mipi dsi host */
1525 if (!msm_host->registered) {
1526 host->dev = &msm_host->pdev->dev;
1527 host->ops = &dsi_host_ops;
1528 ret = mipi_dsi_host_register(host);
1532 msm_host->registered = true;
1534 /* If the panel driver has not been probed after host register,
1535 * we should defer the host's probe.
1536 * It makes sure panel is connected when fbcon detects
1537 * connector status and gets the proper display mode to
1538 * create framebuffer.
1539 * Don't try to defer if there is nothing connected to the dsi
1542 if (check_defer && msm_host->device_node) {
1543 if (!of_drm_find_panel(msm_host->device_node))
1544 if (!of_drm_find_bridge(msm_host->device_node))
1545 return -EPROBE_DEFER;
1552 void msm_dsi_host_unregister(struct mipi_dsi_host *host)
1554 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1556 if (msm_host->registered) {
1557 mipi_dsi_host_unregister(host);
1560 msm_host->registered = false;
1564 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,
1565 const struct mipi_dsi_msg *msg)
1567 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1569 /* TODO: make sure dsi_cmd_mdp is idle.
1570 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME
1571 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed.
1572 * How to handle the old versions? Wait for mdp cmd done?
1576 * mdss interrupt is generated in mdp core clock domain
1577 * mdp clock need to be enabled to receive dsi interrupt
1579 dsi_clk_ctrl(msm_host, 1);
1581 /* TODO: vote for bus bandwidth */
1583 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
1584 dsi_set_tx_power_mode(0, msm_host);
1586 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL);
1587 dsi_write(msm_host, REG_DSI_CTRL,
1588 msm_host->dma_cmd_ctrl_restore |
1589 DSI_CTRL_CMD_MODE_EN |
1591 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1);
1596 void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host,
1597 const struct mipi_dsi_msg *msg)
1599 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1601 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0);
1602 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore);
1604 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
1605 dsi_set_tx_power_mode(1, msm_host);
1607 /* TODO: unvote for bus bandwidth */
1609 dsi_clk_ctrl(msm_host, 0);
1612 int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host,
1613 const struct mipi_dsi_msg *msg)
1615 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1617 return dsi_cmds2buf_tx(msm_host, msg);
1620 int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host,
1621 const struct mipi_dsi_msg *msg)
1623 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1624 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1625 int data_byte, rx_byte, dlen, end;
1626 int short_response, diff, pkt_size, ret = 0;
1628 int rlen = msg->rx_len;
1637 data_byte = 10; /* first read */
1638 if (rlen < data_byte)
1641 pkt_size = data_byte;
1642 rx_byte = data_byte + 6; /* 4 header + 2 crc */
1645 buf = msm_host->rx_buf;
1648 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8};
1649 struct mipi_dsi_msg max_pkt_size_msg = {
1650 .channel = msg->channel,
1651 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
1656 DBG("rlen=%d pkt_size=%d rx_byte=%d",
1657 rlen, pkt_size, rx_byte);
1659 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg);
1661 pr_err("%s: Set max pkt size failed, %d\n",
1666 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
1667 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) {
1668 /* Clear the RDBK_DATA registers */
1669 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL,
1670 DSI_RDBK_DATA_CTRL_CLR);
1671 wmb(); /* make sure the RDBK registers are cleared */
1672 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0);
1673 wmb(); /* release cleared status before transfer */
1676 ret = dsi_cmds2buf_tx(msm_host, msg);
1677 if (ret < msg->tx_len) {
1678 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret);
1683 * once cmd_dma_done interrupt received,
1684 * return data from client is ready and stored
1685 * at RDBK_DATA register already
1686 * since rx fifo is 16 bytes, dcs header is kept at first loop,
1687 * after that dcs header lost during shift into registers
1689 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size);
1697 if (rlen <= data_byte) {
1698 diff = data_byte - rlen;
1706 dlen -= 2; /* 2 crc */
1708 buf += dlen; /* next start position */
1709 data_byte = 14; /* NOT first read */
1710 if (rlen < data_byte)
1713 pkt_size += data_byte;
1714 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff);
1719 * For single Long read, if the requested rlen < 10,
1720 * we need to shift the start position of rx
1721 * data buffer to skip the bytes which are not
1724 if (pkt_size < 10 && !short_response)
1725 buf = msm_host->rx_buf + (10 - rlen);
1727 buf = msm_host->rx_buf;
1731 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1732 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__);
1735 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
1736 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1737 ret = dsi_short_read1_resp(buf, msg);
1739 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
1740 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1741 ret = dsi_short_read2_resp(buf, msg);
1743 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
1744 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
1745 ret = dsi_long_read_resp(buf, msg);
1748 pr_warn("%s:Invalid response cmd\n", __func__);
1755 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 iova, u32 len)
1757 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1759 dsi_write(msm_host, REG_DSI_DMA_BASE, iova);
1760 dsi_write(msm_host, REG_DSI_DMA_LEN, len);
1761 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1);
1763 /* Make sure trigger happens */
1767 int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
1768 struct msm_dsi_pll *src_pll)
1770 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1771 struct clk *byte_clk_provider, *pixel_clk_provider;
1774 ret = msm_dsi_pll_get_clk_provider(src_pll,
1775 &byte_clk_provider, &pixel_clk_provider);
1777 pr_info("%s: can't get provider from pll, don't set parent\n",
1782 ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider);
1784 pr_err("%s: can't set parent to byte_clk_src. ret=%d\n",
1789 ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider);
1791 pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n",
1800 int msm_dsi_host_enable(struct mipi_dsi_host *host)
1802 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1804 dsi_op_mode_config(msm_host,
1805 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true);
1807 /* TODO: clock should be turned off for command mode,
1808 * and only turned on before MDP START.
1809 * This part of code should be enabled once mdp driver support it.
1811 /* if (msm_panel->mode == MSM_DSI_CMD_MODE)
1812 dsi_clk_ctrl(msm_host, 0); */
1817 int msm_dsi_host_disable(struct mipi_dsi_host *host)
1819 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1821 dsi_op_mode_config(msm_host,
1822 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false);
1824 /* Since we have disabled INTF, the video engine won't stop so that
1825 * the cmd engine will be blocked.
1826 * Reset to disable video engine so that we can send off cmd.
1828 dsi_sw_reset(msm_host);
1833 int msm_dsi_host_power_on(struct mipi_dsi_host *host)
1835 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1836 u32 clk_pre = 0, clk_post = 0;
1839 mutex_lock(&msm_host->dev_mutex);
1840 if (msm_host->power_on) {
1841 DBG("dsi host already on");
1845 ret = dsi_calc_clk_rate(msm_host);
1847 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret);
1851 ret = dsi_host_regulator_enable(msm_host);
1853 pr_err("%s:Failed to enable vregs.ret=%d\n",
1858 ret = dsi_bus_clk_enable(msm_host);
1860 pr_err("%s: failed to enable bus clocks, %d\n", __func__, ret);
1861 goto fail_disable_reg;
1864 dsi_phy_sw_reset(msm_host);
1865 ret = msm_dsi_manager_phy_enable(msm_host->id,
1866 msm_host->byte_clk_rate * 8,
1867 clk_get_rate(msm_host->esc_clk),
1868 &clk_pre, &clk_post);
1869 dsi_bus_clk_disable(msm_host);
1871 pr_err("%s: failed to enable phy, %d\n", __func__, ret);
1872 goto fail_disable_reg;
1875 ret = dsi_clk_ctrl(msm_host, 1);
1877 pr_err("%s: failed to enable clocks. ret=%d\n", __func__, ret);
1878 goto fail_disable_reg;
1881 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev);
1883 pr_err("%s: failed to set pinctrl default state, %d\n",
1885 goto fail_disable_clk;
1888 dsi_timing_setup(msm_host);
1889 dsi_sw_reset(msm_host);
1890 dsi_ctrl_config(msm_host, true, clk_pre, clk_post);
1892 if (msm_host->disp_en_gpio)
1893 gpiod_set_value(msm_host->disp_en_gpio, 1);
1895 msm_host->power_on = true;
1896 mutex_unlock(&msm_host->dev_mutex);
1901 dsi_clk_ctrl(msm_host, 0);
1903 dsi_host_regulator_disable(msm_host);
1905 mutex_unlock(&msm_host->dev_mutex);
1909 int msm_dsi_host_power_off(struct mipi_dsi_host *host)
1911 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1913 mutex_lock(&msm_host->dev_mutex);
1914 if (!msm_host->power_on) {
1915 DBG("dsi host already off");
1919 dsi_ctrl_config(msm_host, false, 0, 0);
1921 if (msm_host->disp_en_gpio)
1922 gpiod_set_value(msm_host->disp_en_gpio, 0);
1924 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev);
1926 msm_dsi_manager_phy_disable(msm_host->id);
1928 dsi_clk_ctrl(msm_host, 0);
1930 dsi_host_regulator_disable(msm_host);
1934 msm_host->power_on = false;
1937 mutex_unlock(&msm_host->dev_mutex);
1941 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
1942 struct drm_display_mode *mode)
1944 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1946 if (msm_host->mode) {
1947 drm_mode_destroy(msm_host->dev, msm_host->mode);
1948 msm_host->mode = NULL;
1951 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode);
1952 if (IS_ERR(msm_host->mode)) {
1953 pr_err("%s: cannot duplicate mode\n", __func__);
1954 return PTR_ERR(msm_host->mode);
1960 struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host,
1961 unsigned long *panel_flags)
1963 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1964 struct drm_panel *panel;
1966 panel = of_drm_find_panel(msm_host->device_node);
1968 *panel_flags = msm_host->mode_flags;
1973 struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host)
1975 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1977 return of_drm_find_bridge(msm_host->device_node);