1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
6 #include <linux/delay.h>
7 #include <drm/drm_print.h>
18 DP_AUX_ERR_NACK_DEFER,
22 struct dp_aux_private {
24 struct dp_catalog *catalog;
27 struct completion comp;
29 enum msm_dp_aux_err aux_error_num;
41 struct drm_dp_aux dp_aux;
44 #define MAX_AUX_RETRIES 5
46 static ssize_t dp_aux_write(struct dp_aux_private *aux,
47 struct drm_dp_aux_msg *msg)
52 u8 *msgdata = msg->buffer;
53 int const AUX_CMD_FIFO_LEN = 128;
62 * cmd fifo only has depth of 144 bytes
63 * limit buf length to 128 bytes here
65 if (len > AUX_CMD_FIFO_LEN - 4) {
66 DRM_ERROR("buf size greater than allowed size of 128 bytes\n");
70 /* Pack cmd and write to HW */
71 data[0] = (msg->address >> 16) & 0xf; /* addr[19:16] */
73 data[0] |= BIT(4); /* R/W */
75 data[1] = msg->address >> 8; /* addr[15:8] */
76 data[2] = msg->address; /* addr[7:0] */
77 data[3] = msg->size - 1; /* len[7:0] */
79 for (i = 0; i < len + 4; i++) {
80 reg = (i < 4) ? data[i] : msgdata[i - 4];
81 reg <<= DP_AUX_DATA_OFFSET;
82 reg &= DP_AUX_DATA_MASK;
83 reg |= DP_AUX_DATA_WRITE;
84 /* index = 0, write */
86 reg |= DP_AUX_DATA_INDEX_WRITE;
87 aux->catalog->aux_data = reg;
88 dp_catalog_aux_write_data(aux->catalog);
91 dp_catalog_aux_clear_trans(aux->catalog, false);
92 dp_catalog_aux_clear_hw_interrupts(aux->catalog);
94 reg = 0; /* Transaction number == 1 */
95 if (!aux->native) { /* i2c */
96 reg |= DP_AUX_TRANS_CTRL_I2C;
98 if (aux->no_send_addr)
99 reg |= DP_AUX_TRANS_CTRL_NO_SEND_ADDR;
101 if (aux->no_send_stop)
102 reg |= DP_AUX_TRANS_CTRL_NO_SEND_STOP;
105 reg |= DP_AUX_TRANS_CTRL_GO;
106 aux->catalog->aux_data = reg;
107 dp_catalog_aux_write_trans(aux->catalog);
112 static ssize_t dp_aux_cmd_fifo_tx(struct dp_aux_private *aux,
113 struct drm_dp_aux_msg *msg)
116 unsigned long time_left;
118 reinit_completion(&aux->comp);
120 ret = dp_aux_write(aux, msg);
124 time_left = wait_for_completion_timeout(&aux->comp,
125 msecs_to_jiffies(250));
132 static ssize_t dp_aux_cmd_fifo_rx(struct dp_aux_private *aux,
133 struct drm_dp_aux_msg *msg)
140 dp_catalog_aux_clear_trans(aux->catalog, true);
142 data = DP_AUX_DATA_INDEX_WRITE; /* INDEX_WRITE */
143 data |= DP_AUX_DATA_READ; /* read */
145 aux->catalog->aux_data = data;
146 dp_catalog_aux_write_data(aux->catalog);
150 /* discard first byte */
151 data = dp_catalog_aux_read_data(aux->catalog);
153 for (i = 0; i < len; i++) {
154 data = dp_catalog_aux_read_data(aux->catalog);
155 *dp++ = (u8)((data >> DP_AUX_DATA_OFFSET) & 0xff);
157 actual_i = (data >> DP_AUX_DATA_INDEX_OFFSET) & 0xFF;
165 static void dp_aux_native_handler(struct dp_aux_private *aux, u32 isr)
167 if (isr & DP_INTR_AUX_I2C_DONE)
168 aux->aux_error_num = DP_AUX_ERR_NONE;
169 else if (isr & DP_INTR_WRONG_ADDR)
170 aux->aux_error_num = DP_AUX_ERR_ADDR;
171 else if (isr & DP_INTR_TIMEOUT)
172 aux->aux_error_num = DP_AUX_ERR_TOUT;
173 if (isr & DP_INTR_NACK_DEFER)
174 aux->aux_error_num = DP_AUX_ERR_NACK;
175 if (isr & DP_INTR_AUX_ERROR) {
176 aux->aux_error_num = DP_AUX_ERR_PHY;
177 dp_catalog_aux_clear_hw_interrupts(aux->catalog);
181 static void dp_aux_i2c_handler(struct dp_aux_private *aux, u32 isr)
183 if (isr & DP_INTR_AUX_I2C_DONE) {
184 if (isr & (DP_INTR_I2C_NACK | DP_INTR_I2C_DEFER))
185 aux->aux_error_num = DP_AUX_ERR_NACK;
187 aux->aux_error_num = DP_AUX_ERR_NONE;
189 if (isr & DP_INTR_WRONG_ADDR)
190 aux->aux_error_num = DP_AUX_ERR_ADDR;
191 else if (isr & DP_INTR_TIMEOUT)
192 aux->aux_error_num = DP_AUX_ERR_TOUT;
193 if (isr & DP_INTR_NACK_DEFER)
194 aux->aux_error_num = DP_AUX_ERR_NACK_DEFER;
195 if (isr & DP_INTR_I2C_NACK)
196 aux->aux_error_num = DP_AUX_ERR_NACK;
197 if (isr & DP_INTR_I2C_DEFER)
198 aux->aux_error_num = DP_AUX_ERR_DEFER;
199 if (isr & DP_INTR_AUX_ERROR) {
200 aux->aux_error_num = DP_AUX_ERR_PHY;
201 dp_catalog_aux_clear_hw_interrupts(aux->catalog);
206 static void dp_aux_update_offset_and_segment(struct dp_aux_private *aux,
207 struct drm_dp_aux_msg *input_msg)
209 u32 edid_address = 0x50;
210 u32 segment_address = 0x30;
211 bool i2c_read = input_msg->request &
212 (DP_AUX_I2C_READ & DP_AUX_NATIVE_READ);
215 if (aux->native || i2c_read || ((input_msg->address != edid_address) &&
216 (input_msg->address != segment_address)))
220 data = input_msg->buffer;
221 if (input_msg->address == segment_address)
222 aux->segment = *data;
228 * dp_aux_transfer_helper() - helper function for EDID read transactions
230 * @aux: DP AUX private structure
231 * @input_msg: input message from DRM upstream APIs
232 * @send_seg: send the segment to sink
236 * This helper function is used to fix EDID reads for non-compliant
237 * sinks that do not handle the i2c middle-of-transaction flag correctly.
239 static void dp_aux_transfer_helper(struct dp_aux_private *aux,
240 struct drm_dp_aux_msg *input_msg,
243 struct drm_dp_aux_msg helper_msg;
244 u32 message_size = 0x10;
245 u32 segment_address = 0x30;
246 u32 const edid_block_length = 0x80;
247 bool i2c_mot = input_msg->request & DP_AUX_I2C_MOT;
248 bool i2c_read = input_msg->request &
249 (DP_AUX_I2C_READ & DP_AUX_NATIVE_READ);
251 if (!i2c_mot || !i2c_read || (input_msg->size == 0))
255 * Sending the segment value and EDID offset will be performed
256 * from the DRM upstream EDID driver for each block. Avoid
257 * duplicate AUX transactions related to this while reading the
258 * first 16 bytes of each block.
260 if (!(aux->offset % edid_block_length) || !send_seg)
264 aux->cmd_busy = true;
265 aux->no_send_addr = true;
266 aux->no_send_stop = true;
269 * Send the segment address for every i2c read in which the
270 * middle-of-tranaction flag is set. This is required to support EDID
271 * reads of more than 2 blocks as the segment address is reset to 0
272 * since we are overriding the middle-of-transaction flag for read
277 memset(&helper_msg, 0, sizeof(helper_msg));
278 helper_msg.address = segment_address;
279 helper_msg.buffer = &aux->segment;
281 dp_aux_cmd_fifo_tx(aux, &helper_msg);
285 * Send the offset address for every i2c read in which the
286 * middle-of-transaction flag is set. This will ensure that the sink
287 * will update its read pointer and return the correct portion of the
288 * EDID buffer in the subsequent i2c read trasntion triggered in the
289 * native AUX transfer function.
291 memset(&helper_msg, 0, sizeof(helper_msg));
292 helper_msg.address = input_msg->address;
293 helper_msg.buffer = &aux->offset;
295 dp_aux_cmd_fifo_tx(aux, &helper_msg);
298 aux->offset += message_size;
299 if (aux->offset == 0x80 || aux->offset == 0x100)
300 aux->segment = 0x0; /* reset segment at end of block */
304 * This function does the real job to process an AUX transaction.
305 * It will call aux_reset() function to reset the AUX channel,
306 * if the waiting is timeout.
308 static ssize_t dp_aux_transfer(struct drm_dp_aux *dp_aux,
309 struct drm_dp_aux_msg *msg)
312 int const aux_cmd_native_max = 16;
313 int const aux_cmd_i2c_max = 128;
314 struct dp_aux_private *aux;
316 aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
318 aux->native = msg->request & (DP_AUX_NATIVE_WRITE & DP_AUX_NATIVE_READ);
320 /* Ignore address only message */
321 if (msg->size == 0 || !msg->buffer) {
322 msg->reply = aux->native ?
323 DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK;
327 /* msg sanity check */
328 if ((aux->native && msg->size > aux_cmd_native_max) ||
329 msg->size > aux_cmd_i2c_max) {
330 DRM_ERROR("%s: invalid msg: size(%zu), request(%x)\n",
331 __func__, msg->size, msg->request);
335 mutex_lock(&aux->mutex);
342 * For eDP it's important to give a reasonably long wait here for HPD
343 * to be asserted. This is because the panel driver may have _just_
344 * turned on the panel and then tried to do an AUX transfer. The panel
345 * driver has no way of knowing when the panel is ready, so it's up
346 * to us to wait. For DP we never get into this situation so let's
347 * avoid ever doing the extra long wait for DP.
350 ret = dp_catalog_aux_wait_for_hpd_connect_state(aux->catalog);
352 DRM_DEBUG_DP("Panel not ready for aux transactions\n");
357 dp_aux_update_offset_and_segment(aux, msg);
358 dp_aux_transfer_helper(aux, msg, true);
360 aux->read = msg->request & (DP_AUX_I2C_READ & DP_AUX_NATIVE_READ);
361 aux->cmd_busy = true;
364 aux->no_send_addr = true;
365 aux->no_send_stop = false;
367 aux->no_send_addr = true;
368 aux->no_send_stop = true;
371 ret = dp_aux_cmd_fifo_tx(aux, msg);
375 if (!(aux->retry_cnt % MAX_AUX_RETRIES))
376 dp_catalog_aux_update_cfg(aux->catalog);
378 /* reset aux if link is in connected state */
379 if (dp_catalog_link_is_connected(aux->catalog))
380 dp_catalog_aux_reset(aux->catalog);
383 switch (aux->aux_error_num) {
384 case DP_AUX_ERR_NONE:
386 ret = dp_aux_cmd_fifo_rx(aux, msg);
387 msg->reply = aux->native ? DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK;
389 case DP_AUX_ERR_DEFER:
390 msg->reply = aux->native ? DP_AUX_NATIVE_REPLY_DEFER : DP_AUX_I2C_REPLY_DEFER;
393 case DP_AUX_ERR_ADDR:
394 case DP_AUX_ERR_NACK:
395 case DP_AUX_ERR_NACK_DEFER:
396 msg->reply = aux->native ? DP_AUX_NATIVE_REPLY_NACK : DP_AUX_I2C_REPLY_NACK;
398 case DP_AUX_ERR_TOUT:
404 aux->cmd_busy = false;
407 mutex_unlock(&aux->mutex);
412 void dp_aux_isr(struct drm_dp_aux *dp_aux)
415 struct dp_aux_private *aux;
418 DRM_ERROR("invalid input\n");
422 aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
424 isr = dp_catalog_aux_get_irq(aux->catalog);
430 dp_aux_native_handler(aux, isr);
432 dp_aux_i2c_handler(aux, isr);
434 complete(&aux->comp);
437 void dp_aux_reconfig(struct drm_dp_aux *dp_aux)
439 struct dp_aux_private *aux;
441 aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
443 dp_catalog_aux_update_cfg(aux->catalog);
444 dp_catalog_aux_reset(aux->catalog);
447 void dp_aux_init(struct drm_dp_aux *dp_aux)
449 struct dp_aux_private *aux;
452 DRM_ERROR("invalid input\n");
456 aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
458 mutex_lock(&aux->mutex);
460 dp_catalog_aux_enable(aux->catalog, true);
464 mutex_unlock(&aux->mutex);
467 void dp_aux_deinit(struct drm_dp_aux *dp_aux)
469 struct dp_aux_private *aux;
471 aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
473 mutex_lock(&aux->mutex);
475 aux->initted = false;
476 dp_catalog_aux_enable(aux->catalog, false);
478 mutex_unlock(&aux->mutex);
481 int dp_aux_register(struct drm_dp_aux *dp_aux)
483 struct dp_aux_private *aux;
487 DRM_ERROR("invalid input\n");
491 aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
493 aux->dp_aux.name = "dpu_dp_aux";
494 aux->dp_aux.dev = aux->dev;
495 aux->dp_aux.transfer = dp_aux_transfer;
496 ret = drm_dp_aux_register(&aux->dp_aux);
498 DRM_ERROR("%s: failed to register drm aux: %d\n", __func__,
506 void dp_aux_unregister(struct drm_dp_aux *dp_aux)
508 drm_dp_aux_unregister(dp_aux);
511 struct drm_dp_aux *dp_aux_get(struct device *dev, struct dp_catalog *catalog,
514 struct dp_aux_private *aux;
517 DRM_ERROR("invalid input\n");
518 return ERR_PTR(-ENODEV);
521 aux = devm_kzalloc(dev, sizeof(*aux), GFP_KERNEL);
523 return ERR_PTR(-ENOMEM);
525 init_completion(&aux->comp);
526 aux->cmd_busy = false;
527 aux->is_edp = is_edp;
528 mutex_init(&aux->mutex);
531 aux->catalog = catalog;
537 void dp_aux_put(struct drm_dp_aux *dp_aux)
539 struct dp_aux_private *aux;
544 aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
546 mutex_destroy(&aux->mutex);
548 devm_kfree(aux->dev, aux);