2 * Copyright (C) 2014-2015 The Linux Foundation. All rights reserved.
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <drm/drm_print.h>
23 struct drm_plane base;
28 #define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
30 static int mdp5_plane_mode_set(struct drm_plane *plane,
31 struct drm_crtc *crtc, struct drm_framebuffer *fb,
32 struct drm_rect *src, struct drm_rect *dest);
34 static struct mdp5_kms *get_kms(struct drm_plane *plane)
36 struct msm_drm_private *priv = plane->dev->dev_private;
37 return to_mdp5_kms(to_mdp_kms(priv->kms));
40 static bool plane_enabled(struct drm_plane_state *state)
42 return state->visible;
45 static void mdp5_plane_destroy(struct drm_plane *plane)
47 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
49 drm_plane_helper_disable(plane, NULL);
50 drm_plane_cleanup(plane);
55 static void mdp5_plane_install_rotation_property(struct drm_device *dev,
56 struct drm_plane *plane)
58 drm_plane_create_rotation_property(plane,
66 /* helper to install properties which are common to planes and crtcs */
67 static void mdp5_plane_install_properties(struct drm_plane *plane,
68 struct drm_mode_object *obj)
70 struct drm_device *dev = plane->dev;
71 struct msm_drm_private *dev_priv = dev->dev_private;
72 struct drm_property *prop;
74 #define INSTALL_PROPERTY(name, NAME, init_val, fnc, ...) do { \
75 prop = dev_priv->plane_property[PLANE_PROP_##NAME]; \
77 prop = drm_property_##fnc(dev, 0, #name, \
81 "Create property %s failed\n", \
85 dev_priv->plane_property[PLANE_PROP_##NAME] = prop; \
87 drm_object_attach_property(&plane->base, prop, init_val); \
90 #define INSTALL_RANGE_PROPERTY(name, NAME, min, max, init_val) \
91 INSTALL_PROPERTY(name, NAME, init_val, \
92 create_range, min, max)
94 #define INSTALL_ENUM_PROPERTY(name, NAME, init_val) \
95 INSTALL_PROPERTY(name, NAME, init_val, \
96 create_enum, name##_prop_enum_list, \
97 ARRAY_SIZE(name##_prop_enum_list))
99 INSTALL_RANGE_PROPERTY(zpos, ZPOS, 1, 255, 1);
101 mdp5_plane_install_rotation_property(dev, plane);
103 #undef INSTALL_RANGE_PROPERTY
104 #undef INSTALL_ENUM_PROPERTY
105 #undef INSTALL_PROPERTY
108 static int mdp5_plane_atomic_set_property(struct drm_plane *plane,
109 struct drm_plane_state *state, struct drm_property *property,
112 struct drm_device *dev = plane->dev;
113 struct mdp5_plane_state *pstate;
114 struct msm_drm_private *dev_priv = dev->dev_private;
117 pstate = to_mdp5_plane_state(state);
119 #define SET_PROPERTY(name, NAME, type) do { \
120 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
121 pstate->name = (type)val; \
122 DBG("Set property %s %d", #name, (type)val); \
127 SET_PROPERTY(zpos, ZPOS, uint8_t);
129 dev_err(dev->dev, "Invalid property\n");
136 static int mdp5_plane_atomic_get_property(struct drm_plane *plane,
137 const struct drm_plane_state *state,
138 struct drm_property *property, uint64_t *val)
140 struct drm_device *dev = plane->dev;
141 struct mdp5_plane_state *pstate;
142 struct msm_drm_private *dev_priv = dev->dev_private;
145 pstate = to_mdp5_plane_state(state);
147 #define GET_PROPERTY(name, NAME, type) do { \
148 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
149 *val = pstate->name; \
150 DBG("Get property %s %lld", #name, *val); \
155 GET_PROPERTY(zpos, ZPOS, uint8_t);
157 dev_err(dev->dev, "Invalid property\n");
165 mdp5_plane_atomic_print_state(struct drm_printer *p,
166 const struct drm_plane_state *state)
168 struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
169 struct mdp5_kms *mdp5_kms = get_kms(state->plane);
171 drm_printf(p, "\thwpipe=%s\n", pstate->hwpipe ?
172 pstate->hwpipe->name : "(null)");
173 if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT)
174 drm_printf(p, "\tright-hwpipe=%s\n",
175 pstate->r_hwpipe ? pstate->r_hwpipe->name :
177 drm_printf(p, "\tpremultiplied=%u\n", pstate->premultiplied);
178 drm_printf(p, "\tzpos=%u\n", pstate->zpos);
179 drm_printf(p, "\talpha=%u\n", pstate->alpha);
180 drm_printf(p, "\tstage=%s\n", stage2name(pstate->stage));
183 static void mdp5_plane_reset(struct drm_plane *plane)
185 struct mdp5_plane_state *mdp5_state;
187 if (plane->state && plane->state->fb)
188 drm_framebuffer_unreference(plane->state->fb);
190 kfree(to_mdp5_plane_state(plane->state));
191 mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL);
193 /* assign default blend parameters */
194 mdp5_state->alpha = 255;
195 mdp5_state->premultiplied = 0;
197 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
198 mdp5_state->zpos = STAGE_BASE;
200 mdp5_state->zpos = STAGE0 + drm_plane_index(plane);
202 mdp5_state->base.plane = plane;
204 plane->state = &mdp5_state->base;
207 static struct drm_plane_state *
208 mdp5_plane_duplicate_state(struct drm_plane *plane)
210 struct mdp5_plane_state *mdp5_state;
212 if (WARN_ON(!plane->state))
215 mdp5_state = kmemdup(to_mdp5_plane_state(plane->state),
216 sizeof(*mdp5_state), GFP_KERNEL);
220 __drm_atomic_helper_plane_duplicate_state(plane, &mdp5_state->base);
222 return &mdp5_state->base;
225 static void mdp5_plane_destroy_state(struct drm_plane *plane,
226 struct drm_plane_state *state)
228 struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
231 drm_framebuffer_unreference(state->fb);
236 static const struct drm_plane_funcs mdp5_plane_funcs = {
237 .update_plane = drm_atomic_helper_update_plane,
238 .disable_plane = drm_atomic_helper_disable_plane,
239 .destroy = mdp5_plane_destroy,
240 .atomic_set_property = mdp5_plane_atomic_set_property,
241 .atomic_get_property = mdp5_plane_atomic_get_property,
242 .reset = mdp5_plane_reset,
243 .atomic_duplicate_state = mdp5_plane_duplicate_state,
244 .atomic_destroy_state = mdp5_plane_destroy_state,
245 .atomic_print_state = mdp5_plane_atomic_print_state,
248 static void mdp5_plane_cleanup_fb(struct drm_plane *plane,
249 struct drm_plane_state *old_state)
251 struct mdp5_kms *mdp5_kms = get_kms(plane);
252 struct msm_kms *kms = &mdp5_kms->base.base;
253 struct drm_framebuffer *fb = old_state->fb;
258 DBG("%s: cleanup: FB[%u]", plane->name, fb->base.id);
259 msm_framebuffer_cleanup(fb, kms->aspace);
262 static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state,
263 struct drm_plane_state *state)
265 struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state);
266 struct drm_plane *plane = state->plane;
267 struct drm_plane_state *old_state = plane->state;
268 struct mdp5_cfg *config = mdp5_cfg_get_config(get_kms(plane)->cfg);
269 bool new_hwpipe = false;
270 bool need_right_hwpipe = false;
271 uint32_t max_width, max_height;
272 bool out_of_bounds = false;
274 int min_scale, max_scale;
277 DBG("%s: check (%d -> %d)", plane->name,
278 plane_enabled(old_state), plane_enabled(state));
280 max_width = config->hw->lm.max_width << 16;
281 max_height = config->hw->lm.max_height << 16;
283 /* Make sure source dimensions are within bounds. */
284 if (state->src_h > max_height)
285 out_of_bounds = true;
287 if (state->src_w > max_width) {
288 /* If source split is supported, we can go up to 2x
289 * the max LM width, but we'd need to stage another
290 * hwpipe to the right LM. So, the drm_plane would
291 * consist of 2 hwpipes.
293 if (config->hw->mdp.caps & MDP_CAP_SRC_SPLIT &&
294 (state->src_w <= 2 * max_width))
295 need_right_hwpipe = true;
297 out_of_bounds = true;
301 struct drm_rect src = drm_plane_state_src(state);
302 DBG("Invalid source size "DRM_RECT_FP_FMT,
303 DRM_RECT_FP_ARG(&src));
307 min_scale = FRAC_16_16(1, 8);
308 max_scale = FRAC_16_16(8, 1);
310 ret = drm_atomic_helper_check_plane_state(state, crtc_state,
311 min_scale, max_scale,
316 if (plane_enabled(state)) {
317 unsigned int rotation;
318 const struct mdp_format *format;
319 struct mdp5_kms *mdp5_kms = get_kms(plane);
322 format = to_mdp_format(msm_framebuffer_format(state->fb));
323 if (MDP_FORMAT_IS_YUV(format))
324 caps |= MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC;
326 if (((state->src_w >> 16) != state->crtc_w) ||
327 ((state->src_h >> 16) != state->crtc_h))
328 caps |= MDP_PIPE_CAP_SCALE;
330 rotation = drm_rotation_simplify(state->rotation,
335 if (rotation & DRM_MODE_REFLECT_X)
336 caps |= MDP_PIPE_CAP_HFLIP;
338 if (rotation & DRM_MODE_REFLECT_Y)
339 caps |= MDP_PIPE_CAP_VFLIP;
341 if (plane->type == DRM_PLANE_TYPE_CURSOR)
342 caps |= MDP_PIPE_CAP_CURSOR;
344 /* (re)allocate hw pipe if we don't have one or caps-mismatch: */
345 if (!mdp5_state->hwpipe || (caps & ~mdp5_state->hwpipe->caps))
349 * (re)allocte hw pipe if we're either requesting for 2 hw pipes
350 * or we're switching from 2 hw pipes to 1 hw pipe because the
351 * new src_w can be supported by 1 hw pipe itself.
353 if ((need_right_hwpipe && !mdp5_state->r_hwpipe) ||
354 (!need_right_hwpipe && mdp5_state->r_hwpipe))
358 const struct mdp_format *format =
359 to_mdp_format(msm_framebuffer_format(state->fb));
361 blkcfg = mdp5_smp_calculate(mdp5_kms->smp, format,
362 state->src_w >> 16, false);
364 if (mdp5_state->hwpipe && (mdp5_state->hwpipe->blkcfg != blkcfg))
368 /* (re)assign hwpipe if needed, otherwise keep old one: */
370 /* TODO maybe we want to re-assign hwpipe sometimes
371 * in cases when we no-longer need some caps to make
372 * it available for other planes?
374 struct mdp5_hw_pipe *old_hwpipe = mdp5_state->hwpipe;
375 struct mdp5_hw_pipe *old_right_hwpipe =
376 mdp5_state->r_hwpipe;
377 struct mdp5_hw_pipe *new_hwpipe = NULL;
378 struct mdp5_hw_pipe *new_right_hwpipe = NULL;
380 ret = mdp5_pipe_assign(state->state, plane, caps,
383 &new_right_hwpipe : NULL);
385 DBG("%s: failed to assign hwpipe(s)!",
390 mdp5_state->hwpipe = new_hwpipe;
391 if (need_right_hwpipe)
392 mdp5_state->r_hwpipe = new_right_hwpipe;
395 * set it to NULL so that the driver knows we
396 * don't have a right hwpipe when committing a
399 mdp5_state->r_hwpipe = NULL;
402 mdp5_pipe_release(state->state, old_hwpipe);
403 mdp5_pipe_release(state->state, old_right_hwpipe);
406 mdp5_pipe_release(state->state, mdp5_state->hwpipe);
407 mdp5_pipe_release(state->state, mdp5_state->r_hwpipe);
408 mdp5_state->hwpipe = mdp5_state->r_hwpipe = NULL;
414 static int mdp5_plane_atomic_check(struct drm_plane *plane,
415 struct drm_plane_state *state)
417 struct drm_crtc *crtc;
418 struct drm_crtc_state *crtc_state;
420 crtc = state->crtc ? state->crtc : plane->state->crtc;
424 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
425 if (WARN_ON(!crtc_state))
428 return mdp5_plane_atomic_check_with_state(crtc_state, state);
431 static void mdp5_plane_atomic_update(struct drm_plane *plane,
432 struct drm_plane_state *old_state)
434 struct drm_plane_state *state = plane->state;
436 DBG("%s: update", plane->name);
438 if (plane_enabled(state)) {
441 ret = mdp5_plane_mode_set(plane,
442 state->crtc, state->fb,
443 &state->src, &state->dst);
444 /* atomic_check should have ensured that this doesn't fail */
449 static int mdp5_plane_atomic_async_check(struct drm_plane *plane,
450 struct drm_plane_state *state)
452 struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state);
453 struct drm_crtc_state *crtc_state;
454 int min_scale, max_scale;
457 crtc_state = drm_atomic_get_existing_crtc_state(state->state,
459 if (WARN_ON(!crtc_state))
462 if (!crtc_state->active)
465 mdp5_state = to_mdp5_plane_state(state);
467 /* don't use fast path if we don't have a hwpipe allocated yet */
468 if (!mdp5_state->hwpipe)
471 /* only allow changing of position(crtc x/y or src x/y) in fast path */
472 if (plane->state->crtc != state->crtc ||
473 plane->state->src_w != state->src_w ||
474 plane->state->src_h != state->src_h ||
475 plane->state->crtc_w != state->crtc_w ||
476 plane->state->crtc_h != state->crtc_h ||
478 plane->state->fb != state->fb)
481 min_scale = FRAC_16_16(1, 8);
482 max_scale = FRAC_16_16(8, 1);
484 ret = drm_atomic_helper_check_plane_state(state, crtc_state,
485 min_scale, max_scale,
491 * if the visibility of the plane changes (i.e, if the cursor is
492 * clipped out completely, we can't take the async path because
493 * we need to stage/unstage the plane from the Layer Mixer(s). We
494 * also assign/unassign the hwpipe(s) tied to the plane. We avoid
495 * taking the fast path for both these reasons.
497 if (state->visible != plane->state->visible)
503 static void mdp5_plane_atomic_async_update(struct drm_plane *plane,
504 struct drm_plane_state *new_state)
506 struct drm_framebuffer *old_fb = plane->state->fb;
508 plane->state->src_x = new_state->src_x;
509 plane->state->src_y = new_state->src_y;
510 plane->state->crtc_x = new_state->crtc_x;
511 plane->state->crtc_y = new_state->crtc_y;
513 if (plane_enabled(new_state)) {
514 struct mdp5_ctl *ctl;
515 struct mdp5_pipeline *pipeline =
516 mdp5_crtc_get_pipeline(new_state->crtc);
519 ret = mdp5_plane_mode_set(plane, new_state->crtc, new_state->fb,
520 &new_state->src, &new_state->dst);
523 ctl = mdp5_crtc_get_ctl(new_state->crtc);
525 mdp5_ctl_commit(ctl, pipeline, mdp5_plane_get_flush(plane), true);
528 *to_mdp5_plane_state(plane->state) =
529 *to_mdp5_plane_state(new_state);
531 new_state->fb = old_fb;
534 static const struct drm_plane_helper_funcs mdp5_plane_helper_funcs = {
535 .prepare_fb = msm_atomic_prepare_fb,
536 .cleanup_fb = mdp5_plane_cleanup_fb,
537 .atomic_check = mdp5_plane_atomic_check,
538 .atomic_update = mdp5_plane_atomic_update,
539 .atomic_async_check = mdp5_plane_atomic_async_check,
540 .atomic_async_update = mdp5_plane_atomic_async_update,
543 static void set_scanout_locked(struct mdp5_kms *mdp5_kms,
545 struct drm_framebuffer *fb)
547 struct msm_kms *kms = &mdp5_kms->base.base;
549 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe),
550 MDP5_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) |
551 MDP5_PIPE_SRC_STRIDE_A_P1(fb->pitches[1]));
553 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe),
554 MDP5_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) |
555 MDP5_PIPE_SRC_STRIDE_B_P3(fb->pitches[3]));
557 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe),
558 msm_framebuffer_iova(fb, kms->aspace, 0));
559 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe),
560 msm_framebuffer_iova(fb, kms->aspace, 1));
561 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe),
562 msm_framebuffer_iova(fb, kms->aspace, 2));
563 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe),
564 msm_framebuffer_iova(fb, kms->aspace, 3));
567 /* Note: mdp5_plane->pipe_lock must be locked */
568 static void csc_disable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe)
570 uint32_t value = mdp5_read(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe)) &
571 ~MDP5_PIPE_OP_MODE_CSC_1_EN;
573 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), value);
576 /* Note: mdp5_plane->pipe_lock must be locked */
577 static void csc_enable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
580 uint32_t i, mode = 0; /* RGB, no CSC */
586 if ((csc->type == CSC_YUV2RGB) || (CSC_YUV2YUV == csc->type))
587 mode |= MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(DATA_FORMAT_YUV);
588 if ((csc->type == CSC_RGB2YUV) || (CSC_YUV2YUV == csc->type))
589 mode |= MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(DATA_FORMAT_YUV);
590 mode |= MDP5_PIPE_OP_MODE_CSC_1_EN;
591 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), mode);
593 matrix = csc->matrix;
594 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe),
595 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(matrix[0]) |
596 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(matrix[1]));
597 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe),
598 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(matrix[2]) |
599 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(matrix[3]));
600 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(pipe),
601 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(matrix[4]) |
602 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(matrix[5]));
603 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(pipe),
604 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(matrix[6]) |
605 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(matrix[7]));
606 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(pipe),
607 MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(matrix[8]));
609 for (i = 0; i < ARRAY_SIZE(csc->pre_bias); i++) {
610 uint32_t *pre_clamp = csc->pre_clamp;
611 uint32_t *post_clamp = csc->post_clamp;
613 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_CLAMP(pipe, i),
614 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(pre_clamp[2*i+1]) |
615 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(pre_clamp[2*i]));
617 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_CLAMP(pipe, i),
618 MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(post_clamp[2*i+1]) |
619 MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(post_clamp[2*i]));
621 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_BIAS(pipe, i),
622 MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(csc->pre_bias[i]));
624 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_BIAS(pipe, i),
625 MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(csc->post_bias[i]));
629 #define PHASE_STEP_SHIFT 21
630 #define DOWN_SCALE_RATIO_MAX 32 /* 2^(26-21) */
632 static int calc_phase_step(uint32_t src, uint32_t dst, uint32_t *out_phase)
636 if (src == 0 || dst == 0)
640 * PHASE_STEP_X/Y is coded on 26 bits (25:0),
641 * where 2^21 represents the unity "1" in fixed-point hardware design.
642 * This leaves 5 bits for the integer part (downscale case):
643 * -> maximum downscale ratio = 0b1_1111 = 31
645 if (src > (dst * DOWN_SCALE_RATIO_MAX))
648 unit = 1 << PHASE_STEP_SHIFT;
649 *out_phase = mult_frac(unit, src, dst);
654 static int calc_scalex_steps(struct drm_plane *plane,
655 uint32_t pixel_format, uint32_t src, uint32_t dest,
656 uint32_t phasex_steps[COMP_MAX])
658 struct mdp5_kms *mdp5_kms = get_kms(plane);
659 struct device *dev = mdp5_kms->dev->dev;
660 uint32_t phasex_step;
664 ret = calc_phase_step(src, dest, &phasex_step);
666 dev_err(dev, "X scaling (%d->%d) failed: %d\n", src, dest, ret);
670 hsub = drm_format_horz_chroma_subsampling(pixel_format);
672 phasex_steps[COMP_0] = phasex_step;
673 phasex_steps[COMP_3] = phasex_step;
674 phasex_steps[COMP_1_2] = phasex_step / hsub;
679 static int calc_scaley_steps(struct drm_plane *plane,
680 uint32_t pixel_format, uint32_t src, uint32_t dest,
681 uint32_t phasey_steps[COMP_MAX])
683 struct mdp5_kms *mdp5_kms = get_kms(plane);
684 struct device *dev = mdp5_kms->dev->dev;
685 uint32_t phasey_step;
689 ret = calc_phase_step(src, dest, &phasey_step);
691 dev_err(dev, "Y scaling (%d->%d) failed: %d\n", src, dest, ret);
695 vsub = drm_format_vert_chroma_subsampling(pixel_format);
697 phasey_steps[COMP_0] = phasey_step;
698 phasey_steps[COMP_3] = phasey_step;
699 phasey_steps[COMP_1_2] = phasey_step / vsub;
704 static uint32_t get_scale_config(const struct mdp_format *format,
705 uint32_t src, uint32_t dst, bool horz)
707 bool scaling = format->is_yuv ? true : (src != dst);
708 uint32_t sub, pix_fmt = format->base.pixel_format;
709 uint32_t ya_filter, uv_filter;
710 bool yuv = format->is_yuv;
716 sub = horz ? drm_format_horz_chroma_subsampling(pix_fmt) :
717 drm_format_vert_chroma_subsampling(pix_fmt);
718 uv_filter = ((src / sub) <= dst) ?
719 SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
721 ya_filter = (src <= dst) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
724 return MDP5_PIPE_SCALE_CONFIG_SCALEX_EN |
725 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(ya_filter) |
726 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(ya_filter) |
727 COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter));
729 return MDP5_PIPE_SCALE_CONFIG_SCALEY_EN |
730 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(ya_filter) |
731 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(ya_filter) |
732 COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter));
735 static void calc_pixel_ext(const struct mdp_format *format,
736 uint32_t src, uint32_t dst, uint32_t phase_step[2],
737 int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX],
740 bool scaling = format->is_yuv ? true : (src != dst);
745 * We assume here that:
746 * 1. PCMN filter is used for downscale
747 * 2. bilinear filter is used for upscale
748 * 3. we are in a single pipe configuration
751 for (i = 0; i < COMP_MAX; i++) {
752 pix_ext_edge1[i] = 0;
753 pix_ext_edge2[i] = scaling ? 1 : 0;
757 static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
758 const struct mdp_format *format,
759 uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX],
760 uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX])
762 uint32_t pix_fmt = format->base.pixel_format;
763 uint32_t lr, tb, req;
766 for (i = 0; i < COMP_MAX; i++) {
767 uint32_t roi_w = src_w;
768 uint32_t roi_h = src_h;
770 if (format->is_yuv && i == COMP_1_2) {
771 roi_w /= drm_format_horz_chroma_subsampling(pix_fmt);
772 roi_h /= drm_format_vert_chroma_subsampling(pix_fmt);
775 lr = (pe_left[i] >= 0) ?
776 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(pe_left[i]) :
777 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(pe_left[i]);
779 lr |= (pe_right[i] >= 0) ?
780 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(pe_right[i]) :
781 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(pe_right[i]);
783 tb = (pe_top[i] >= 0) ?
784 MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(pe_top[i]) :
785 MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(pe_top[i]);
787 tb |= (pe_bottom[i] >= 0) ?
788 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(pe_bottom[i]) :
789 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(pe_bottom[i]);
791 req = MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(roi_w +
792 pe_left[i] + pe_right[i]);
794 req |= MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(roi_h +
795 pe_top[i] + pe_bottom[i]);
797 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_LR(pipe, i), lr);
798 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_TB(pipe, i), tb);
799 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(pipe, i), req);
801 DBG("comp-%d (L/R): rpt=%d/%d, ovf=%d/%d, req=%d", i,
802 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT),
803 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT),
804 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF),
805 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF),
806 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT));
808 DBG("comp-%d (T/B): rpt=%d/%d, ovf=%d/%d, req=%d", i,
809 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT),
810 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT),
811 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF),
812 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF),
813 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM));
821 int bottom[COMP_MAX];
829 static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms,
830 struct mdp5_hw_pipe *hwpipe,
831 struct drm_framebuffer *fb,
832 struct phase_step *step,
833 struct pixel_ext *pe,
834 u32 scale_config, u32 hdecm, u32 vdecm,
835 bool hflip, bool vflip,
836 int crtc_x, int crtc_y,
837 unsigned int crtc_w, unsigned int crtc_h,
838 u32 src_img_w, u32 src_img_h,
839 u32 src_x, u32 src_y,
840 u32 src_w, u32 src_h)
842 enum mdp5_pipe pipe = hwpipe->pipe;
843 bool has_pe = hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT;
844 const struct mdp_format *format =
845 to_mdp_format(msm_framebuffer_format(fb));
847 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe),
848 MDP5_PIPE_SRC_IMG_SIZE_WIDTH(src_img_w) |
849 MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(src_img_h));
851 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe),
852 MDP5_PIPE_SRC_SIZE_WIDTH(src_w) |
853 MDP5_PIPE_SRC_SIZE_HEIGHT(src_h));
855 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_XY(pipe),
856 MDP5_PIPE_SRC_XY_X(src_x) |
857 MDP5_PIPE_SRC_XY_Y(src_y));
859 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_SIZE(pipe),
860 MDP5_PIPE_OUT_SIZE_WIDTH(crtc_w) |
861 MDP5_PIPE_OUT_SIZE_HEIGHT(crtc_h));
863 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_XY(pipe),
864 MDP5_PIPE_OUT_XY_X(crtc_x) |
865 MDP5_PIPE_OUT_XY_Y(crtc_y));
867 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe),
868 MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
869 MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
870 MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
871 MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
872 COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
873 MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
874 MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
875 COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
876 MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) |
877 MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample));
879 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe),
880 MDP5_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
881 MDP5_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
882 MDP5_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
883 MDP5_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
885 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe),
886 (hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) |
887 (vflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_UD : 0) |
888 COND(has_pe, MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE) |
889 MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS));
891 /* not using secure mode: */
892 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0);
894 if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT)
895 mdp5_write_pixel_ext(mdp5_kms, pipe, format,
896 src_w, pe->left, pe->right,
897 src_h, pe->top, pe->bottom);
899 if (hwpipe->caps & MDP_PIPE_CAP_SCALE) {
900 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe),
902 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe),
904 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe),
906 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe),
908 mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe),
909 MDP5_PIPE_DECIMATION_VERT(vdecm) |
910 MDP5_PIPE_DECIMATION_HORZ(hdecm));
911 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe),
915 if (hwpipe->caps & MDP_PIPE_CAP_CSC) {
916 if (MDP_FORMAT_IS_YUV(format))
917 csc_enable(mdp5_kms, pipe,
918 mdp_get_default_csc_cfg(CSC_YUV2RGB));
920 csc_disable(mdp5_kms, pipe);
923 set_scanout_locked(mdp5_kms, pipe, fb);
926 static int mdp5_plane_mode_set(struct drm_plane *plane,
927 struct drm_crtc *crtc, struct drm_framebuffer *fb,
928 struct drm_rect *src, struct drm_rect *dest)
930 struct drm_plane_state *pstate = plane->state;
931 struct mdp5_hw_pipe *hwpipe = to_mdp5_plane_state(pstate)->hwpipe;
932 struct mdp5_kms *mdp5_kms = get_kms(plane);
933 enum mdp5_pipe pipe = hwpipe->pipe;
934 struct mdp5_hw_pipe *right_hwpipe;
935 const struct mdp_format *format;
936 uint32_t nplanes, config = 0;
937 struct phase_step step = { { 0 } };
938 struct pixel_ext pe = { { 0 } };
939 uint32_t hdecm = 0, vdecm = 0;
941 unsigned int rotation;
944 unsigned int crtc_w, crtc_h;
945 uint32_t src_x, src_y;
946 uint32_t src_w, src_h;
947 uint32_t src_img_w, src_img_h;
950 nplanes = fb->format->num_planes;
952 /* bad formats should already be rejected: */
953 if (WARN_ON(nplanes > pipe2nclients(pipe)))
956 format = to_mdp_format(msm_framebuffer_format(fb));
957 pix_format = format->base.pixel_format;
961 src_w = drm_rect_width(src);
962 src_h = drm_rect_height(src);
966 crtc_w = drm_rect_width(dest);
967 crtc_h = drm_rect_height(dest);
969 /* src values are in Q16 fixed point, convert to integer: */
975 src_img_w = min(fb->width, src_w);
976 src_img_h = min(fb->height, src_h);
978 DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", plane->name,
979 fb->base.id, src_x, src_y, src_w, src_h,
980 crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
982 right_hwpipe = to_mdp5_plane_state(pstate)->r_hwpipe;
985 * if the plane comprises of 2 hw pipes, assume that the width
986 * is split equally across them. The only parameters that varies
987 * between the 2 pipes are src_x and crtc_x
994 ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, step.x);
998 ret = calc_scaley_steps(plane, pix_format, src_h, crtc_h, step.y);
1002 if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT) {
1003 calc_pixel_ext(format, src_w, crtc_w, step.x,
1004 pe.left, pe.right, true);
1005 calc_pixel_ext(format, src_h, crtc_h, step.y,
1006 pe.top, pe.bottom, false);
1009 /* TODO calc hdecm, vdecm */
1011 /* SCALE is used to both scale and up-sample chroma components */
1012 config |= get_scale_config(format, src_w, crtc_w, true);
1013 config |= get_scale_config(format, src_h, crtc_h, false);
1014 DBG("scale config = %x", config);
1016 rotation = drm_rotation_simplify(pstate->rotation,
1018 DRM_MODE_REFLECT_X |
1019 DRM_MODE_REFLECT_Y);
1020 hflip = !!(rotation & DRM_MODE_REFLECT_X);
1021 vflip = !!(rotation & DRM_MODE_REFLECT_Y);
1023 mdp5_hwpipe_mode_set(mdp5_kms, hwpipe, fb, &step, &pe,
1024 config, hdecm, vdecm, hflip, vflip,
1025 crtc_x, crtc_y, crtc_w, crtc_h,
1026 src_img_w, src_img_h,
1027 src_x, src_y, src_w, src_h);
1029 mdp5_hwpipe_mode_set(mdp5_kms, right_hwpipe, fb, &step, &pe,
1030 config, hdecm, vdecm, hflip, vflip,
1031 crtc_x + crtc_w, crtc_y, crtc_w, crtc_h,
1032 src_img_w, src_img_h,
1033 src_x + src_w, src_y, src_w, src_h);
1039 * Use this func and the one below only after the atomic state has been
1040 * successfully swapped
1042 enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane)
1044 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
1046 if (WARN_ON(!pstate->hwpipe))
1049 return pstate->hwpipe->pipe;
1052 enum mdp5_pipe mdp5_plane_right_pipe(struct drm_plane *plane)
1054 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
1056 if (!pstate->r_hwpipe)
1059 return pstate->r_hwpipe->pipe;
1062 uint32_t mdp5_plane_get_flush(struct drm_plane *plane)
1064 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
1067 if (WARN_ON(!pstate->hwpipe))
1070 mask = pstate->hwpipe->flush_mask;
1072 if (pstate->r_hwpipe)
1073 mask |= pstate->r_hwpipe->flush_mask;
1078 /* initialize plane */
1079 struct drm_plane *mdp5_plane_init(struct drm_device *dev,
1080 enum drm_plane_type type)
1082 struct drm_plane *plane = NULL;
1083 struct mdp5_plane *mdp5_plane;
1086 mdp5_plane = kzalloc(sizeof(*mdp5_plane), GFP_KERNEL);
1092 plane = &mdp5_plane->base;
1094 mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats,
1095 ARRAY_SIZE(mdp5_plane->formats), false);
1097 ret = drm_universal_plane_init(dev, plane, 0xff, &mdp5_plane_funcs,
1098 mdp5_plane->formats, mdp5_plane->nformats,
1103 drm_plane_helper_add(plane, &mdp5_plane_helper_funcs);
1105 mdp5_plane_install_properties(plane, &plane->base);
1111 mdp5_plane_destroy(plane);
1113 return ERR_PTR(ret);