drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

   1 /*
   2  * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published by
   8  * the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <linux/sort.h>
  20 #include <drm/drm_mode.h>
  21 #include <drm/drm_crtc.h>
  22 #include <drm/drm_crtc_helper.h>
  23 #include <drm/drm_flip_work.h>
  24
  25 #include "mdp5_kms.h"
  26
  27 #define CURSOR_WIDTH    64
  28 #define CURSOR_HEIGHT   64
  29
  30 struct mdp5_crtc {
  31         struct drm_crtc base;
  32         int id;
  33         bool enabled;
  34
  35         spinlock_t lm_lock;     /* protect REG_MDP5_LM_* registers */
  36
  37         /* if there is a pending flip, these will be non-null: */
  38         struct drm_pending_vblank_event *event;
  39
  40         /* Bits have been flushed at the last commit,
  41          * used to decide if a vsync has happened since last commit.
  42          */
  43         u32 flushed_mask;
  44
  45 #define PENDING_CURSOR 0x1
  46 #define PENDING_FLIP   0x2
  47         atomic_t pending;
  48
  49         /* for unref'ing cursor bo's after scanout completes: */
  50         struct drm_flip_work unref_cursor_work;
  51
  52         struct mdp_irq vblank;
  53         struct mdp_irq err;
  54         struct mdp_irq pp_done;
  55
  56         struct completion pp_completion;
  57
  58         bool lm_cursor_enabled;
  59
  60         struct {
  61                 /* protect REG_MDP5_LM_CURSOR* registers and cursor scanout_bo*/
  62                 spinlock_t lock;
  63
  64                 /* current cursor being scanned out: */
  65                 struct drm_gem_object *scanout_bo;
  66                 uint64_t iova;
  67                 uint32_t width, height;
  68                 int x, y;
  69         } cursor;
  70 };
  71 #define to_mdp5_crtc(x) container_of(x, struct mdp5_crtc, base)
  72
  73 static void mdp5_crtc_restore_cursor(struct drm_crtc *crtc);
  74
  75 static struct mdp5_kms *get_kms(struct drm_crtc *crtc)
  76 {
  77         struct msm_drm_private *priv = crtc->dev->dev_private;
  78         return to_mdp5_kms(to_mdp_kms(priv->kms));
  79 }
  80
  81 static void request_pending(struct drm_crtc *crtc, uint32_t pending)
  82 {
  83         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
  84
  85         atomic_or(pending, &mdp5_crtc->pending);
  86         mdp_irq_register(&get_kms(crtc)->base, &mdp5_crtc->vblank);
  87 }
  88
  89 static void request_pp_done_pending(struct drm_crtc *crtc)
  90 {
  91         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
  92         reinit_completion(&mdp5_crtc->pp_completion);
  93 }
  94
  95 static u32 crtc_flush(struct drm_crtc *crtc, u32 flush_mask)
  96 {
  97         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
  98         struct mdp5_ctl *ctl = mdp5_cstate->ctl;
  99         struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
 100         bool start = !mdp5_cstate->defer_start;
 101
 102         mdp5_cstate->defer_start = false;
 103
 104         DBG("%s: flush=%08x", crtc->name, flush_mask);
 105
 106         return mdp5_ctl_commit(ctl, pipeline, flush_mask, start);
 107 }
 108
 109 /*
 110  * flush updates, to make sure hw is updated to new scanout fb,
 111  * so that we can safely queue unref to current fb (ie. next
 112  * vblank we know hw is done w/ previous scanout_fb).
 113  */
 114 static u32 crtc_flush_all(struct drm_crtc *crtc)
 115 {
 116         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
 117         struct mdp5_hw_mixer *mixer, *r_mixer;
 118         struct drm_plane *plane;
 119         uint32_t flush_mask = 0;
 120
 121         /* this should not happen: */
 122         if (WARN_ON(!mdp5_cstate->ctl))
 123                 return 0;
 124
 125         drm_atomic_crtc_for_each_plane(plane, crtc) {
 126                 if (!plane->state->visible)
 127                         continue;
 128                 flush_mask |= mdp5_plane_get_flush(plane);
 129         }
 130
 131         mixer = mdp5_cstate->pipeline.mixer;
 132         flush_mask |= mdp_ctl_flush_mask_lm(mixer->lm);
 133
 134         r_mixer = mdp5_cstate->pipeline.r_mixer;
 135         if (r_mixer)
 136                 flush_mask |= mdp_ctl_flush_mask_lm(r_mixer->lm);
 137
 138         return crtc_flush(crtc, flush_mask);
 139 }
 140
 141 /* if file!=NULL, this is preclose potential cancel-flip path */
 142 static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
 143 {
 144         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
 145         struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
 146         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 147         struct mdp5_ctl *ctl = mdp5_cstate->ctl;
 148         struct drm_device *dev = crtc->dev;
 149         struct drm_pending_vblank_event *event;
 150         unsigned long flags;
 151
 152         spin_lock_irqsave(&dev->event_lock, flags);
 153         event = mdp5_crtc->event;
 154         if (event) {
 155                 mdp5_crtc->event = NULL;
 156                 DBG("%s: send event: %p", crtc->name, event);
 157                 drm_crtc_send_vblank_event(crtc, event);
 158         }
 159         spin_unlock_irqrestore(&dev->event_lock, flags);
 160
 161         if (ctl && !crtc->state->enable) {
 162                 /* set STAGE_UNUSED for all layers */
 163                 mdp5_ctl_blend(ctl, pipeline, NULL, NULL, 0, 0);
 164                 /* XXX: What to do here? */
 165                 /* mdp5_crtc->ctl = NULL; */
 166         }
 167 }
 168
 169 static void unref_cursor_worker(struct drm_flip_work *work, void *val)
 170 {
 171         struct mdp5_crtc *mdp5_crtc =
 172                 container_of(work, struct mdp5_crtc, unref_cursor_work);
 173         struct mdp5_kms *mdp5_kms = get_kms(&mdp5_crtc->base);
 174         struct msm_kms *kms = &mdp5_kms->base.base;
 175
 176         msm_gem_put_iova(val, kms->aspace);
 177         drm_gem_object_put_unlocked(val);
 178 }
 179
 180 static void mdp5_crtc_destroy(struct drm_crtc *crtc)
 181 {
 182         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 183
 184         drm_crtc_cleanup(crtc);
 185         drm_flip_work_cleanup(&mdp5_crtc->unref_cursor_work);
 186
 187         kfree(mdp5_crtc);
 188 }
 189
 190 static inline u32 mdp5_lm_use_fg_alpha_mask(enum mdp_mixer_stage_id stage)
 191 {
 192         switch (stage) {
 193         case STAGE0: return MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA;
 194         case STAGE1: return MDP5_LM_BLEND_COLOR_OUT_STAGE1_FG_ALPHA;
 195         case STAGE2: return MDP5_LM_BLEND_COLOR_OUT_STAGE2_FG_ALPHA;
 196         case STAGE3: return MDP5_LM_BLEND_COLOR_OUT_STAGE3_FG_ALPHA;
 197         case STAGE4: return MDP5_LM_BLEND_COLOR_OUT_STAGE4_FG_ALPHA;
 198         case STAGE5: return MDP5_LM_BLEND_COLOR_OUT_STAGE5_FG_ALPHA;
 199         case STAGE6: return MDP5_LM_BLEND_COLOR_OUT_STAGE6_FG_ALPHA;
 200         default:
 201                 return 0;
 202         }
 203 }
 204
 205 /*
 206  * left/right pipe offsets for the stage array used in blend_setup()
 207  */
 208 #define PIPE_LEFT       0
 209 #define PIPE_RIGHT      1
 210
 211 /*
 212  * blend_setup() - blend all the planes of a CRTC
 213  *
 214  * If no base layer is available, border will be enabled as the base layer.
 215  * Otherwise all layers will be blended based on their stage calculated
 216  * in mdp5_crtc_atomic_check.
 217  */
 218 static void blend_setup(struct drm_crtc *crtc)
 219 {
 220         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 221         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
 222         struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
 223         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 224         struct drm_plane *plane;
 225         const struct mdp5_cfg_hw *hw_cfg;
 226         struct mdp5_plane_state *pstate, *pstates[STAGE_MAX + 1] = {NULL};
 227         const struct mdp_format *format;
 228         struct mdp5_hw_mixer *mixer = pipeline->mixer;
 229         uint32_t lm = mixer->lm;
 230         struct mdp5_hw_mixer *r_mixer = pipeline->r_mixer;
 231         uint32_t r_lm = r_mixer ? r_mixer->lm : 0;
 232         struct mdp5_ctl *ctl = mdp5_cstate->ctl;
 233         uint32_t blend_op, fg_alpha, bg_alpha, ctl_blend_flags = 0;
 234         unsigned long flags;
 235         enum mdp5_pipe stage[STAGE_MAX + 1][MAX_PIPE_STAGE] = { { SSPP_NONE } };
 236         enum mdp5_pipe r_stage[STAGE_MAX + 1][MAX_PIPE_STAGE] = { { SSPP_NONE } };
 237         int i, plane_cnt = 0;
 238         bool bg_alpha_enabled = false;
 239         u32 mixer_op_mode = 0;
 240         u32 val;
 241 #define blender(stage)  ((stage) - STAGE0)
 242
 243         hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
 244
 245         spin_lock_irqsave(&mdp5_crtc->lm_lock, flags);
 246
 247         /* ctl could be released already when we are shutting down: */
 248         /* XXX: Can this happen now? */
 249         if (!ctl)
 250                 goto out;
 251
 252         /* Collect all plane information */
 253         drm_atomic_crtc_for_each_plane(plane, crtc) {
 254                 enum mdp5_pipe right_pipe;
 255
 256                 if (!plane->state->visible)
 257                         continue;
 258
 259                 pstate = to_mdp5_plane_state(plane->state);
 260                 pstates[pstate->stage] = pstate;
 261                 stage[pstate->stage][PIPE_LEFT] = mdp5_plane_pipe(plane);
 262                 /*
 263                  * if we have a right mixer, stage the same pipe as we
 264                  * have on the left mixer
 265                  */
 266                 if (r_mixer)
 267                         r_stage[pstate->stage][PIPE_LEFT] =
 268                                                 mdp5_plane_pipe(plane);
 269                 /*
 270                  * if we have a right pipe (i.e, the plane comprises of 2
 271                  * hwpipes, then stage the right pipe on the right side of both
 272                  * the layer mixers
 273                  */
 274                 right_pipe = mdp5_plane_right_pipe(plane);
 275                 if (right_pipe) {
 276                         stage[pstate->stage][PIPE_RIGHT] = right_pipe;
 277                         r_stage[pstate->stage][PIPE_RIGHT] = right_pipe;
 278                 }
 279
 280                 plane_cnt++;
 281         }
 282
 283         if (!pstates[STAGE_BASE]) {
 284                 ctl_blend_flags |= MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT;
 285                 DBG("Border Color is enabled");
 286         } else if (plane_cnt) {
 287                 format = to_mdp_format(msm_framebuffer_format(pstates[STAGE_BASE]->base.fb));
 288
 289                 if (format->alpha_enable)
 290                         bg_alpha_enabled = true;
 291         }
 292
 293         /* The reset for blending */
 294         for (i = STAGE0; i <= STAGE_MAX; i++) {
 295                 if (!pstates[i])
 296                         continue;
 297
 298                 format = to_mdp_format(
 299                         msm_framebuffer_format(pstates[i]->base.fb));
 300                 plane = pstates[i]->base.plane;
 301                 blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
 302                         MDP5_LM_BLEND_OP_MODE_BG_ALPHA(BG_CONST);
 303                 fg_alpha = pstates[i]->alpha;
 304                 bg_alpha = 0xFF - pstates[i]->alpha;
 305
 306                 if (!format->alpha_enable && bg_alpha_enabled)
 307                         mixer_op_mode = 0;
 308                 else
 309                         mixer_op_mode |= mdp5_lm_use_fg_alpha_mask(i);
 310
 311                 DBG("Stage %d fg_alpha %x bg_alpha %x", i, fg_alpha, bg_alpha);
 312
 313                 if (format->alpha_enable && pstates[i]->premultiplied) {
 314                         blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
 315                                 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
 316                         if (fg_alpha != 0xff) {
 317                                 bg_alpha = fg_alpha;
 318                                 blend_op |=
 319                                         MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA |
 320                                         MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA;
 321                         } else {
 322                                 blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA;
 323                         }
 324                 } else if (format->alpha_enable) {
 325                         blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_PIXEL) |
 326                                 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
 327                         if (fg_alpha != 0xff) {
 328                                 bg_alpha = fg_alpha;
 329                                 blend_op |=
 330                                        MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA |
 331                                        MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA |
 332                                        MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA |
 333                                        MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA;
 334                         } else {
 335                                 blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA;
 336                         }
 337                 }
 338
 339                 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(lm,
 340                                 blender(i)), blend_op);
 341                 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(lm,
 342                                 blender(i)), fg_alpha);
 343                 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(lm,
 344                                 blender(i)), bg_alpha);
 345                 if (r_mixer) {
 346                         mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(r_lm,
 347                                         blender(i)), blend_op);
 348                         mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(r_lm,
 349                                         blender(i)), fg_alpha);
 350                         mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(r_lm,
 351                                         blender(i)), bg_alpha);
 352                 }
 353         }
 354
 355         val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm));
 356         mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm),
 357                    val | mixer_op_mode);
 358         if (r_mixer) {
 359                 val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm));
 360                 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm),
 361                            val | mixer_op_mode);
 362         }
 363
 364         mdp5_ctl_blend(ctl, pipeline, stage, r_stage, plane_cnt,
 365                        ctl_blend_flags);
 366 out:
 367         spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);
 368 }
 369
 370 static void mdp5_crtc_mode_set_nofb(struct drm_crtc *crtc)
 371 {
 372         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 373         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
 374         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 375         struct mdp5_hw_mixer *mixer = mdp5_cstate->pipeline.mixer;
 376         struct mdp5_hw_mixer *r_mixer = mdp5_cstate->pipeline.r_mixer;
 377         uint32_t lm = mixer->lm;
 378         u32 mixer_width, val;
 379         unsigned long flags;
 380         struct drm_display_mode *mode;
 381
 382         if (WARN_ON(!crtc->state))
 383                 return;
 384
 385         mode = &crtc->state->adjusted_mode;
 386
 387         DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
 388                         crtc->name, mode->base.id, mode->name,
 389                         mode->vrefresh, mode->clock,
 390                         mode->hdisplay, mode->hsync_start,
 391                         mode->hsync_end, mode->htotal,
 392                         mode->vdisplay, mode->vsync_start,
 393                         mode->vsync_end, mode->vtotal,
 394                         mode->type, mode->flags);
 395
 396         mixer_width = mode->hdisplay;
 397         if (r_mixer)
 398                 mixer_width /= 2;
 399
 400         spin_lock_irqsave(&mdp5_crtc->lm_lock, flags);
 401         mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(lm),
 402                         MDP5_LM_OUT_SIZE_WIDTH(mixer_width) |
 403                         MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay));
 404
 405         /* Assign mixer to LEFT side in source split mode */
 406         val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm));
 407         val &= ~MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT;
 408         mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm), val);
 409
 410         if (r_mixer) {
 411                 u32 r_lm = r_mixer->lm;
 412
 413                 mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(r_lm),
 414                            MDP5_LM_OUT_SIZE_WIDTH(mixer_width) |
 415                            MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay));
 416
 417                 /* Assign mixer to RIGHT side in source split mode */
 418                 val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm));
 419                 val |= MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT;
 420                 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm), val);
 421         }
 422
 423         spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);
 424 }
 425
 426 static void mdp5_crtc_atomic_disable(struct drm_crtc *crtc,
 427                                      struct drm_crtc_state *old_state)
 428 {
 429         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 430         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
 431         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 432         struct device *dev = &mdp5_kms->pdev->dev;
 433         unsigned long flags;
 434
 435         DBG("%s", crtc->name);
 436
 437         if (WARN_ON(!mdp5_crtc->enabled))
 438                 return;
 439
 440         /* Disable/save vblank irq handling before power is disabled */
 441         drm_crtc_vblank_off(crtc);
 442
 443         if (mdp5_cstate->cmd_mode)
 444                 mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->pp_done);
 445
 446         mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->err);
 447         pm_runtime_put_sync(dev);
 448
 449         if (crtc->state->event && !crtc->state->active) {
 450                 WARN_ON(mdp5_crtc->event);
 451                 spin_lock_irqsave(&mdp5_kms->dev->event_lock, flags);
 452                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 453                 crtc->state->event = NULL;
 454                 spin_unlock_irqrestore(&mdp5_kms->dev->event_lock, flags);
 455         }
 456
 457         mdp5_crtc->enabled = false;
 458 }
 459
 460 static void mdp5_crtc_atomic_enable(struct drm_crtc *crtc,
 461                                     struct drm_crtc_state *old_state)
 462 {
 463         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 464         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
 465         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 466         struct device *dev = &mdp5_kms->pdev->dev;
 467
 468         DBG("%s", crtc->name);
 469
 470         if (WARN_ON(mdp5_crtc->enabled))
 471                 return;
 472
 473         pm_runtime_get_sync(dev);
 474
 475         if (mdp5_crtc->lm_cursor_enabled) {
 476                 /*
 477                  * Restore LM cursor state, as it might have been lost
 478                  * with suspend:
 479                  */
 480                 if (mdp5_crtc->cursor.iova) {
 481                         unsigned long flags;
 482
 483                         spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
 484                         mdp5_crtc_restore_cursor(crtc);
 485                         spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
 486
 487                         mdp5_ctl_set_cursor(mdp5_cstate->ctl,
 488                                             &mdp5_cstate->pipeline, 0, true);
 489                 } else {
 490                         mdp5_ctl_set_cursor(mdp5_cstate->ctl,
 491                                             &mdp5_cstate->pipeline, 0, false);
 492                 }
 493         }
 494
 495         /* Restore vblank irq handling after power is enabled */
 496         drm_crtc_vblank_on(crtc);
 497
 498         mdp5_crtc_mode_set_nofb(crtc);
 499
 500         mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->err);
 501
 502         if (mdp5_cstate->cmd_mode)
 503                 mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->pp_done);
 504
 505         mdp5_crtc->enabled = true;
 506 }
 507
 508 int mdp5_crtc_setup_pipeline(struct drm_crtc *crtc,
 509                              struct drm_crtc_state *new_crtc_state,
 510                              bool need_right_mixer)
 511 {
 512         struct mdp5_crtc_state *mdp5_cstate =
 513                         to_mdp5_crtc_state(new_crtc_state);
 514         struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
 515         struct mdp5_interface *intf;
 516         bool new_mixer = false;
 517
 518         new_mixer = !pipeline->mixer;
 519
 520         if ((need_right_mixer && !pipeline->r_mixer) ||
 521             (!need_right_mixer && pipeline->r_mixer))
 522                 new_mixer = true;
 523
 524         if (new_mixer) {
 525                 struct mdp5_hw_mixer *old_mixer = pipeline->mixer;
 526                 struct mdp5_hw_mixer *old_r_mixer = pipeline->r_mixer;
 527                 u32 caps;
 528                 int ret;
 529
 530                 caps = MDP_LM_CAP_DISPLAY;
 531                 if (need_right_mixer)
 532                         caps |= MDP_LM_CAP_PAIR;
 533
 534                 ret = mdp5_mixer_assign(new_crtc_state->state, crtc, caps,
 535                                         &pipeline->mixer, need_right_mixer ?
 536                                         &pipeline->r_mixer : NULL);
 537                 if (ret)
 538                         return ret;
 539
 540                 mdp5_mixer_release(new_crtc_state->state, old_mixer);
 541                 if (old_r_mixer) {
 542                         mdp5_mixer_release(new_crtc_state->state, old_r_mixer);
 543                         if (!need_right_mixer)
 544                                 pipeline->r_mixer = NULL;
 545                 }
 546         }
 547
 548         /*
 549          * these should have been already set up in the encoder's atomic
 550          * check (called by drm_atomic_helper_check_modeset)
 551          */
 552         intf = pipeline->intf;
 553
 554         mdp5_cstate->err_irqmask = intf2err(intf->num);
 555         mdp5_cstate->vblank_irqmask = intf2vblank(pipeline->mixer, intf);
 556
 557         if ((intf->type == INTF_DSI) &&
 558             (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)) {
 559                 mdp5_cstate->pp_done_irqmask = lm2ppdone(pipeline->mixer);
 560                 mdp5_cstate->cmd_mode = true;
 561         } else {
 562                 mdp5_cstate->pp_done_irqmask = 0;
 563                 mdp5_cstate->cmd_mode = false;
 564         }
 565
 566         return 0;
 567 }
 568
 569 struct plane_state {
 570         struct drm_plane *plane;
 571         struct mdp5_plane_state *state;
 572 };
 573
 574 static int pstate_cmp(const void *a, const void *b)
 575 {
 576         struct plane_state *pa = (struct plane_state *)a;
 577         struct plane_state *pb = (struct plane_state *)b;
 578         return pa->state->zpos - pb->state->zpos;
 579 }
 580
 581 /* is there a helper for this? */
 582 static bool is_fullscreen(struct drm_crtc_state *cstate,
 583                 struct drm_plane_state *pstate)
 584 {
 585         return (pstate->crtc_x <= 0) && (pstate->crtc_y <= 0) &&
 586                 ((pstate->crtc_x + pstate->crtc_w) >= cstate->mode.hdisplay) &&
 587                 ((pstate->crtc_y + pstate->crtc_h) >= cstate->mode.vdisplay);
 588 }
 589
 590 static enum mdp_mixer_stage_id get_start_stage(struct drm_crtc *crtc,
 591                                         struct drm_crtc_state *new_crtc_state,
 592                                         struct drm_plane_state *bpstate)
 593 {
 594         struct mdp5_crtc_state *mdp5_cstate =
 595                         to_mdp5_crtc_state(new_crtc_state);
 596
 597         /*
 598          * if we're in source split mode, it's mandatory to have
 599          * border out on the base stage
 600          */
 601         if (mdp5_cstate->pipeline.r_mixer)
 602                 return STAGE0;
 603
 604         /* if the bottom-most layer is not fullscreen, we need to use
 605          * it for solid-color:
 606          */
 607         if (!is_fullscreen(new_crtc_state, bpstate))
 608                 return STAGE0;
 609
 610         return STAGE_BASE;
 611 }
 612
 613 static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
 614                 struct drm_crtc_state *state)
 615 {
 616         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 617         struct drm_plane *plane;
 618         struct drm_device *dev = crtc->dev;
 619         struct plane_state pstates[STAGE_MAX + 1];
 620         const struct mdp5_cfg_hw *hw_cfg;
 621         const struct drm_plane_state *pstate;
 622         const struct drm_display_mode *mode = &state->adjusted_mode;
 623         bool cursor_plane = false;
 624         bool need_right_mixer = false;
 625         int cnt = 0, i;
 626         int ret;
 627         enum mdp_mixer_stage_id start;
 628
 629         DBG("%s: check", crtc->name);
 630
 631         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
 632                 if (!pstate->visible)
 633                         continue;
 634
 635                 pstates[cnt].plane = plane;
 636                 pstates[cnt].state = to_mdp5_plane_state(pstate);
 637
 638                 /*
 639                  * if any plane on this crtc uses 2 hwpipes, then we need
 640                  * the crtc to have a right hwmixer.
 641                  */
 642                 if (pstates[cnt].state->r_hwpipe)
 643                         need_right_mixer = true;
 644                 cnt++;
 645
 646                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
 647                         cursor_plane = true;
 648         }
 649
 650         /* bail out early if there aren't any planes */
 651         if (!cnt)
 652                 return 0;
 653
 654         hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
 655
 656         /*
 657          * we need a right hwmixer if the mode's width is greater than a single
 658          * LM's max width
 659          */
 660         if (mode->hdisplay > hw_cfg->lm.max_width)
 661                 need_right_mixer = true;
 662
 663         ret = mdp5_crtc_setup_pipeline(crtc, state, need_right_mixer);
 664         if (ret) {
 665                 dev_err(dev->dev, "couldn't assign mixers %d\n", ret);
 666                 return ret;
 667         }
 668
 669         /* assign a stage based on sorted zpos property */
 670         sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
 671
 672         /* trigger a warning if cursor isn't the highest zorder */
 673         WARN_ON(cursor_plane &&
 674                 (pstates[cnt - 1].plane->type != DRM_PLANE_TYPE_CURSOR));
 675
 676         start = get_start_stage(crtc, state, &pstates[0].state->base);
 677
 678         /* verify that there are not too many planes attached to crtc
 679          * and that we don't have conflicting mixer stages:
 680          */
 681         if ((cnt + start - 1) >= hw_cfg->lm.nb_stages) {
 682                 dev_err(dev->dev, "too many planes! cnt=%d, start stage=%d\n",
 683                         cnt, start);
 684                 return -EINVAL;
 685         }
 686
 687         for (i = 0; i < cnt; i++) {
 688                 if (cursor_plane && (i == (cnt - 1)))
 689                         pstates[i].state->stage = hw_cfg->lm.nb_stages;
 690                 else
 691                         pstates[i].state->stage = start + i;
 692                 DBG("%s: assign pipe %s on stage=%d", crtc->name,
 693                                 pstates[i].plane->name,
 694                                 pstates[i].state->stage);
 695         }
 696
 697         return 0;
 698 }
 699
 700 static void mdp5_crtc_atomic_begin(struct drm_crtc *crtc,
 701                                    struct drm_crtc_state *old_crtc_state)
 702 {
 703         DBG("%s: begin", crtc->name);
 704 }
 705
 706 static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc,
 707                                    struct drm_crtc_state *old_crtc_state)
 708 {
 709         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 710         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
 711         struct drm_device *dev = crtc->dev;
 712         unsigned long flags;
 713
 714         DBG("%s: event: %p", crtc->name, crtc->state->event);
 715
 716         WARN_ON(mdp5_crtc->event);
 717
 718         spin_lock_irqsave(&dev->event_lock, flags);
 719         mdp5_crtc->event = crtc->state->event;
 720         crtc->state->event = NULL;
 721         spin_unlock_irqrestore(&dev->event_lock, flags);
 722
 723         /*
 724          * If no CTL has been allocated in mdp5_crtc_atomic_check(),
 725          * it means we are trying to flush a CRTC whose state is disabled:
 726          * nothing else needs to be done.
 727          */
 728         /* XXX: Can this happen now ? */
 729         if (unlikely(!mdp5_cstate->ctl))
 730                 return;
 731
 732         blend_setup(crtc);
 733
 734         /* PP_DONE irq is only used by command mode for now.
 735          * It is better to request pending before FLUSH and START trigger
 736          * to make sure no pp_done irq missed.
 737          * This is safe because no pp_done will happen before SW trigger
 738          * in command mode.
 739          */
 740         if (mdp5_cstate->cmd_mode)
 741                 request_pp_done_pending(crtc);
 742
 743         mdp5_crtc->flushed_mask = crtc_flush_all(crtc);
 744
 745         /* XXX are we leaking out state here? */
 746         mdp5_crtc->vblank.irqmask = mdp5_cstate->vblank_irqmask;
 747         mdp5_crtc->err.irqmask = mdp5_cstate->err_irqmask;
 748         mdp5_crtc->pp_done.irqmask = mdp5_cstate->pp_done_irqmask;
 749
 750         request_pending(crtc, PENDING_FLIP);
 751 }
 752
 753 static void get_roi(struct drm_crtc *crtc, uint32_t *roi_w, uint32_t *roi_h)
 754 {
 755         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 756         uint32_t xres = crtc->mode.hdisplay;
 757         uint32_t yres = crtc->mode.vdisplay;
 758
 759         /*
 760          * Cursor Region Of Interest (ROI) is a plane read from cursor
 761          * buffer to render. The ROI region is determined by the visibility of
 762          * the cursor point. In the default Cursor image the cursor point will
 763          * be at the top left of the cursor image.
 764          *
 765          * Without rotation:
 766          * If the cursor point reaches the right (xres - x < cursor.width) or
 767          * bottom (yres - y < cursor.height) boundary of the screen, then ROI
 768          * width and ROI height need to be evaluated to crop the cursor image
 769          * accordingly.
 770          * (xres-x) will be new cursor width when x > (xres - cursor.width)
 771          * (yres-y) will be new cursor height when y > (yres - cursor.height)
 772          *
 773          * With rotation:
 774          * We get negative x and/or y coordinates.
 775          * (cursor.width - abs(x)) will be new cursor width when x < 0
 776          * (cursor.height - abs(y)) will be new cursor width when y < 0
 777          */
 778         if (mdp5_crtc->cursor.x >= 0)
 779                 *roi_w = min(mdp5_crtc->cursor.width, xres -
 780                         mdp5_crtc->cursor.x);
 781         else
 782                 *roi_w = mdp5_crtc->cursor.width - abs(mdp5_crtc->cursor.x);
 783         if (mdp5_crtc->cursor.y >= 0)
 784                 *roi_h = min(mdp5_crtc->cursor.height, yres -
 785                         mdp5_crtc->cursor.y);
 786         else
 787                 *roi_h = mdp5_crtc->cursor.height - abs(mdp5_crtc->cursor.y);
 788 }
 789
 790 static void mdp5_crtc_restore_cursor(struct drm_crtc *crtc)
 791 {
 792         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
 793         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 794         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 795         const enum mdp5_cursor_alpha cur_alpha = CURSOR_ALPHA_PER_PIXEL;
 796         uint32_t blendcfg, stride;
 797         uint32_t x, y, src_x, src_y, width, height;
 798         uint32_t roi_w, roi_h;
 799         int lm;
 800
 801         assert_spin_locked(&mdp5_crtc->cursor.lock);
 802
 803         lm = mdp5_cstate->pipeline.mixer->lm;
 804
 805         x = mdp5_crtc->cursor.x;
 806         y = mdp5_crtc->cursor.y;
 807         width = mdp5_crtc->cursor.width;
 808         height = mdp5_crtc->cursor.height;
 809
 810         stride = width * drm_format_plane_cpp(DRM_FORMAT_ARGB8888, 0);
 811
 812         get_roi(crtc, &roi_w, &roi_h);
 813
 814         /* If cusror buffer overlaps due to rotation on the
 815          * upper or left screen border the pixel offset inside
 816          * the cursor buffer of the ROI is the positive overlap
 817          * distance.
 818          */
 819         if (mdp5_crtc->cursor.x < 0) {
 820                 src_x = abs(mdp5_crtc->cursor.x);
 821                 x = 0;
 822         } else {
 823                 src_x = 0;
 824         }
 825         if (mdp5_crtc->cursor.y < 0) {
 826                 src_y = abs(mdp5_crtc->cursor.y);
 827                 y = 0;
 828         } else {
 829                 src_y = 0;
 830         }
 831         DBG("%s: x=%d, y=%d roi_w=%d roi_h=%d src_x=%d src_y=%d",
 832                 crtc->name, x, y, roi_w, roi_h, src_x, src_y);
 833
 834         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_STRIDE(lm), stride);
 835         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_FORMAT(lm),
 836                         MDP5_LM_CURSOR_FORMAT_FORMAT(CURSOR_FMT_ARGB8888));
 837         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_IMG_SIZE(lm),
 838                         MDP5_LM_CURSOR_IMG_SIZE_SRC_H(height) |
 839                         MDP5_LM_CURSOR_IMG_SIZE_SRC_W(width));
 840         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm),
 841                         MDP5_LM_CURSOR_SIZE_ROI_H(roi_h) |
 842                         MDP5_LM_CURSOR_SIZE_ROI_W(roi_w));
 843         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_START_XY(lm),
 844                         MDP5_LM_CURSOR_START_XY_Y_START(y) |
 845                         MDP5_LM_CURSOR_START_XY_X_START(x));
 846         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_XY(lm),
 847                         MDP5_LM_CURSOR_XY_SRC_Y(src_y) |
 848                         MDP5_LM_CURSOR_XY_SRC_X(src_x));
 849         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BASE_ADDR(lm),
 850                         mdp5_crtc->cursor.iova);
 851
 852         blendcfg = MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN;
 853         blendcfg |= MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(cur_alpha);
 854         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BLEND_CONFIG(lm), blendcfg);
 855 }
 856
 857 static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,
 858                 struct drm_file *file, uint32_t handle,
 859                 uint32_t width, uint32_t height)
 860 {
 861         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 862         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
 863         struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
 864         struct drm_device *dev = crtc->dev;
 865         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 866         struct platform_device *pdev = mdp5_kms->pdev;
 867         struct msm_kms *kms = &mdp5_kms->base.base;
 868         struct drm_gem_object *cursor_bo, *old_bo = NULL;
 869         struct mdp5_ctl *ctl;
 870         int ret;
 871         uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
 872         bool cursor_enable = true;
 873         unsigned long flags;
 874
 875         if (!mdp5_crtc->lm_cursor_enabled) {
 876                 dev_warn(dev->dev,
 877                          "cursor_set is deprecated with cursor planes\n");
 878                 return -EINVAL;
 879         }
 880
 881         if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
 882                 dev_err(dev->dev, "bad cursor size: %dx%d\n", width, height);
 883                 return -EINVAL;
 884         }
 885
 886         ctl = mdp5_cstate->ctl;
 887         if (!ctl)
 888                 return -EINVAL;
 889
 890         /* don't support LM cursors when we we have source split enabled */
 891         if (mdp5_cstate->pipeline.r_mixer)
 892                 return -EINVAL;
 893
 894         if (!handle) {
 895                 DBG("Cursor off");
 896                 cursor_enable = false;
 897                 mdp5_crtc->cursor.iova = 0;
 898                 pm_runtime_get_sync(&pdev->dev);
 899                 goto set_cursor;
 900         }
 901
 902         cursor_bo = drm_gem_object_lookup(file, handle);
 903         if (!cursor_bo)
 904                 return -ENOENT;
 905
 906         ret = msm_gem_get_iova(cursor_bo, kms->aspace,
 907                         &mdp5_crtc->cursor.iova);
 908         if (ret)
 909                 return -EINVAL;
 910
 911         pm_runtime_get_sync(&pdev->dev);
 912
 913         spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
 914         old_bo = mdp5_crtc->cursor.scanout_bo;
 915
 916         mdp5_crtc->cursor.scanout_bo = cursor_bo;
 917         mdp5_crtc->cursor.width = width;
 918         mdp5_crtc->cursor.height = height;
 919
 920         mdp5_crtc_restore_cursor(crtc);
 921
 922         spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
 923
 924 set_cursor:
 925         ret = mdp5_ctl_set_cursor(ctl, pipeline, 0, cursor_enable);
 926         if (ret) {
 927                 dev_err(dev->dev, "failed to %sable cursor: %d\n",
 928                                 cursor_enable ? "en" : "dis", ret);
 929                 goto end;
 930         }
 931
 932         crtc_flush(crtc, flush_mask);
 933
 934 end:
 935         pm_runtime_put_sync(&pdev->dev);
 936         if (old_bo) {
 937                 drm_flip_work_queue(&mdp5_crtc->unref_cursor_work, old_bo);
 938                 /* enable vblank to complete cursor work: */
 939                 request_pending(crtc, PENDING_CURSOR);
 940         }
 941         return ret;
 942 }
 943
 944 static int mdp5_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 945 {
 946         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 947         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 948         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
 949         uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
 950         struct drm_device *dev = crtc->dev;
 951         uint32_t roi_w;
 952         uint32_t roi_h;
 953         unsigned long flags;
 954
 955         if (!mdp5_crtc->lm_cursor_enabled) {
 956                 dev_warn(dev->dev,
 957                          "cursor_move is deprecated with cursor planes\n");
 958                 return -EINVAL;
 959         }
 960
 961         /* don't support LM cursors when we we have source split enabled */
 962         if (mdp5_cstate->pipeline.r_mixer)
 963                 return -EINVAL;
 964
 965         /* In case the CRTC is disabled, just drop the cursor update */
 966         if (unlikely(!crtc->state->enable))
 967                 return 0;
 968
 969         /* accept negative x/y coordinates up to maximum cursor overlap */
 970         mdp5_crtc->cursor.x = x = max(x, -(int)mdp5_crtc->cursor.width);
 971         mdp5_crtc->cursor.y = y = max(y, -(int)mdp5_crtc->cursor.height);
 972
 973         get_roi(crtc, &roi_w, &roi_h);
 974
 975         pm_runtime_get_sync(&mdp5_kms->pdev->dev);
 976
 977         spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
 978         mdp5_crtc_restore_cursor(crtc);
 979         spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
 980
 981         crtc_flush(crtc, flush_mask);
 982
 983         pm_runtime_put_sync(&mdp5_kms->pdev->dev);
 984
 985         return 0;
 986 }
 987
 988 static void
 989 mdp5_crtc_atomic_print_state(struct drm_printer *p,
 990                              const struct drm_crtc_state *state)
 991 {
 992         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(state);
 993         struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
 994         struct mdp5_kms *mdp5_kms = get_kms(state->crtc);
 995
 996         if (WARN_ON(!pipeline))
 997                 return;
 998
 999         if (mdp5_cstate->ctl)
1000                 drm_printf(p, "\tctl=%d\n", mdp5_ctl_get_ctl_id(mdp5_cstate->ctl));
1001
1002         drm_printf(p, "\thwmixer=%s\n", pipeline->mixer ?
1003                         pipeline->mixer->name : "(null)");
1004
1005         if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT)
1006                 drm_printf(p, "\tright hwmixer=%s\n", pipeline->r_mixer ?
1007                            pipeline->r_mixer->name : "(null)");
1008
1009         drm_printf(p, "\tcmd_mode=%d\n", mdp5_cstate->cmd_mode);
1010 }
1011
1012 static void mdp5_crtc_reset(struct drm_crtc *crtc)
1013 {
1014         struct mdp5_crtc_state *mdp5_cstate;
1015
1016         if (crtc->state) {
1017                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
1018                 kfree(to_mdp5_crtc_state(crtc->state));
1019         }
1020
1021         mdp5_cstate = kzalloc(sizeof(*mdp5_cstate), GFP_KERNEL);
1022
1023         if (mdp5_cstate) {
1024                 mdp5_cstate->base.crtc = crtc;
1025                 crtc->state = &mdp5_cstate->base;
1026         }
1027 }
1028
1029 static struct drm_crtc_state *
1030 mdp5_crtc_duplicate_state(struct drm_crtc *crtc)
1031 {
1032         struct mdp5_crtc_state *mdp5_cstate;
1033
1034         if (WARN_ON(!crtc->state))
1035                 return NULL;
1036
1037         mdp5_cstate = kmemdup(to_mdp5_crtc_state(crtc->state),
1038                               sizeof(*mdp5_cstate), GFP_KERNEL);
1039         if (!mdp5_cstate)
1040                 return NULL;
1041
1042         __drm_atomic_helper_crtc_duplicate_state(crtc, &mdp5_cstate->base);
1043
1044         return &mdp5_cstate->base;
1045 }
1046
1047 static void mdp5_crtc_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *state)
1048 {
1049         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(state);
1050
1051         __drm_atomic_helper_crtc_destroy_state(state);
1052
1053         kfree(mdp5_cstate);
1054 }
1055
1056 static const struct drm_crtc_funcs mdp5_crtc_funcs = {
1057         .set_config = drm_atomic_helper_set_config,
1058         .destroy = mdp5_crtc_destroy,
1059         .page_flip = drm_atomic_helper_page_flip,
1060         .reset = mdp5_crtc_reset,
1061         .atomic_duplicate_state = mdp5_crtc_duplicate_state,
1062         .atomic_destroy_state = mdp5_crtc_destroy_state,
1063         .cursor_set = mdp5_crtc_cursor_set,
1064         .cursor_move = mdp5_crtc_cursor_move,
1065         .atomic_print_state = mdp5_crtc_atomic_print_state,
1066 };
1067
1068 static const struct drm_crtc_helper_funcs mdp5_crtc_helper_funcs = {
1069         .mode_set_nofb = mdp5_crtc_mode_set_nofb,
1070         .atomic_check = mdp5_crtc_atomic_check,
1071         .atomic_begin = mdp5_crtc_atomic_begin,
1072         .atomic_flush = mdp5_crtc_atomic_flush,
1073         .atomic_enable = mdp5_crtc_atomic_enable,
1074         .atomic_disable = mdp5_crtc_atomic_disable,
1075 };
1076
1077 static void mdp5_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus)
1078 {
1079         struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, vblank);
1080         struct drm_crtc *crtc = &mdp5_crtc->base;
1081         struct msm_drm_private *priv = crtc->dev->dev_private;
1082         unsigned pending;
1083
1084         mdp_irq_unregister(&get_kms(crtc)->base, &mdp5_crtc->vblank);
1085
1086         pending = atomic_xchg(&mdp5_crtc->pending, 0);
1087
1088         if (pending & PENDING_FLIP) {
1089                 complete_flip(crtc, NULL);
1090         }
1091
1092         if (pending & PENDING_CURSOR)
1093                 drm_flip_work_commit(&mdp5_crtc->unref_cursor_work, priv->wq);
1094 }
1095
1096 static void mdp5_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
1097 {
1098         struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, err);
1099
1100         DBG("%s: error: %08x", mdp5_crtc->base.name, irqstatus);
1101 }
1102
1103 static void mdp5_crtc_pp_done_irq(struct mdp_irq *irq, uint32_t irqstatus)
1104 {
1105         struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc,
1106                                                                 pp_done);
1107
1108         complete(&mdp5_crtc->pp_completion);
1109 }
1110
1111 static void mdp5_crtc_wait_for_pp_done(struct drm_crtc *crtc)
1112 {
1113         struct drm_device *dev = crtc->dev;
1114         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
1115         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1116         int ret;
1117
1118         ret = wait_for_completion_timeout(&mdp5_crtc->pp_completion,
1119                                                 msecs_to_jiffies(50));
1120         if (ret == 0)
1121                 dev_warn_ratelimited(dev->dev, "pp done time out, lm=%d\n",
1122                                      mdp5_cstate->pipeline.mixer->lm);
1123 }
1124
1125 static void mdp5_crtc_wait_for_flush_done(struct drm_crtc *crtc)
1126 {
1127         struct drm_device *dev = crtc->dev;
1128         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
1129         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1130         struct mdp5_ctl *ctl = mdp5_cstate->ctl;
1131         int ret;
1132
1133         /* Should not call this function if crtc is disabled. */
1134         if (!ctl)
1135                 return;
1136
1137         ret = drm_crtc_vblank_get(crtc);
1138         if (ret)
1139                 return;
1140
1141         ret = wait_event_timeout(dev->vblank[drm_crtc_index(crtc)].queue,
1142                 ((mdp5_ctl_get_commit_status(ctl) &
1143                 mdp5_crtc->flushed_mask) == 0),
1144                 msecs_to_jiffies(50));
1145         if (ret <= 0)
1146                 dev_warn(dev->dev, "vblank time out, crtc=%d\n", mdp5_crtc->id);
1147
1148         mdp5_crtc->flushed_mask = 0;
1149
1150         drm_crtc_vblank_put(crtc);
1151 }
1152
1153 uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc)
1154 {
1155         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
1156         return mdp5_crtc->vblank.irqmask;
1157 }
1158
1159 void mdp5_crtc_set_pipeline(struct drm_crtc *crtc)
1160 {
1161         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1162         struct mdp5_kms *mdp5_kms = get_kms(crtc);
1163
1164         /* should this be done elsewhere ? */
1165         mdp_irq_update(&mdp5_kms->base);
1166
1167         mdp5_ctl_set_pipeline(mdp5_cstate->ctl, &mdp5_cstate->pipeline);
1168 }
1169
1170 struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc)
1171 {
1172         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1173
1174         return mdp5_cstate->ctl;
1175 }
1176
1177 struct mdp5_hw_mixer *mdp5_crtc_get_mixer(struct drm_crtc *crtc)
1178 {
1179         struct mdp5_crtc_state *mdp5_cstate;
1180
1181         if (WARN_ON(!crtc))
1182                 return ERR_PTR(-EINVAL);
1183
1184         mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1185
1186         return WARN_ON(!mdp5_cstate->pipeline.mixer) ?
1187                 ERR_PTR(-EINVAL) : mdp5_cstate->pipeline.mixer;
1188 }
1189
1190 struct mdp5_pipeline *mdp5_crtc_get_pipeline(struct drm_crtc *crtc)
1191 {
1192         struct mdp5_crtc_state *mdp5_cstate;
1193
1194         if (WARN_ON(!crtc))
1195                 return ERR_PTR(-EINVAL);
1196
1197         mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1198
1199         return &mdp5_cstate->pipeline;
1200 }
1201
1202 void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc)
1203 {
1204         struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1205
1206         if (mdp5_cstate->cmd_mode)
1207                 mdp5_crtc_wait_for_pp_done(crtc);
1208         else
1209                 mdp5_crtc_wait_for_flush_done(crtc);
1210 }
1211
1212 /* initialize crtc */
1213 struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
1214                                 struct drm_plane *plane,
1215                                 struct drm_plane *cursor_plane, int id)
1216 {
1217         struct drm_crtc *crtc = NULL;
1218         struct mdp5_crtc *mdp5_crtc;
1219
1220         mdp5_crtc = kzalloc(sizeof(*mdp5_crtc), GFP_KERNEL);
1221         if (!mdp5_crtc)
1222                 return ERR_PTR(-ENOMEM);
1223
1224         crtc = &mdp5_crtc->base;
1225
1226         mdp5_crtc->id = id;
1227
1228         spin_lock_init(&mdp5_crtc->lm_lock);
1229         spin_lock_init(&mdp5_crtc->cursor.lock);
1230         init_completion(&mdp5_crtc->pp_completion);
1231
1232         mdp5_crtc->vblank.irq = mdp5_crtc_vblank_irq;
1233         mdp5_crtc->err.irq = mdp5_crtc_err_irq;
1234         mdp5_crtc->pp_done.irq = mdp5_crtc_pp_done_irq;
1235
1236         mdp5_crtc->lm_cursor_enabled = cursor_plane ? false : true;
1237
1238         drm_crtc_init_with_planes(dev, crtc, plane, cursor_plane,
1239                                   &mdp5_crtc_funcs, NULL);
1240
1241         drm_flip_work_init(&mdp5_crtc->unref_cursor_work,
1242                         "unref cursor", unref_cursor_worker);
1243
1244         drm_crtc_helper_add(crtc, &mdp5_crtc_helper_funcs);
1245
1246         return crtc;
1247 }