2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
24 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev);
26 static int mdp4_hw_init(struct msm_kms *kms)
28 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
29 struct drm_device *dev = mdp4_kms->dev;
30 uint32_t version, major, minor, dmap_cfg, vg_cfg;
34 pm_runtime_get_sync(dev->dev);
36 mdp4_enable(mdp4_kms);
37 version = mdp4_read(mdp4_kms, REG_MDP4_VERSION);
38 mdp4_disable(mdp4_kms);
40 major = FIELD(version, MDP4_VERSION_MAJOR);
41 minor = FIELD(version, MDP4_VERSION_MINOR);
43 DBG("found MDP4 version v%d.%d", major, minor);
46 dev_err(dev->dev, "unexpected MDP version: v%d.%d\n",
52 mdp4_kms->rev = minor;
54 if (mdp4_kms->rev > 1) {
55 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff);
56 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f);
59 mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3);
61 /* max read pending cmd config, 3 pending requests: */
62 mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222);
64 clk = clk_get_rate(mdp4_kms->clk);
66 if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) {
67 dmap_cfg = 0x47; /* 16 bytes-burst x 8 req */
68 vg_cfg = 0x47; /* 16 bytes-burs x 8 req */
70 dmap_cfg = 0x27; /* 8 bytes-burst x 8 req */
71 vg_cfg = 0x43; /* 16 bytes-burst x 4 req */
74 DBG("fetch config: dmap=%02x, vg=%02x", dmap_cfg, vg_cfg);
76 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg);
77 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg);
79 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg);
80 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg);
81 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg);
82 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg);
84 if (mdp4_kms->rev >= 2)
85 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1);
86 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, 0);
88 /* disable CSC matrix / YUV by default: */
89 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0);
90 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0);
91 mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0);
92 mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0);
93 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0);
94 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0);
96 if (mdp4_kms->rev > 1)
97 mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1);
100 pm_runtime_put_sync(dev->dev);
105 static void mdp4_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state)
107 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
109 struct drm_crtc *crtc;
110 struct drm_crtc_state *crtc_state;
112 mdp4_enable(mdp4_kms);
115 for_each_new_crtc_in_state(state, crtc, crtc_state, i)
116 drm_crtc_vblank_get(crtc);
119 static void mdp4_complete_commit(struct msm_kms *kms, struct drm_atomic_state *state)
121 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
123 struct drm_crtc *crtc;
124 struct drm_crtc_state *crtc_state;
126 drm_atomic_helper_wait_for_vblanks(mdp4_kms->dev, state);
129 for_each_new_crtc_in_state(state, crtc, crtc_state, i)
130 drm_crtc_vblank_put(crtc);
132 mdp4_disable(mdp4_kms);
135 static void mdp4_wait_for_crtc_commit_done(struct msm_kms *kms,
136 struct drm_crtc *crtc)
138 mdp4_crtc_wait_for_commit_done(crtc);
141 static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate,
142 struct drm_encoder *encoder)
144 /* if we had >1 encoder, we'd need something more clever: */
145 switch (encoder->encoder_type) {
146 case DRM_MODE_ENCODER_TMDS:
147 return mdp4_dtv_round_pixclk(encoder, rate);
148 case DRM_MODE_ENCODER_LVDS:
149 case DRM_MODE_ENCODER_DSI:
155 static const char * const iommu_ports[] = {
156 "mdp_port0_cb0", "mdp_port1_cb0",
159 static void mdp4_destroy(struct msm_kms *kms)
161 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
162 struct device *dev = mdp4_kms->dev->dev;
163 struct msm_gem_address_space *aspace = kms->aspace;
165 if (mdp4_kms->blank_cursor_iova)
166 msm_gem_put_iova(mdp4_kms->blank_cursor_bo, kms->aspace);
167 drm_gem_object_put_unlocked(mdp4_kms->blank_cursor_bo);
170 aspace->mmu->funcs->detach(aspace->mmu,
171 iommu_ports, ARRAY_SIZE(iommu_ports));
172 msm_gem_address_space_put(aspace);
175 if (mdp4_kms->rpm_enabled)
176 pm_runtime_disable(dev);
181 static const struct mdp_kms_funcs kms_funcs = {
183 .hw_init = mdp4_hw_init,
184 .irq_preinstall = mdp4_irq_preinstall,
185 .irq_postinstall = mdp4_irq_postinstall,
186 .irq_uninstall = mdp4_irq_uninstall,
188 .enable_vblank = mdp4_enable_vblank,
189 .disable_vblank = mdp4_disable_vblank,
190 .prepare_commit = mdp4_prepare_commit,
191 .complete_commit = mdp4_complete_commit,
192 .wait_for_crtc_commit_done = mdp4_wait_for_crtc_commit_done,
193 .get_format = mdp_get_format,
194 .round_pixclk = mdp4_round_pixclk,
195 .destroy = mdp4_destroy,
197 .set_irqmask = mdp4_set_irqmask,
200 int mdp4_disable(struct mdp4_kms *mdp4_kms)
204 clk_disable_unprepare(mdp4_kms->clk);
206 clk_disable_unprepare(mdp4_kms->pclk);
207 clk_disable_unprepare(mdp4_kms->lut_clk);
208 if (mdp4_kms->axi_clk)
209 clk_disable_unprepare(mdp4_kms->axi_clk);
214 int mdp4_enable(struct mdp4_kms *mdp4_kms)
218 clk_prepare_enable(mdp4_kms->clk);
220 clk_prepare_enable(mdp4_kms->pclk);
221 clk_prepare_enable(mdp4_kms->lut_clk);
222 if (mdp4_kms->axi_clk)
223 clk_prepare_enable(mdp4_kms->axi_clk);
229 static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms,
232 struct drm_device *dev = mdp4_kms->dev;
233 struct msm_drm_private *priv = dev->dev_private;
234 struct drm_encoder *encoder;
235 struct drm_connector *connector;
236 struct device_node *panel_node;
241 case DRM_MODE_ENCODER_LVDS:
243 * bail out early if there is no panel node (no need to
244 * initialize LCDC encoder and LVDS connector)
246 panel_node = of_graph_get_remote_node(dev->dev->of_node, 0, 0);
250 encoder = mdp4_lcdc_encoder_init(dev, panel_node);
251 if (IS_ERR(encoder)) {
252 dev_err(dev->dev, "failed to construct LCDC encoder\n");
253 return PTR_ERR(encoder);
256 /* LCDC can be hooked to DMA_P (TODO: Add DMA_S later?) */
257 encoder->possible_crtcs = 1 << DMA_P;
259 connector = mdp4_lvds_connector_init(dev, panel_node, encoder);
260 if (IS_ERR(connector)) {
261 dev_err(dev->dev, "failed to initialize LVDS connector\n");
262 return PTR_ERR(connector);
265 priv->encoders[priv->num_encoders++] = encoder;
266 priv->connectors[priv->num_connectors++] = connector;
269 case DRM_MODE_ENCODER_TMDS:
270 encoder = mdp4_dtv_encoder_init(dev);
271 if (IS_ERR(encoder)) {
272 dev_err(dev->dev, "failed to construct DTV encoder\n");
273 return PTR_ERR(encoder);
276 /* DTV can be hooked to DMA_E: */
277 encoder->possible_crtcs = 1 << 1;
280 /* Construct bridge/connector for HDMI: */
281 ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder);
283 dev_err(dev->dev, "failed to initialize HDMI: %d\n", ret);
288 priv->encoders[priv->num_encoders++] = encoder;
291 case DRM_MODE_ENCODER_DSI:
292 /* only DSI1 supported for now */
295 if (!priv->dsi[dsi_id])
298 encoder = mdp4_dsi_encoder_init(dev);
299 if (IS_ERR(encoder)) {
300 ret = PTR_ERR(encoder);
302 "failed to construct DSI encoder: %d\n", ret);
306 /* TODO: Add DMA_S later? */
307 encoder->possible_crtcs = 1 << DMA_P;
308 priv->encoders[priv->num_encoders++] = encoder;
310 ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder);
312 dev_err(dev->dev, "failed to initialize DSI: %d\n",
319 dev_err(dev->dev, "Invalid or unsupported interface\n");
326 static int modeset_init(struct mdp4_kms *mdp4_kms)
328 struct drm_device *dev = mdp4_kms->dev;
329 struct msm_drm_private *priv = dev->dev_private;
330 struct drm_plane *plane;
331 struct drm_crtc *crtc;
333 static const enum mdp4_pipe rgb_planes[] = {
336 static const enum mdp4_pipe vg_planes[] = {
339 static const enum mdp4_dma mdp4_crtcs[] = {
342 static const char * const mdp4_crtc_names[] = {
345 static const int mdp4_intfs[] = {
346 DRM_MODE_ENCODER_LVDS,
347 DRM_MODE_ENCODER_DSI,
348 DRM_MODE_ENCODER_TMDS,
351 /* construct non-private planes: */
352 for (i = 0; i < ARRAY_SIZE(vg_planes); i++) {
353 plane = mdp4_plane_init(dev, vg_planes[i], false);
356 "failed to construct plane for VG%d\n", i + 1);
357 ret = PTR_ERR(plane);
360 priv->planes[priv->num_planes++] = plane;
363 for (i = 0; i < ARRAY_SIZE(mdp4_crtcs); i++) {
364 plane = mdp4_plane_init(dev, rgb_planes[i], true);
367 "failed to construct plane for RGB%d\n", i + 1);
368 ret = PTR_ERR(plane);
372 crtc = mdp4_crtc_init(dev, plane, priv->num_crtcs, i,
375 dev_err(dev->dev, "failed to construct crtc for %s\n",
381 priv->crtcs[priv->num_crtcs++] = crtc;
385 * we currently set up two relatively fixed paths:
387 * LCDC/LVDS path: RGB1 -> DMA_P -> LCDC -> LVDS
389 * DSI path: RGB1 -> DMA_P -> DSI1 -> DSI Panel
391 * DTV/HDMI path: RGB2 -> DMA_E -> DTV -> HDMI
394 for (i = 0; i < ARRAY_SIZE(mdp4_intfs); i++) {
395 ret = mdp4_modeset_init_intf(mdp4_kms, mdp4_intfs[i]);
397 dev_err(dev->dev, "failed to initialize intf: %d, %d\n",
409 struct msm_kms *mdp4_kms_init(struct drm_device *dev)
411 struct platform_device *pdev = to_platform_device(dev->dev);
412 struct mdp4_platform_config *config = mdp4_get_config(pdev);
413 struct mdp4_kms *mdp4_kms;
414 struct msm_kms *kms = NULL;
415 struct msm_gem_address_space *aspace;
418 mdp4_kms = kzalloc(sizeof(*mdp4_kms), GFP_KERNEL);
420 dev_err(dev->dev, "failed to allocate kms\n");
425 mdp_kms_init(&mdp4_kms->base, &kms_funcs);
427 kms = &mdp4_kms->base.base;
431 mdp4_kms->mmio = msm_ioremap(pdev, NULL, "MDP4");
432 if (IS_ERR(mdp4_kms->mmio)) {
433 ret = PTR_ERR(mdp4_kms->mmio);
437 irq = platform_get_irq(pdev, 0);
440 dev_err(dev->dev, "failed to get irq: %d\n", ret);
446 /* NOTE: driver for this regulator still missing upstream.. use
447 * _get_exclusive() and ignore the error if it does not exist
448 * (and hope that the bootloader left it on for us)
450 mdp4_kms->vdd = devm_regulator_get_exclusive(&pdev->dev, "vdd");
451 if (IS_ERR(mdp4_kms->vdd))
452 mdp4_kms->vdd = NULL;
455 ret = regulator_enable(mdp4_kms->vdd);
457 dev_err(dev->dev, "failed to enable regulator vdd: %d\n", ret);
462 mdp4_kms->clk = devm_clk_get(&pdev->dev, "core_clk");
463 if (IS_ERR(mdp4_kms->clk)) {
464 dev_err(dev->dev, "failed to get core_clk\n");
465 ret = PTR_ERR(mdp4_kms->clk);
469 mdp4_kms->pclk = devm_clk_get(&pdev->dev, "iface_clk");
470 if (IS_ERR(mdp4_kms->pclk))
471 mdp4_kms->pclk = NULL;
473 // XXX if (rev >= MDP_REV_42) { ???
474 mdp4_kms->lut_clk = devm_clk_get(&pdev->dev, "lut_clk");
475 if (IS_ERR(mdp4_kms->lut_clk)) {
476 dev_err(dev->dev, "failed to get lut_clk\n");
477 ret = PTR_ERR(mdp4_kms->lut_clk);
481 mdp4_kms->axi_clk = devm_clk_get(&pdev->dev, "bus_clk");
482 if (IS_ERR(mdp4_kms->axi_clk)) {
483 dev_err(dev->dev, "failed to get axi_clk\n");
484 ret = PTR_ERR(mdp4_kms->axi_clk);
488 clk_set_rate(mdp4_kms->clk, config->max_clk);
489 clk_set_rate(mdp4_kms->lut_clk, config->max_clk);
491 pm_runtime_enable(dev->dev);
492 mdp4_kms->rpm_enabled = true;
494 /* make sure things are off before attaching iommu (bootloader could
495 * have left things on, in which case we'll start getting faults if
498 mdp4_enable(mdp4_kms);
499 mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);
500 mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0);
501 mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0);
502 mdp4_disable(mdp4_kms);
506 aspace = msm_gem_address_space_create(&pdev->dev,
507 config->iommu, "mdp4");
508 if (IS_ERR(aspace)) {
509 ret = PTR_ERR(aspace);
513 kms->aspace = aspace;
515 ret = aspace->mmu->funcs->attach(aspace->mmu, iommu_ports,
516 ARRAY_SIZE(iommu_ports));
520 dev_info(dev->dev, "no iommu, fallback to phys "
521 "contig buffers for scanout\n");
525 ret = modeset_init(mdp4_kms);
527 dev_err(dev->dev, "modeset_init failed: %d\n", ret);
531 mdp4_kms->blank_cursor_bo = msm_gem_new(dev, SZ_16K, MSM_BO_WC);
532 if (IS_ERR(mdp4_kms->blank_cursor_bo)) {
533 ret = PTR_ERR(mdp4_kms->blank_cursor_bo);
534 dev_err(dev->dev, "could not allocate blank-cursor bo: %d\n", ret);
535 mdp4_kms->blank_cursor_bo = NULL;
539 ret = msm_gem_get_iova(mdp4_kms->blank_cursor_bo, kms->aspace,
540 &mdp4_kms->blank_cursor_iova);
542 dev_err(dev->dev, "could not pin blank-cursor bo: %d\n", ret);
546 dev->mode_config.min_width = 0;
547 dev->mode_config.min_height = 0;
548 dev->mode_config.max_width = 2048;
549 dev->mode_config.max_height = 2048;
559 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev)
561 static struct mdp4_platform_config config = {};
563 /* TODO: Chips that aren't apq8064 have a 200 Mhz max_clk */
564 config.max_clk = 266667000;
565 config.iommu = iommu_domain_alloc(&platform_bus_type);
567 config.iommu->geometry.aperture_start = 0x1000;
568 config.iommu->geometry.aperture_end = 0xffffffff;