drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h

   1 #ifndef ADRENO_PM4_XML
   2 #define ADRENO_PM4_XML
   3
   4 /* Autogenerated file, DO NOT EDIT manually!
   5
   6 This file was generated by the rules-ng-ng headergen tool in this git repository:
   7 http://github.com/freedreno/envytools/
   8 git clone https://github.com/freedreno/envytools.git
   9
  10 The rules-ng-ng source files this header was generated from are:
  11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    398 bytes, from 2015-09-24 17:25:31)
  12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2016-02-10 17:07:21)
  13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2015-05-20 20:03:14)
  14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  11518 bytes, from 2016-02-10 21:03:25)
  15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  16166 bytes, from 2016-02-11 21:20:31)
  16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83967 bytes, from 2016-02-10 17:07:21)
  17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 109916 bytes, from 2016-02-20 18:44:48)
  18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2015-09-24 17:30:00)
  19
  20 Copyright (C) 2013-2016 by the following authors:
  21 - Rob Clark <robdclark@gmail.com> (robclark)
  22 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
  23
  24 Permission is hereby granted, free of charge, to any person obtaining
  25 a copy of this software and associated documentation files (the
  26 "Software"), to deal in the Software without restriction, including
  27 without limitation the rights to use, copy, modify, merge, publish,
  28 distribute, sublicense, and/or sell copies of the Software, and to
  29 permit persons to whom the Software is furnished to do so, subject to
  30 the following conditions:
  31
  32 The above copyright notice and this permission notice (including the
  33 next paragraph) shall be included in all copies or substantial
  34 portions of the Software.
  35
  36 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  37 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  38 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  39 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  40 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  41 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  42 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  43 */
  44
  45
  46 enum vgt_event_type {
  47         VS_DEALLOC = 0,
  48         PS_DEALLOC = 1,
  49         VS_DONE_TS = 2,
  50         PS_DONE_TS = 3,
  51         CACHE_FLUSH_TS = 4,
  52         CONTEXT_DONE = 5,
  53         CACHE_FLUSH = 6,
  54         HLSQ_FLUSH = 7,
  55         VIZQUERY_START = 7,
  56         VIZQUERY_END = 8,
  57         SC_WAIT_WC = 9,
  58         RST_PIX_CNT = 13,
  59         RST_VTX_CNT = 14,
  60         TILE_FLUSH = 15,
  61         CACHE_FLUSH_AND_INV_TS_EVENT = 20,
  62         ZPASS_DONE = 21,
  63         CACHE_FLUSH_AND_INV_EVENT = 22,
  64         PERFCOUNTER_START = 23,
  65         PERFCOUNTER_STOP = 24,
  66         VS_FETCH_DONE = 27,
  67         FACENESS_FLUSH = 28,
  68 };
  69
  70 enum pc_di_primtype {
  71         DI_PT_NONE = 0,
  72         DI_PT_POINTLIST_PSIZE = 1,
  73         DI_PT_LINELIST = 2,
  74         DI_PT_LINESTRIP = 3,
  75         DI_PT_TRILIST = 4,
  76         DI_PT_TRIFAN = 5,
  77         DI_PT_TRISTRIP = 6,
  78         DI_PT_LINELOOP = 7,
  79         DI_PT_RECTLIST = 8,
  80         DI_PT_POINTLIST = 9,
  81         DI_PT_LINE_ADJ = 10,
  82         DI_PT_LINESTRIP_ADJ = 11,
  83         DI_PT_TRI_ADJ = 12,
  84         DI_PT_TRISTRIP_ADJ = 13,
  85         DI_PT_PATCHES = 34,
  86 };
  87
  88 enum pc_di_src_sel {
  89         DI_SRC_SEL_DMA = 0,
  90         DI_SRC_SEL_IMMEDIATE = 1,
  91         DI_SRC_SEL_AUTO_INDEX = 2,
  92         DI_SRC_SEL_RESERVED = 3,
  93 };
  94
  95 enum pc_di_index_size {
  96         INDEX_SIZE_IGN = 0,
  97         INDEX_SIZE_16_BIT = 0,
  98         INDEX_SIZE_32_BIT = 1,
  99         INDEX_SIZE_8_BIT = 2,
 100         INDEX_SIZE_INVALID = 0,
 101 };
 102
 103 enum pc_di_vis_cull_mode {
 104         IGNORE_VISIBILITY = 0,
 105         USE_VISIBILITY = 1,
 106 };
 107
 108 enum adreno_pm4_packet_type {
 109         CP_TYPE0_PKT = 0,
 110         CP_TYPE1_PKT = 0x40000000,
 111         CP_TYPE2_PKT = 0x80000000,
 112         CP_TYPE3_PKT = 0xc0000000,
 113 };
 114
 115 enum adreno_pm4_type3_packets {
 116         CP_ME_INIT = 72,
 117         CP_NOP = 16,
 118         CP_INDIRECT_BUFFER = 63,
 119         CP_INDIRECT_BUFFER_PFD = 55,
 120         CP_WAIT_FOR_IDLE = 38,
 121         CP_WAIT_REG_MEM = 60,
 122         CP_WAIT_REG_EQ = 82,
 123         CP_WAIT_REG_GTE = 83,
 124         CP_WAIT_UNTIL_READ = 92,
 125         CP_WAIT_IB_PFD_COMPLETE = 93,
 126         CP_REG_RMW = 33,
 127         CP_SET_BIN_DATA = 47,
 128         CP_REG_TO_MEM = 62,
 129         CP_MEM_WRITE = 61,
 130         CP_MEM_WRITE_CNTR = 79,
 131         CP_COND_EXEC = 68,
 132         CP_COND_WRITE = 69,
 133         CP_EVENT_WRITE = 70,
 134         CP_EVENT_WRITE_SHD = 88,
 135         CP_EVENT_WRITE_CFL = 89,
 136         CP_EVENT_WRITE_ZPD = 91,
 137         CP_RUN_OPENCL = 49,
 138         CP_DRAW_INDX = 34,
 139         CP_DRAW_INDX_2 = 54,
 140         CP_DRAW_INDX_BIN = 52,
 141         CP_DRAW_INDX_2_BIN = 53,
 142         CP_VIZ_QUERY = 35,
 143         CP_SET_STATE = 37,
 144         CP_SET_CONSTANT = 45,
 145         CP_IM_LOAD = 39,
 146         CP_IM_LOAD_IMMEDIATE = 43,
 147         CP_LOAD_CONSTANT_CONTEXT = 46,
 148         CP_INVALIDATE_STATE = 59,
 149         CP_SET_SHADER_BASES = 74,
 150         CP_SET_BIN_MASK = 80,
 151         CP_SET_BIN_SELECT = 81,
 152         CP_CONTEXT_UPDATE = 94,
 153         CP_INTERRUPT = 64,
 154         CP_IM_STORE = 44,
 155         CP_SET_DRAW_INIT_FLAGS = 75,
 156         CP_SET_PROTECTED_MODE = 95,
 157         CP_BOOTSTRAP_UCODE = 111,
 158         CP_LOAD_STATE = 48,
 159         CP_COND_INDIRECT_BUFFER_PFE = 58,
 160         CP_COND_INDIRECT_BUFFER_PFD = 50,
 161         CP_INDIRECT_BUFFER_PFE = 63,
 162         CP_SET_BIN = 76,
 163         CP_TEST_TWO_MEMS = 113,
 164         CP_REG_WR_NO_CTXT = 120,
 165         CP_RECORD_PFP_TIMESTAMP = 17,
 166         CP_WAIT_FOR_ME = 19,
 167         CP_SET_DRAW_STATE = 67,
 168         CP_DRAW_INDX_OFFSET = 56,
 169         CP_DRAW_INDIRECT = 40,
 170         CP_DRAW_INDX_INDIRECT = 41,
 171         CP_DRAW_AUTO = 36,
 172         CP_UNKNOWN_19 = 25,
 173         CP_UNKNOWN_1A = 26,
 174         CP_UNKNOWN_4E = 78,
 175         CP_WIDE_REG_WRITE = 116,
 176         CP_SCRATCH_TO_REG = 77,
 177         CP_REG_TO_SCRATCH = 74,
 178         CP_WAIT_MEM_WRITES = 18,
 179         CP_COND_REG_EXEC = 71,
 180         CP_MEM_TO_REG = 66,
 181         IN_IB_PREFETCH_END = 23,
 182         IN_SUBBLK_PREFETCH = 31,
 183         IN_INSTR_PREFETCH = 32,
 184         IN_INSTR_MATCH = 71,
 185         IN_CONST_PREFETCH = 73,
 186         IN_INCR_UPDT_STATE = 85,
 187         IN_INCR_UPDT_CONST = 86,
 188         IN_INCR_UPDT_INSTR = 87,
 189 };
 190
 191 enum adreno_state_block {
 192         SB_VERT_TEX = 0,
 193         SB_VERT_MIPADDR = 1,
 194         SB_FRAG_TEX = 2,
 195         SB_FRAG_MIPADDR = 3,
 196         SB_VERT_SHADER = 4,
 197         SB_GEOM_SHADER = 5,
 198         SB_FRAG_SHADER = 6,
 199 };
 200
 201 enum adreno_state_type {
 202         ST_SHADER = 0,
 203         ST_CONSTANTS = 1,
 204 };
 205
 206 enum adreno_state_src {
 207         SS_DIRECT = 0,
 208         SS_INVALID_ALL_IC = 2,
 209         SS_INVALID_PART_IC = 3,
 210         SS_INDIRECT = 4,
 211         SS_INDIRECT_TCM = 5,
 212         SS_INDIRECT_STM = 6,
 213 };
 214
 215 enum a4xx_index_size {
 216         INDEX4_SIZE_8_BIT = 0,
 217         INDEX4_SIZE_16_BIT = 1,
 218         INDEX4_SIZE_32_BIT = 2,
 219 };
 220
 221 #define REG_CP_LOAD_STATE_0                                     0x00000000
 222 #define CP_LOAD_STATE_0_DST_OFF__MASK                           0x0000ffff
 223 #define CP_LOAD_STATE_0_DST_OFF__SHIFT                          0
 224 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val)
 225 {
 226         return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK;
 227 }
 228 #define CP_LOAD_STATE_0_STATE_SRC__MASK                         0x00070000
 229 #define CP_LOAD_STATE_0_STATE_SRC__SHIFT                        16
 230 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)
 231 {
 232         return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK;
 233 }
 234 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK                       0x00380000
 235 #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT                      19
 236 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)
 237 {
 238         return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;
 239 }
 240 #define CP_LOAD_STATE_0_NUM_UNIT__MASK                          0xffc00000
 241 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT                         22
 242 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)
 243 {
 244         return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK;
 245 }
 246
 247 #define REG_CP_LOAD_STATE_1                                     0x00000001
 248 #define CP_LOAD_STATE_1_STATE_TYPE__MASK                        0x00000003
 249 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT                       0
 250 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)
 251 {
 252         return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK;
 253 }
 254 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK                      0xfffffffc
 255 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT                     2
 256 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
 257 {
 258         return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
 259 }
 260
 261 #define REG_CP_DRAW_INDX_0                                      0x00000000
 262 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK                          0xffffffff
 263 #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT                         0
 264 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)
 265 {
 266         return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;
 267 }
 268
 269 #define REG_CP_DRAW_INDX_1                                      0x00000001
 270 #define CP_DRAW_INDX_1_PRIM_TYPE__MASK                          0x0000003f
 271 #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT                         0
 272 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)
 273 {
 274         return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;
 275 }
 276 #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK                      0x000000c0
 277 #define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT                     6
 278 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)
 279 {
 280         return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;
 281 }
 282 #define CP_DRAW_INDX_1_VIS_CULL__MASK                           0x00000600
 283 #define CP_DRAW_INDX_1_VIS_CULL__SHIFT                          9
 284 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)
 285 {
 286         return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;
 287 }
 288 #define CP_DRAW_INDX_1_INDEX_SIZE__MASK                         0x00000800
 289 #define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT                        11
 290 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)
 291 {
 292         return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;
 293 }
 294 #define CP_DRAW_INDX_1_NOT_EOP                                  0x00001000
 295 #define CP_DRAW_INDX_1_SMALL_INDEX                              0x00002000
 296 #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE                0x00004000
 297 #define CP_DRAW_INDX_1_NUM_INSTANCES__MASK                      0xff000000
 298 #define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT                     24
 299 static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)
 300 {
 301         return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK;
 302 }
 303
 304 #define REG_CP_DRAW_INDX_2                                      0x00000002
 305 #define CP_DRAW_INDX_2_NUM_INDICES__MASK                        0xffffffff
 306 #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT                       0
 307 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)
 308 {
 309         return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;
 310 }
 311
 312 #define REG_CP_DRAW_INDX_3                                      0x00000003
 313 #define CP_DRAW_INDX_3_INDX_BASE__MASK                          0xffffffff
 314 #define CP_DRAW_INDX_3_INDX_BASE__SHIFT                         0
 315 static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val)
 316 {
 317         return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK;
 318 }
 319
 320 #define REG_CP_DRAW_INDX_4                                      0x00000004
 321 #define CP_DRAW_INDX_4_INDX_SIZE__MASK                          0xffffffff
 322 #define CP_DRAW_INDX_4_INDX_SIZE__SHIFT                         0
 323 static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)
 324 {
 325         return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK;
 326 }
 327
 328 #define REG_CP_DRAW_INDX_2_0                                    0x00000000
 329 #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK                        0xffffffff
 330 #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT                       0
 331 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)
 332 {
 333         return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;
 334 }
 335
 336 #define REG_CP_DRAW_INDX_2_1                                    0x00000001
 337 #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK                        0x0000003f
 338 #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT                       0
 339 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)
 340 {
 341         return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;
 342 }
 343 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK                    0x000000c0
 344 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT                   6
 345 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)
 346 {
 347         return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;
 348 }
 349 #define CP_DRAW_INDX_2_1_VIS_CULL__MASK                         0x00000600
 350 #define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT                        9
 351 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)
 352 {
 353         return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;
 354 }
 355 #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK                       0x00000800
 356 #define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT                      11
 357 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)
 358 {
 359         return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;
 360 }
 361 #define CP_DRAW_INDX_2_1_NOT_EOP                                0x00001000
 362 #define CP_DRAW_INDX_2_1_SMALL_INDEX                            0x00002000
 363 #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE              0x00004000
 364 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK                    0xff000000
 365 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT                   24
 366 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)
 367 {
 368         return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK;
 369 }
 370
 371 #define REG_CP_DRAW_INDX_2_2                                    0x00000002
 372 #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK                      0xffffffff
 373 #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT                     0
 374 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)
 375 {
 376         return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;
 377 }
 378
 379 #define REG_CP_DRAW_INDX_OFFSET_0                               0x00000000
 380 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK                   0x0000003f
 381 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT                  0
 382 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)
 383 {
 384         return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;
 385 }
 386 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK               0x000000c0
 387 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT              6
 388 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)
 389 {
 390         return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
 391 }
 392 #define CP_DRAW_INDX_OFFSET_0_TESSELLATE                        0x00000100
 393 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK                  0x00000c00
 394 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT                 10
 395 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)
 396 {
 397         return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
 398 }
 399 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK                   0x01f00000
 400 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT                  20
 401 static inline uint32_t CP_DRAW_INDX_OFFSET_0_TESS_MODE(uint32_t val)
 402 {
 403         return ((val) << CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT) & CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK;
 404 }
 405
 406 #define REG_CP_DRAW_INDX_OFFSET_1                               0x00000001
 407 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK               0xffffffff
 408 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT              0
 409 static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)
 410 {
 411         return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK;
 412 }
 413
 414 #define REG_CP_DRAW_INDX_OFFSET_2                               0x00000002
 415 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK                 0xffffffff
 416 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT                0
 417 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)
 418 {
 419         return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK;
 420 }
 421
 422 #define REG_CP_DRAW_INDX_OFFSET_3                               0x00000003
 423
 424 #define REG_CP_DRAW_INDX_OFFSET_4                               0x00000004
 425 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK                   0xffffffff
 426 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT                  0
 427 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val)
 428 {
 429         return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK;
 430 }
 431
 432 #define REG_CP_DRAW_INDX_OFFSET_5                               0x00000005
 433 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK                   0xffffffff
 434 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT                  0
 435 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)
 436 {
 437         return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK;
 438 }
 439
 440 #define REG_CP_SET_DRAW_STATE_0                                 0x00000000
 441 #define CP_SET_DRAW_STATE_0_COUNT__MASK                         0x0000ffff
 442 #define CP_SET_DRAW_STATE_0_COUNT__SHIFT                        0
 443 static inline uint32_t CP_SET_DRAW_STATE_0_COUNT(uint32_t val)
 444 {
 445         return ((val) << CP_SET_DRAW_STATE_0_COUNT__SHIFT) & CP_SET_DRAW_STATE_0_COUNT__MASK;
 446 }
 447 #define CP_SET_DRAW_STATE_0_DIRTY                               0x00010000
 448 #define CP_SET_DRAW_STATE_0_DISABLE                             0x00020000
 449 #define CP_SET_DRAW_STATE_0_DISABLE_ALL_GROUPS                  0x00040000
 450 #define CP_SET_DRAW_STATE_0_LOAD_IMMED                          0x00080000
 451 #define CP_SET_DRAW_STATE_0_GROUP_ID__MASK                      0x1f000000
 452 #define CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT                     24
 453 static inline uint32_t CP_SET_DRAW_STATE_0_GROUP_ID(uint32_t val)
 454 {
 455         return ((val) << CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE_0_GROUP_ID__MASK;
 456 }
 457
 458 #define REG_CP_SET_DRAW_STATE_1                                 0x00000001
 459 #define CP_SET_DRAW_STATE_1_ADDR__MASK                          0xffffffff
 460 #define CP_SET_DRAW_STATE_1_ADDR__SHIFT                         0
 461 static inline uint32_t CP_SET_DRAW_STATE_1_ADDR(uint32_t val)
 462 {
 463         return ((val) << CP_SET_DRAW_STATE_1_ADDR__SHIFT) & CP_SET_DRAW_STATE_1_ADDR__MASK;
 464 }
 465
 466 #define REG_CP_SET_BIN_0                                        0x00000000
 467
 468 #define REG_CP_SET_BIN_1                                        0x00000001
 469 #define CP_SET_BIN_1_X1__MASK                                   0x0000ffff
 470 #define CP_SET_BIN_1_X1__SHIFT                                  0
 471 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val)
 472 {
 473         return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK;
 474 }
 475 #define CP_SET_BIN_1_Y1__MASK                                   0xffff0000
 476 #define CP_SET_BIN_1_Y1__SHIFT                                  16
 477 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val)
 478 {
 479         return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK;
 480 }
 481
 482 #define REG_CP_SET_BIN_2                                        0x00000002
 483 #define CP_SET_BIN_2_X2__MASK                                   0x0000ffff
 484 #define CP_SET_BIN_2_X2__SHIFT                                  0
 485 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val)
 486 {
 487         return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK;
 488 }
 489 #define CP_SET_BIN_2_Y2__MASK                                   0xffff0000
 490 #define CP_SET_BIN_2_Y2__SHIFT                                  16
 491 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)
 492 {
 493         return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;
 494 }
 495
 496 #define REG_CP_SET_BIN_DATA_0                                   0x00000000
 497 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK                   0xffffffff
 498 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT                  0
 499 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)
 500 {
 501         return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK;
 502 }
 503
 504 #define REG_CP_SET_BIN_DATA_1                                   0x00000001
 505 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK                0xffffffff
 506 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT               0
 507 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
 508 {
 509         return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
 510 }
 511
 512 #define REG_CP_REG_TO_MEM_0                                     0x00000000
 513 #define CP_REG_TO_MEM_0_REG__MASK                               0x0000ffff
 514 #define CP_REG_TO_MEM_0_REG__SHIFT                              0
 515 static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val)
 516 {
 517         return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK;
 518 }
 519 #define CP_REG_TO_MEM_0_CNT__MASK                               0x3ff80000
 520 #define CP_REG_TO_MEM_0_CNT__SHIFT                              19
 521 static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val)
 522 {
 523         return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK;
 524 }
 525 #define CP_REG_TO_MEM_0_64B                                     0x40000000
 526 #define CP_REG_TO_MEM_0_ACCUMULATE                              0x80000000
 527
 528 #define REG_CP_REG_TO_MEM_1                                     0x00000001
 529 #define CP_REG_TO_MEM_1_DEST__MASK                              0xffffffff
 530 #define CP_REG_TO_MEM_1_DEST__SHIFT                             0
 531 static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)
 532 {
 533         return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK;
 534 }
 535
 536
 537 #endif /* ADRENO_PM4_XML */