drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h

   1 #ifndef ADRENO_PM4_XML
   2 #define ADRENO_PM4_XML
   3
   4 /* Autogenerated file, DO NOT EDIT manually!
   5
   6 This file was generated by the rules-ng-ng headergen tool in this git repository:
   7 http://github.com/freedreno/envytools/
   8 git clone https://github.com/freedreno/envytools.git
   9
  10 The rules-ng-ng source files this header was generated from are:
  11 - /home/robclark/src/envytools/rnndb/adreno.xml               (    501 bytes, from 2018-07-03 19:37:13)
  12 - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2018-07-03 19:37:13)
  13 - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml          (  36805 bytes, from 2018-07-03 19:37:13)
  14 - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml (  13634 bytes, from 2018-07-03 19:37:13)
  15 - /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml    (  42393 bytes, from 2018-08-06 18:45:45)
  16 - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2018-07-03 19:37:13)
  17 - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml          ( 112086 bytes, from 2018-07-03 19:37:13)
  18 - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml          ( 147240 bytes, from 2018-08-06 18:45:45)
  19 - /home/robclark/src/envytools/rnndb/adreno/a6xx.xml          ( 101627 bytes, from 2018-08-06 18:45:45)
  20 - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml      (  10431 bytes, from 2018-07-03 19:37:13)
  21 - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2018-07-03 19:37:13)
  22
  23 Copyright (C) 2013-2018 by the following authors:
  24 - Rob Clark <robdclark@gmail.com> (robclark)
  25 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
  26
  27 Permission is hereby granted, free of charge, to any person obtaining
  28 a copy of this software and associated documentation files (the
  29 "Software"), to deal in the Software without restriction, including
  30 without limitation the rights to use, copy, modify, merge, publish,
  31 distribute, sublicense, and/or sell copies of the Software, and to
  32 permit persons to whom the Software is furnished to do so, subject to
  33 the following conditions:
  34
  35 The above copyright notice and this permission notice (including the
  36 next paragraph) shall be included in all copies or substantial
  37 portions of the Software.
  38
  39 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  40 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  41 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  42 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  43 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  44 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  45 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  46 */
  47
  48
  49 enum vgt_event_type {
  50         VS_DEALLOC = 0,
  51         PS_DEALLOC = 1,
  52         VS_DONE_TS = 2,
  53         PS_DONE_TS = 3,
  54         CACHE_FLUSH_TS = 4,
  55         CONTEXT_DONE = 5,
  56         CACHE_FLUSH = 6,
  57         HLSQ_FLUSH = 7,
  58         VIZQUERY_START = 7,
  59         VIZQUERY_END = 8,
  60         SC_WAIT_WC = 9,
  61         RST_PIX_CNT = 13,
  62         RST_VTX_CNT = 14,
  63         TILE_FLUSH = 15,
  64         STAT_EVENT = 16,
  65         CACHE_FLUSH_AND_INV_TS_EVENT = 20,
  66         ZPASS_DONE = 21,
  67         CACHE_FLUSH_AND_INV_EVENT = 22,
  68         PERFCOUNTER_START = 23,
  69         PERFCOUNTER_STOP = 24,
  70         VS_FETCH_DONE = 27,
  71         FACENESS_FLUSH = 28,
  72         FLUSH_SO_0 = 17,
  73         FLUSH_SO_1 = 18,
  74         FLUSH_SO_2 = 19,
  75         FLUSH_SO_3 = 20,
  76         PC_CCU_INVALIDATE_DEPTH = 24,
  77         PC_CCU_INVALIDATE_COLOR = 25,
  78         UNK_1C = 28,
  79         UNK_1D = 29,
  80         BLIT = 30,
  81         UNK_25 = 37,
  82         LRZ_FLUSH = 38,
  83         UNK_2C = 44,
  84         UNK_2D = 45,
  85 };
  86
  87 enum pc_di_primtype {
  88         DI_PT_NONE = 0,
  89         DI_PT_POINTLIST_PSIZE = 1,
  90         DI_PT_LINELIST = 2,
  91         DI_PT_LINESTRIP = 3,
  92         DI_PT_TRILIST = 4,
  93         DI_PT_TRIFAN = 5,
  94         DI_PT_TRISTRIP = 6,
  95         DI_PT_LINELOOP = 7,
  96         DI_PT_RECTLIST = 8,
  97         DI_PT_POINTLIST = 9,
  98         DI_PT_LINE_ADJ = 10,
  99         DI_PT_LINESTRIP_ADJ = 11,
 100         DI_PT_TRI_ADJ = 12,
 101         DI_PT_TRISTRIP_ADJ = 13,
 102 };
 103
 104 enum pc_di_src_sel {
 105         DI_SRC_SEL_DMA = 0,
 106         DI_SRC_SEL_IMMEDIATE = 1,
 107         DI_SRC_SEL_AUTO_INDEX = 2,
 108         DI_SRC_SEL_RESERVED = 3,
 109 };
 110
 111 enum pc_di_index_size {
 112         INDEX_SIZE_IGN = 0,
 113         INDEX_SIZE_16_BIT = 0,
 114         INDEX_SIZE_32_BIT = 1,
 115         INDEX_SIZE_8_BIT = 2,
 116         INDEX_SIZE_INVALID = 0,
 117 };
 118
 119 enum pc_di_vis_cull_mode {
 120         IGNORE_VISIBILITY = 0,
 121         USE_VISIBILITY = 1,
 122 };
 123
 124 enum adreno_pm4_packet_type {
 125         CP_TYPE0_PKT = 0,
 126         CP_TYPE1_PKT = 0x40000000,
 127         CP_TYPE2_PKT = 0x80000000,
 128         CP_TYPE3_PKT = 0xc0000000,
 129         CP_TYPE4_PKT = 0x40000000,
 130         CP_TYPE7_PKT = 0x70000000,
 131 };
 132
 133 enum adreno_pm4_type3_packets {
 134         CP_ME_INIT = 72,
 135         CP_NOP = 16,
 136         CP_PREEMPT_ENABLE = 28,
 137         CP_PREEMPT_TOKEN = 30,
 138         CP_INDIRECT_BUFFER = 63,
 139         CP_INDIRECT_BUFFER_PFD = 55,
 140         CP_WAIT_FOR_IDLE = 38,
 141         CP_WAIT_REG_MEM = 60,
 142         CP_WAIT_REG_EQ = 82,
 143         CP_WAIT_REG_GTE = 83,
 144         CP_WAIT_UNTIL_READ = 92,
 145         CP_WAIT_IB_PFD_COMPLETE = 93,
 146         CP_REG_RMW = 33,
 147         CP_SET_BIN_DATA = 47,
 148         CP_SET_BIN_DATA5 = 47,
 149         CP_REG_TO_MEM = 62,
 150         CP_MEM_WRITE = 61,
 151         CP_MEM_WRITE_CNTR = 79,
 152         CP_COND_EXEC = 68,
 153         CP_COND_WRITE = 69,
 154         CP_COND_WRITE5 = 69,
 155         CP_EVENT_WRITE = 70,
 156         CP_EVENT_WRITE_SHD = 88,
 157         CP_EVENT_WRITE_CFL = 89,
 158         CP_EVENT_WRITE_ZPD = 91,
 159         CP_RUN_OPENCL = 49,
 160         CP_DRAW_INDX = 34,
 161         CP_DRAW_INDX_2 = 54,
 162         CP_DRAW_INDX_BIN = 52,
 163         CP_DRAW_INDX_2_BIN = 53,
 164         CP_VIZ_QUERY = 35,
 165         CP_SET_STATE = 37,
 166         CP_SET_CONSTANT = 45,
 167         CP_IM_LOAD = 39,
 168         CP_IM_LOAD_IMMEDIATE = 43,
 169         CP_LOAD_CONSTANT_CONTEXT = 46,
 170         CP_INVALIDATE_STATE = 59,
 171         CP_SET_SHADER_BASES = 74,
 172         CP_SET_BIN_MASK = 80,
 173         CP_SET_BIN_SELECT = 81,
 174         CP_CONTEXT_UPDATE = 94,
 175         CP_INTERRUPT = 64,
 176         CP_IM_STORE = 44,
 177         CP_SET_DRAW_INIT_FLAGS = 75,
 178         CP_SET_PROTECTED_MODE = 95,
 179         CP_BOOTSTRAP_UCODE = 111,
 180         CP_LOAD_STATE = 48,
 181         CP_LOAD_STATE4 = 48,
 182         CP_COND_INDIRECT_BUFFER_PFE = 58,
 183         CP_COND_INDIRECT_BUFFER_PFD = 50,
 184         CP_INDIRECT_BUFFER_PFE = 63,
 185         CP_SET_BIN = 76,
 186         CP_TEST_TWO_MEMS = 113,
 187         CP_REG_WR_NO_CTXT = 120,
 188         CP_RECORD_PFP_TIMESTAMP = 17,
 189         CP_SET_SECURE_MODE = 102,
 190         CP_WAIT_FOR_ME = 19,
 191         CP_SET_DRAW_STATE = 67,
 192         CP_DRAW_INDX_OFFSET = 56,
 193         CP_DRAW_INDIRECT = 40,
 194         CP_DRAW_INDX_INDIRECT = 41,
 195         CP_DRAW_AUTO = 36,
 196         CP_UNKNOWN_19 = 25,
 197         CP_UNKNOWN_1A = 26,
 198         CP_UNKNOWN_4E = 78,
 199         CP_WIDE_REG_WRITE = 116,
 200         CP_SCRATCH_TO_REG = 77,
 201         CP_REG_TO_SCRATCH = 74,
 202         CP_WAIT_MEM_WRITES = 18,
 203         CP_COND_REG_EXEC = 71,
 204         CP_MEM_TO_REG = 66,
 205         CP_EXEC_CS_INDIRECT = 65,
 206         CP_EXEC_CS = 51,
 207         CP_PERFCOUNTER_ACTION = 80,
 208         CP_SMMU_TABLE_UPDATE = 83,
 209         CP_SET_MARKER = 101,
 210         CP_SET_PSEUDO_REG = 86,
 211         CP_CONTEXT_REG_BUNCH = 92,
 212         CP_YIELD_ENABLE = 28,
 213         CP_SKIP_IB2_ENABLE_GLOBAL = 29,
 214         CP_SKIP_IB2_ENABLE_LOCAL = 35,
 215         CP_SET_SUBDRAW_SIZE = 53,
 216         CP_SET_VISIBILITY_OVERRIDE = 100,
 217         CP_PREEMPT_ENABLE_GLOBAL = 105,
 218         CP_PREEMPT_ENABLE_LOCAL = 106,
 219         CP_CONTEXT_SWITCH_YIELD = 107,
 220         CP_SET_RENDER_MODE = 108,
 221         CP_COMPUTE_CHECKPOINT = 110,
 222         CP_MEM_TO_MEM = 115,
 223         CP_BLIT = 44,
 224         CP_REG_TEST = 57,
 225         CP_SET_MODE = 99,
 226         CP_LOAD_STATE6_GEOM = 50,
 227         CP_LOAD_STATE6_FRAG = 52,
 228         IN_IB_PREFETCH_END = 23,
 229         IN_SUBBLK_PREFETCH = 31,
 230         IN_INSTR_PREFETCH = 32,
 231         IN_INSTR_MATCH = 71,
 232         IN_CONST_PREFETCH = 73,
 233         IN_INCR_UPDT_STATE = 85,
 234         IN_INCR_UPDT_CONST = 86,
 235         IN_INCR_UPDT_INSTR = 87,
 236         PKT4 = 4,
 237         CP_UNK_A6XX_14 = 20,
 238         CP_UNK_A6XX_36 = 54,
 239         CP_UNK_A6XX_55 = 85,
 240         UNK_A6XX_6D = 109,
 241 };
 242
 243 enum adreno_state_block {
 244         SB_VERT_TEX = 0,
 245         SB_VERT_MIPADDR = 1,
 246         SB_FRAG_TEX = 2,
 247         SB_FRAG_MIPADDR = 3,
 248         SB_VERT_SHADER = 4,
 249         SB_GEOM_SHADER = 5,
 250         SB_FRAG_SHADER = 6,
 251         SB_COMPUTE_SHADER = 7,
 252 };
 253
 254 enum adreno_state_type {
 255         ST_SHADER = 0,
 256         ST_CONSTANTS = 1,
 257 };
 258
 259 enum adreno_state_src {
 260         SS_DIRECT = 0,
 261         SS_INVALID_ALL_IC = 2,
 262         SS_INVALID_PART_IC = 3,
 263         SS_INDIRECT = 4,
 264         SS_INDIRECT_TCM = 5,
 265         SS_INDIRECT_STM = 6,
 266 };
 267
 268 enum a4xx_state_block {
 269         SB4_VS_TEX = 0,
 270         SB4_HS_TEX = 1,
 271         SB4_DS_TEX = 2,
 272         SB4_GS_TEX = 3,
 273         SB4_FS_TEX = 4,
 274         SB4_CS_TEX = 5,
 275         SB4_VS_SHADER = 8,
 276         SB4_HS_SHADER = 9,
 277         SB4_DS_SHADER = 10,
 278         SB4_GS_SHADER = 11,
 279         SB4_FS_SHADER = 12,
 280         SB4_CS_SHADER = 13,
 281         SB4_SSBO = 14,
 282         SB4_CS_SSBO = 15,
 283 };
 284
 285 enum a4xx_state_type {
 286         ST4_SHADER = 0,
 287         ST4_CONSTANTS = 1,
 288 };
 289
 290 enum a4xx_state_src {
 291         SS4_DIRECT = 0,
 292         SS4_INDIRECT = 2,
 293 };
 294
 295 enum a6xx_state_block {
 296         SB6_VS_TEX = 0,
 297         SB6_HS_TEX = 1,
 298         SB6_DS_TEX = 2,
 299         SB6_GS_TEX = 3,
 300         SB6_FS_TEX = 4,
 301         SB6_CS_TEX = 5,
 302         SB6_VS_SHADER = 8,
 303         SB6_HS_SHADER = 9,
 304         SB6_DS_SHADER = 10,
 305         SB6_GS_SHADER = 11,
 306         SB6_FS_SHADER = 12,
 307         SB6_CS_SHADER = 13,
 308         SB6_SSBO = 14,
 309         SB6_CS_SSBO = 15,
 310 };
 311
 312 enum a6xx_state_type {
 313         ST6_SHADER = 0,
 314         ST6_CONSTANTS = 1,
 315 };
 316
 317 enum a6xx_state_src {
 318         SS6_DIRECT = 0,
 319         SS6_INDIRECT = 2,
 320 };
 321
 322 enum a4xx_index_size {
 323         INDEX4_SIZE_8_BIT = 0,
 324         INDEX4_SIZE_16_BIT = 1,
 325         INDEX4_SIZE_32_BIT = 2,
 326 };
 327
 328 enum cp_cond_function {
 329         WRITE_ALWAYS = 0,
 330         WRITE_LT = 1,
 331         WRITE_LE = 2,
 332         WRITE_EQ = 3,
 333         WRITE_NE = 4,
 334         WRITE_GE = 5,
 335         WRITE_GT = 6,
 336 };
 337
 338 enum render_mode_cmd {
 339         BYPASS = 1,
 340         BINNING = 2,
 341         GMEM = 3,
 342         BLIT2D = 5,
 343         BLIT2DSCALE = 7,
 344         END2D = 8,
 345 };
 346
 347 enum cp_blit_cmd {
 348         BLIT_OP_FILL = 0,
 349         BLIT_OP_COPY = 1,
 350         BLIT_OP_SCALE = 3,
 351 };
 352
 353 enum a6xx_render_mode {
 354         RM6_BYPASS = 1,
 355         RM6_BINNING = 2,
 356         RM6_GMEM = 4,
 357         RM6_BLIT2D = 5,
 358         RM6_RESOLVE = 6,
 359 };
 360
 361 enum pseudo_reg {
 362         SMMU_INFO = 0,
 363         NON_SECURE_SAVE_ADDR = 1,
 364         SECURE_SAVE_ADDR = 2,
 365         NON_PRIV_SAVE_ADDR = 3,
 366         COUNTER = 4,
 367 };
 368
 369 #define REG_CP_LOAD_STATE_0                                     0x00000000
 370 #define CP_LOAD_STATE_0_DST_OFF__MASK                           0x0000ffff
 371 #define CP_LOAD_STATE_0_DST_OFF__SHIFT                          0
 372 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val)
 373 {
 374         return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK;
 375 }
 376 #define CP_LOAD_STATE_0_STATE_SRC__MASK                         0x00070000
 377 #define CP_LOAD_STATE_0_STATE_SRC__SHIFT                        16
 378 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)
 379 {
 380         return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK;
 381 }
 382 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK                       0x00380000
 383 #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT                      19
 384 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)
 385 {
 386         return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;
 387 }
 388 #define CP_LOAD_STATE_0_NUM_UNIT__MASK                          0xffc00000
 389 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT                         22
 390 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)
 391 {
 392         return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK;
 393 }
 394
 395 #define REG_CP_LOAD_STATE_1                                     0x00000001
 396 #define CP_LOAD_STATE_1_STATE_TYPE__MASK                        0x00000003
 397 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT                       0
 398 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)
 399 {
 400         return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK;
 401 }
 402 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK                      0xfffffffc
 403 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT                     2
 404 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
 405 {
 406         return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
 407 }
 408
 409 #define REG_CP_LOAD_STATE4_0                                    0x00000000
 410 #define CP_LOAD_STATE4_0_DST_OFF__MASK                          0x00003fff
 411 #define CP_LOAD_STATE4_0_DST_OFF__SHIFT                         0
 412 static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val)
 413 {
 414         return ((val) << CP_LOAD_STATE4_0_DST_OFF__SHIFT) & CP_LOAD_STATE4_0_DST_OFF__MASK;
 415 }
 416 #define CP_LOAD_STATE4_0_STATE_SRC__MASK                        0x00030000
 417 #define CP_LOAD_STATE4_0_STATE_SRC__SHIFT                       16
 418 static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val)
 419 {
 420         return ((val) << CP_LOAD_STATE4_0_STATE_SRC__SHIFT) & CP_LOAD_STATE4_0_STATE_SRC__MASK;
 421 }
 422 #define CP_LOAD_STATE4_0_STATE_BLOCK__MASK                      0x003c0000
 423 #define CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT                     18
 424 static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val)
 425 {
 426         return ((val) << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK;
 427 }
 428 #define CP_LOAD_STATE4_0_NUM_UNIT__MASK                         0xffc00000
 429 #define CP_LOAD_STATE4_0_NUM_UNIT__SHIFT                        22
 430 static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val)
 431 {
 432         return ((val) << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE4_0_NUM_UNIT__MASK;
 433 }
 434
 435 #define REG_CP_LOAD_STATE4_1                                    0x00000001
 436 #define CP_LOAD_STATE4_1_STATE_TYPE__MASK                       0x00000003
 437 #define CP_LOAD_STATE4_1_STATE_TYPE__SHIFT                      0
 438 static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val)
 439 {
 440         return ((val) << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE4_1_STATE_TYPE__MASK;
 441 }
 442 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK                     0xfffffffc
 443 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT                    2
 444 static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val)
 445 {
 446         return ((val >> 2) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK;
 447 }
 448
 449 #define REG_CP_LOAD_STATE4_2                                    0x00000002
 450 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK                  0xffffffff
 451 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT                 0
 452 static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val)
 453 {
 454         return ((val) << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK;
 455 }
 456
 457 #define REG_CP_LOAD_STATE6_0                                    0x00000000
 458 #define CP_LOAD_STATE6_0_DST_OFF__MASK                          0x00003fff
 459 #define CP_LOAD_STATE6_0_DST_OFF__SHIFT                         0
 460 static inline uint32_t CP_LOAD_STATE6_0_DST_OFF(uint32_t val)
 461 {
 462         return ((val) << CP_LOAD_STATE6_0_DST_OFF__SHIFT) & CP_LOAD_STATE6_0_DST_OFF__MASK;
 463 }
 464 #define CP_LOAD_STATE6_0_STATE_TYPE__MASK                       0x00004000
 465 #define CP_LOAD_STATE6_0_STATE_TYPE__SHIFT                      14
 466 static inline uint32_t CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val)
 467 {
 468         return ((val) << CP_LOAD_STATE6_0_STATE_TYPE__SHIFT) & CP_LOAD_STATE6_0_STATE_TYPE__MASK;
 469 }
 470 #define CP_LOAD_STATE6_0_STATE_SRC__MASK                        0x00030000
 471 #define CP_LOAD_STATE6_0_STATE_SRC__SHIFT                       16
 472 static inline uint32_t CP_LOAD_STATE6_0_STATE_SRC(enum a6xx_state_src val)
 473 {
 474         return ((val) << CP_LOAD_STATE6_0_STATE_SRC__SHIFT) & CP_LOAD_STATE6_0_STATE_SRC__MASK;
 475 }
 476 #define CP_LOAD_STATE6_0_STATE_BLOCK__MASK                      0x003c0000
 477 #define CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT                     18
 478 static inline uint32_t CP_LOAD_STATE6_0_STATE_BLOCK(enum a6xx_state_block val)
 479 {
 480         return ((val) << CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE6_0_STATE_BLOCK__MASK;
 481 }
 482 #define CP_LOAD_STATE6_0_NUM_UNIT__MASK                         0xffc00000
 483 #define CP_LOAD_STATE6_0_NUM_UNIT__SHIFT                        22
 484 static inline uint32_t CP_LOAD_STATE6_0_NUM_UNIT(uint32_t val)
 485 {
 486         return ((val) << CP_LOAD_STATE6_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE6_0_NUM_UNIT__MASK;
 487 }
 488
 489 #define REG_CP_LOAD_STATE6_1                                    0x00000001
 490 #define CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK                     0xfffffffc
 491 #define CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT                    2
 492 static inline uint32_t CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val)
 493 {
 494         return ((val >> 2) << CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK;
 495 }
 496
 497 #define REG_CP_LOAD_STATE6_2                                    0x00000002
 498 #define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK                  0xffffffff
 499 #define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT                 0
 500 static inline uint32_t CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(uint32_t val)
 501 {
 502         return ((val) << CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK;
 503 }
 504
 505 #define REG_CP_DRAW_INDX_0                                      0x00000000
 506 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK                          0xffffffff
 507 #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT                         0
 508 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)
 509 {
 510         return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;
 511 }
 512
 513 #define REG_CP_DRAW_INDX_1                                      0x00000001
 514 #define CP_DRAW_INDX_1_PRIM_TYPE__MASK                          0x0000003f
 515 #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT                         0
 516 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)
 517 {
 518         return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;
 519 }
 520 #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK                      0x000000c0
 521 #define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT                     6
 522 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)
 523 {
 524         return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;
 525 }
 526 #define CP_DRAW_INDX_1_VIS_CULL__MASK                           0x00000600
 527 #define CP_DRAW_INDX_1_VIS_CULL__SHIFT                          9
 528 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)
 529 {
 530         return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;
 531 }
 532 #define CP_DRAW_INDX_1_INDEX_SIZE__MASK                         0x00000800
 533 #define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT                        11
 534 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)
 535 {
 536         return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;
 537 }
 538 #define CP_DRAW_INDX_1_NOT_EOP                                  0x00001000
 539 #define CP_DRAW_INDX_1_SMALL_INDEX                              0x00002000
 540 #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE                0x00004000
 541 #define CP_DRAW_INDX_1_NUM_INSTANCES__MASK                      0xff000000
 542 #define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT                     24
 543 static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)
 544 {
 545         return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK;
 546 }
 547
 548 #define REG_CP_DRAW_INDX_2                                      0x00000002
 549 #define CP_DRAW_INDX_2_NUM_INDICES__MASK                        0xffffffff
 550 #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT                       0
 551 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)
 552 {
 553         return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;
 554 }
 555
 556 #define REG_CP_DRAW_INDX_3                                      0x00000003
 557 #define CP_DRAW_INDX_3_INDX_BASE__MASK                          0xffffffff
 558 #define CP_DRAW_INDX_3_INDX_BASE__SHIFT                         0
 559 static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val)
 560 {
 561         return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK;
 562 }
 563
 564 #define REG_CP_DRAW_INDX_4                                      0x00000004
 565 #define CP_DRAW_INDX_4_INDX_SIZE__MASK                          0xffffffff
 566 #define CP_DRAW_INDX_4_INDX_SIZE__SHIFT                         0
 567 static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)
 568 {
 569         return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK;
 570 }
 571
 572 #define REG_CP_DRAW_INDX_2_0                                    0x00000000
 573 #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK                        0xffffffff
 574 #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT                       0
 575 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)
 576 {
 577         return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;
 578 }
 579
 580 #define REG_CP_DRAW_INDX_2_1                                    0x00000001
 581 #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK                        0x0000003f
 582 #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT                       0
 583 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)
 584 {
 585         return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;
 586 }
 587 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK                    0x000000c0
 588 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT                   6
 589 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)
 590 {
 591         return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;
 592 }
 593 #define CP_DRAW_INDX_2_1_VIS_CULL__MASK                         0x00000600
 594 #define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT                        9
 595 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)
 596 {
 597         return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;
 598 }
 599 #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK                       0x00000800
 600 #define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT                      11
 601 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)
 602 {
 603         return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;
 604 }
 605 #define CP_DRAW_INDX_2_1_NOT_EOP                                0x00001000
 606 #define CP_DRAW_INDX_2_1_SMALL_INDEX                            0x00002000
 607 #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE              0x00004000
 608 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK                    0xff000000
 609 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT                   24
 610 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)
 611 {
 612         return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK;
 613 }
 614
 615 #define REG_CP_DRAW_INDX_2_2                                    0x00000002
 616 #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK                      0xffffffff
 617 #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT                     0
 618 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)
 619 {
 620         return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;
 621 }
 622
 623 #define REG_CP_DRAW_INDX_OFFSET_0                               0x00000000
 624 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK                   0x0000003f
 625 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT                  0
 626 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)
 627 {
 628         return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;
 629 }
 630 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK               0x000000c0
 631 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT              6
 632 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)
 633 {
 634         return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
 635 }
 636 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK                    0x00000300
 637 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT                   8
 638 static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)
 639 {
 640         return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK;
 641 }
 642 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK                  0x00000c00
 643 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT                 10
 644 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)
 645 {
 646         return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
 647 }
 648 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK                   0x01f00000
 649 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT                  20
 650 static inline uint32_t CP_DRAW_INDX_OFFSET_0_TESS_MODE(uint32_t val)
 651 {
 652         return ((val) << CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT) & CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK;
 653 }
 654
 655 #define REG_CP_DRAW_INDX_OFFSET_1                               0x00000001
 656 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK               0xffffffff
 657 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT              0
 658 static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)
 659 {
 660         return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK;
 661 }
 662
 663 #define REG_CP_DRAW_INDX_OFFSET_2                               0x00000002
 664 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK                 0xffffffff
 665 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT                0
 666 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)
 667 {
 668         return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK;
 669 }
 670
 671 #define REG_CP_DRAW_INDX_OFFSET_3                               0x00000003
 672
 673 #define REG_CP_DRAW_INDX_OFFSET_4                               0x00000004
 674 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK                   0xffffffff
 675 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT                  0
 676 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val)
 677 {
 678         return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK;
 679 }
 680
 681 #define REG_CP_DRAW_INDX_OFFSET_5                               0x00000005
 682 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK                   0xffffffff
 683 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT                  0
 684 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)
 685 {
 686         return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK;
 687 }
 688
 689 #define REG_A4XX_CP_DRAW_INDIRECT_0                             0x00000000
 690 #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK                 0x0000003f
 691 #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT                0
 692 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)
 693 {
 694         return ((val) << A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK;
 695 }
 696 #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK             0x000000c0
 697 #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT            6
 698 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)
 699 {
 700         return ((val) << A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK;
 701 }
 702 #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK                  0x00000300
 703 #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT                 8
 704 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)
 705 {
 706         return ((val) << A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK;
 707 }
 708 #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK                0x00000c00
 709 #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT               10
 710 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)
 711 {
 712         return ((val) << A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK;
 713 }
 714 #define A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__MASK                 0x01f00000
 715 #define A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT                20
 716 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_TESS_MODE(uint32_t val)
 717 {
 718         return ((val) << A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__MASK;
 719 }
 720
 721 #define REG_A4XX_CP_DRAW_INDIRECT_1                             0x00000001
 722 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK                  0xffffffff
 723 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT                 0
 724 static inline uint32_t A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val)
 725 {
 726         return ((val) << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK;
 727 }
 728
 729
 730 #define REG_A5XX_CP_DRAW_INDIRECT_2                             0x00000002
 731 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK               0xffffffff
 732 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT              0
 733 static inline uint32_t A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val)
 734 {
 735         return ((val) << A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK;
 736 }
 737
 738 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_0                        0x00000000
 739 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK            0x0000003f
 740 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT           0
 741 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)
 742 {
 743         return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK;
 744 }
 745 #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK        0x000000c0
 746 #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT       6
 747 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)
 748 {
 749         return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK;
 750 }
 751 #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK             0x00000300
 752 #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT            8
 753 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)
 754 {
 755         return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK;
 756 }
 757 #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK           0x00000c00
 758 #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT          10
 759 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)
 760 {
 761         return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK;
 762 }
 763 #define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__MASK            0x01f00000
 764 #define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT           20
 765 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE(uint32_t val)
 766 {
 767         return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__MASK;
 768 }
 769
 770
 771 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_1                        0x00000001
 772 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK            0xffffffff
 773 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT           0
 774 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val)
 775 {
 776         return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK;
 777 }
 778
 779 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_2                        0x00000002
 780 #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK            0xffffffff
 781 #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT           0
 782 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val)
 783 {
 784         return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK;
 785 }
 786
 787 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_3                        0x00000003
 788 #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK             0xffffffff
 789 #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT            0
 790 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val)
 791 {
 792         return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK;
 793 }
 794
 795
 796 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_1                        0x00000001
 797 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK         0xffffffff
 798 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT        0
 799 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val)
 800 {
 801         return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK;
 802 }
 803
 804 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_2                        0x00000002
 805 #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK         0xffffffff
 806 #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT        0
 807 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val)
 808 {
 809         return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK;
 810 }
 811
 812 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_3                        0x00000003
 813 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK          0xffffffff
 814 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT         0
 815 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val)
 816 {
 817         return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK;
 818 }
 819
 820 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_4                        0x00000004
 821 #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK          0xffffffff
 822 #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT         0
 823 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val)
 824 {
 825         return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK;
 826 }
 827
 828 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_5                        0x00000005
 829 #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK          0xffffffff
 830 #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT         0
 831 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val)
 832 {
 833         return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK;
 834 }
 835
 836 static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
 837
 838 static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
 839 #define CP_SET_DRAW_STATE__0_COUNT__MASK                        0x0000ffff
 840 #define CP_SET_DRAW_STATE__0_COUNT__SHIFT                       0
 841 static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val)
 842 {
 843         return ((val) << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK;
 844 }
 845 #define CP_SET_DRAW_STATE__0_DIRTY                              0x00010000
 846 #define CP_SET_DRAW_STATE__0_DISABLE                            0x00020000
 847 #define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS                 0x00040000
 848 #define CP_SET_DRAW_STATE__0_LOAD_IMMED                         0x00080000
 849 #define CP_SET_DRAW_STATE__0_ENABLE_MASK__MASK                  0x00f00000
 850 #define CP_SET_DRAW_STATE__0_ENABLE_MASK__SHIFT                 20
 851 static inline uint32_t CP_SET_DRAW_STATE__0_ENABLE_MASK(uint32_t val)
 852 {
 853         return ((val) << CP_SET_DRAW_STATE__0_ENABLE_MASK__SHIFT) & CP_SET_DRAW_STATE__0_ENABLE_MASK__MASK;
 854 }
 855 #define CP_SET_DRAW_STATE__0_GROUP_ID__MASK                     0x1f000000
 856 #define CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT                    24
 857 static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val)
 858 {
 859         return ((val) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK;
 860 }
 861
 862 static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
 863 #define CP_SET_DRAW_STATE__1_ADDR_LO__MASK                      0xffffffff
 864 #define CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT                     0
 865 static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val)
 866 {
 867         return ((val) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK;
 868 }
 869
 870 static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
 871 #define CP_SET_DRAW_STATE__2_ADDR_HI__MASK                      0xffffffff
 872 #define CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT                     0
 873 static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val)
 874 {
 875         return ((val) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK;
 876 }
 877
 878 #define REG_CP_SET_BIN_0                                        0x00000000
 879
 880 #define REG_CP_SET_BIN_1                                        0x00000001
 881 #define CP_SET_BIN_1_X1__MASK                                   0x0000ffff
 882 #define CP_SET_BIN_1_X1__SHIFT                                  0
 883 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val)
 884 {
 885         return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK;
 886 }
 887 #define CP_SET_BIN_1_Y1__MASK                                   0xffff0000
 888 #define CP_SET_BIN_1_Y1__SHIFT                                  16
 889 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val)
 890 {
 891         return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK;
 892 }
 893
 894 #define REG_CP_SET_BIN_2                                        0x00000002
 895 #define CP_SET_BIN_2_X2__MASK                                   0x0000ffff
 896 #define CP_SET_BIN_2_X2__SHIFT                                  0
 897 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val)
 898 {
 899         return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK;
 900 }
 901 #define CP_SET_BIN_2_Y2__MASK                                   0xffff0000
 902 #define CP_SET_BIN_2_Y2__SHIFT                                  16
 903 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)
 904 {
 905         return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;
 906 }
 907
 908 #define REG_CP_SET_BIN_DATA_0                                   0x00000000
 909 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK                   0xffffffff
 910 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT                  0
 911 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)
 912 {
 913         return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK;
 914 }
 915
 916 #define REG_CP_SET_BIN_DATA_1                                   0x00000001
 917 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK                0xffffffff
 918 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT               0
 919 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
 920 {
 921         return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
 922 }
 923
 924 #define REG_CP_SET_BIN_DATA5_0                                  0x00000000
 925 #define CP_SET_BIN_DATA5_0_VSC_SIZE__MASK                       0x003f0000
 926 #define CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT                      16
 927 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val)
 928 {
 929         return ((val) << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK;
 930 }
 931 #define CP_SET_BIN_DATA5_0_VSC_N__MASK                          0x07c00000
 932 #define CP_SET_BIN_DATA5_0_VSC_N__SHIFT                         22
 933 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val)
 934 {
 935         return ((val) << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK;
 936 }
 937
 938 #define REG_CP_SET_BIN_DATA5_1                                  0x00000001
 939 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK               0xffffffff
 940 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT              0
 941 static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val)
 942 {
 943         return ((val) << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK;
 944 }
 945
 946 #define REG_CP_SET_BIN_DATA5_2                                  0x00000002
 947 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK               0xffffffff
 948 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT              0
 949 static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val)
 950 {
 951         return ((val) << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK;
 952 }
 953
 954 #define REG_CP_SET_BIN_DATA5_3                                  0x00000003
 955 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK            0xffffffff
 956 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT           0
 957 static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val)
 958 {
 959         return ((val) << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK;
 960 }
 961
 962 #define REG_CP_SET_BIN_DATA5_4                                  0x00000004
 963 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK            0xffffffff
 964 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT           0
 965 static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)
 966 {
 967         return ((val) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK;
 968 }
 969
 970 #define REG_CP_SET_BIN_DATA5_5                                  0x00000005
 971 #define CP_SET_BIN_DATA5_5_XXX_ADDRESS_LO__MASK                 0xffffffff
 972 #define CP_SET_BIN_DATA5_5_XXX_ADDRESS_LO__SHIFT                0
 973 static inline uint32_t CP_SET_BIN_DATA5_5_XXX_ADDRESS_LO(uint32_t val)
 974 {
 975         return ((val) << CP_SET_BIN_DATA5_5_XXX_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_5_XXX_ADDRESS_LO__MASK;
 976 }
 977
 978 #define REG_CP_SET_BIN_DATA5_6                                  0x00000006
 979 #define CP_SET_BIN_DATA5_6_XXX_ADDRESS_HI__MASK                 0xffffffff
 980 #define CP_SET_BIN_DATA5_6_XXX_ADDRESS_HI__SHIFT                0
 981 static inline uint32_t CP_SET_BIN_DATA5_6_XXX_ADDRESS_HI(uint32_t val)
 982 {
 983         return ((val) << CP_SET_BIN_DATA5_6_XXX_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_6_XXX_ADDRESS_HI__MASK;
 984 }
 985
 986 #define REG_CP_REG_TO_MEM_0                                     0x00000000
 987 #define CP_REG_TO_MEM_0_REG__MASK                               0x0000ffff
 988 #define CP_REG_TO_MEM_0_REG__SHIFT                              0
 989 static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val)
 990 {
 991         return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK;
 992 }
 993 #define CP_REG_TO_MEM_0_CNT__MASK                               0x3ff80000
 994 #define CP_REG_TO_MEM_0_CNT__SHIFT                              19
 995 static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val)
 996 {
 997         return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK;
 998 }
 999 #define CP_REG_TO_MEM_0_64B                                     0x40000000
1000 #define CP_REG_TO_MEM_0_ACCUMULATE                              0x80000000
1001
1002 #define REG_CP_REG_TO_MEM_1                                     0x00000001
1003 #define CP_REG_TO_MEM_1_DEST__MASK                              0xffffffff
1004 #define CP_REG_TO_MEM_1_DEST__SHIFT                             0
1005 static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)
1006 {
1007         return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK;
1008 }
1009
1010 #define REG_CP_REG_TO_MEM_2                                     0x00000002
1011 #define CP_REG_TO_MEM_2_DEST_HI__MASK                           0xffffffff
1012 #define CP_REG_TO_MEM_2_DEST_HI__SHIFT                          0
1013 static inline uint32_t CP_REG_TO_MEM_2_DEST_HI(uint32_t val)
1014 {
1015         return ((val) << CP_REG_TO_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_2_DEST_HI__MASK;
1016 }
1017
1018 #define REG_CP_MEM_TO_REG_0                                     0x00000000
1019 #define CP_MEM_TO_REG_0_REG__MASK                               0x0000ffff
1020 #define CP_MEM_TO_REG_0_REG__SHIFT                              0
1021 static inline uint32_t CP_MEM_TO_REG_0_REG(uint32_t val)
1022 {
1023         return ((val) << CP_MEM_TO_REG_0_REG__SHIFT) & CP_MEM_TO_REG_0_REG__MASK;
1024 }
1025 #define CP_MEM_TO_REG_0_CNT__MASK                               0x3ff80000
1026 #define CP_MEM_TO_REG_0_CNT__SHIFT                              19
1027 static inline uint32_t CP_MEM_TO_REG_0_CNT(uint32_t val)
1028 {
1029         return ((val) << CP_MEM_TO_REG_0_CNT__SHIFT) & CP_MEM_TO_REG_0_CNT__MASK;
1030 }
1031 #define CP_MEM_TO_REG_0_64B                                     0x40000000
1032 #define CP_MEM_TO_REG_0_ACCUMULATE                              0x80000000
1033
1034 #define REG_CP_MEM_TO_REG_1                                     0x00000001
1035 #define CP_MEM_TO_REG_1_SRC__MASK                               0xffffffff
1036 #define CP_MEM_TO_REG_1_SRC__SHIFT                              0
1037 static inline uint32_t CP_MEM_TO_REG_1_SRC(uint32_t val)
1038 {
1039         return ((val) << CP_MEM_TO_REG_1_SRC__SHIFT) & CP_MEM_TO_REG_1_SRC__MASK;
1040 }
1041
1042 #define REG_CP_MEM_TO_REG_2                                     0x00000002
1043 #define CP_MEM_TO_REG_2_SRC_HI__MASK                            0xffffffff
1044 #define CP_MEM_TO_REG_2_SRC_HI__SHIFT                           0
1045 static inline uint32_t CP_MEM_TO_REG_2_SRC_HI(uint32_t val)
1046 {
1047         return ((val) << CP_MEM_TO_REG_2_SRC_HI__SHIFT) & CP_MEM_TO_REG_2_SRC_HI__MASK;
1048 }
1049
1050 #define REG_CP_MEM_TO_MEM_0                                     0x00000000
1051 #define CP_MEM_TO_MEM_0_NEG_A                                   0x00000001
1052 #define CP_MEM_TO_MEM_0_NEG_B                                   0x00000002
1053 #define CP_MEM_TO_MEM_0_NEG_C                                   0x00000004
1054 #define CP_MEM_TO_MEM_0_DOUBLE                                  0x20000000
1055
1056 #define REG_CP_COND_WRITE_0                                     0x00000000
1057 #define CP_COND_WRITE_0_FUNCTION__MASK                          0x00000007
1058 #define CP_COND_WRITE_0_FUNCTION__SHIFT                         0
1059 static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val)
1060 {
1061         return ((val) << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK;
1062 }
1063 #define CP_COND_WRITE_0_POLL_MEMORY                             0x00000010
1064 #define CP_COND_WRITE_0_WRITE_MEMORY                            0x00000100
1065
1066 #define REG_CP_COND_WRITE_1                                     0x00000001
1067 #define CP_COND_WRITE_1_POLL_ADDR__MASK                         0xffffffff
1068 #define CP_COND_WRITE_1_POLL_ADDR__SHIFT                        0
1069 static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val)
1070 {
1071         return ((val) << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK;
1072 }
1073
1074 #define REG_CP_COND_WRITE_2                                     0x00000002
1075 #define CP_COND_WRITE_2_REF__MASK                               0xffffffff
1076 #define CP_COND_WRITE_2_REF__SHIFT                              0
1077 static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val)
1078 {
1079         return ((val) << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK;
1080 }
1081
1082 #define REG_CP_COND_WRITE_3                                     0x00000003
1083 #define CP_COND_WRITE_3_MASK__MASK                              0xffffffff
1084 #define CP_COND_WRITE_3_MASK__SHIFT                             0
1085 static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val)
1086 {
1087         return ((val) << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK;
1088 }
1089
1090 #define REG_CP_COND_WRITE_4                                     0x00000004
1091 #define CP_COND_WRITE_4_WRITE_ADDR__MASK                        0xffffffff
1092 #define CP_COND_WRITE_4_WRITE_ADDR__SHIFT                       0
1093 static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val)
1094 {
1095         return ((val) << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK;
1096 }
1097
1098 #define REG_CP_COND_WRITE_5                                     0x00000005
1099 #define CP_COND_WRITE_5_WRITE_DATA__MASK                        0xffffffff
1100 #define CP_COND_WRITE_5_WRITE_DATA__SHIFT                       0
1101 static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val)
1102 {
1103         return ((val) << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK;
1104 }
1105
1106 #define REG_CP_COND_WRITE5_0                                    0x00000000
1107 #define CP_COND_WRITE5_0_FUNCTION__MASK                         0x00000007
1108 #define CP_COND_WRITE5_0_FUNCTION__SHIFT                        0
1109 static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val)
1110 {
1111         return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK;
1112 }
1113 #define CP_COND_WRITE5_0_POLL_MEMORY                            0x00000010
1114 #define CP_COND_WRITE5_0_WRITE_MEMORY                           0x00000100
1115
1116 #define REG_CP_COND_WRITE5_1                                    0x00000001
1117 #define CP_COND_WRITE5_1_POLL_ADDR_LO__MASK                     0xffffffff
1118 #define CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT                    0
1119 static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val)
1120 {
1121         return ((val) << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK;
1122 }
1123
1124 #define REG_CP_COND_WRITE5_2                                    0x00000002
1125 #define CP_COND_WRITE5_2_POLL_ADDR_HI__MASK                     0xffffffff
1126 #define CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT                    0
1127 static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val)
1128 {
1129         return ((val) << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK;
1130 }
1131
1132 #define REG_CP_COND_WRITE5_3                                    0x00000003
1133 #define CP_COND_WRITE5_3_REF__MASK                              0xffffffff
1134 #define CP_COND_WRITE5_3_REF__SHIFT                             0
1135 static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val)
1136 {
1137         return ((val) << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK;
1138 }
1139
1140 #define REG_CP_COND_WRITE5_4                                    0x00000004
1141 #define CP_COND_WRITE5_4_MASK__MASK                             0xffffffff
1142 #define CP_COND_WRITE5_4_MASK__SHIFT                            0
1143 static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val)
1144 {
1145         return ((val) << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK;
1146 }
1147
1148 #define REG_CP_COND_WRITE5_5                                    0x00000005
1149 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK                    0xffffffff
1150 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT                   0
1151 static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val)
1152 {
1153         return ((val) << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK;
1154 }
1155
1156 #define REG_CP_COND_WRITE5_6                                    0x00000006
1157 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK                    0xffffffff
1158 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT                   0
1159 static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val)
1160 {
1161         return ((val) << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK;
1162 }
1163
1164 #define REG_CP_COND_WRITE5_7                                    0x00000007
1165 #define CP_COND_WRITE5_7_WRITE_DATA__MASK                       0xffffffff
1166 #define CP_COND_WRITE5_7_WRITE_DATA__SHIFT                      0
1167 static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val)
1168 {
1169         return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK;
1170 }
1171
1172 #define REG_CP_DISPATCH_COMPUTE_0                               0x00000000
1173
1174 #define REG_CP_DISPATCH_COMPUTE_1                               0x00000001
1175 #define CP_DISPATCH_COMPUTE_1_X__MASK                           0xffffffff
1176 #define CP_DISPATCH_COMPUTE_1_X__SHIFT                          0
1177 static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val)
1178 {
1179         return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK;
1180 }
1181
1182 #define REG_CP_DISPATCH_COMPUTE_2                               0x00000002
1183 #define CP_DISPATCH_COMPUTE_2_Y__MASK                           0xffffffff
1184 #define CP_DISPATCH_COMPUTE_2_Y__SHIFT                          0
1185 static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val)
1186 {
1187         return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK;
1188 }
1189
1190 #define REG_CP_DISPATCH_COMPUTE_3                               0x00000003
1191 #define CP_DISPATCH_COMPUTE_3_Z__MASK                           0xffffffff
1192 #define CP_DISPATCH_COMPUTE_3_Z__SHIFT                          0
1193 static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val)
1194 {
1195         return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK;
1196 }
1197
1198 #define REG_CP_SET_RENDER_MODE_0                                0x00000000
1199 #define CP_SET_RENDER_MODE_0_MODE__MASK                         0x000001ff
1200 #define CP_SET_RENDER_MODE_0_MODE__SHIFT                        0
1201 static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val)
1202 {
1203         return ((val) << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK;
1204 }
1205
1206 #define REG_CP_SET_RENDER_MODE_1                                0x00000001
1207 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK                    0xffffffff
1208 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT                   0
1209 static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val)
1210 {
1211         return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK;
1212 }
1213
1214 #define REG_CP_SET_RENDER_MODE_2                                0x00000002
1215 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK                    0xffffffff
1216 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT                   0
1217 static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)
1218 {
1219         return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK;
1220 }
1221
1222 #define REG_CP_SET_RENDER_MODE_3                                0x00000003
1223 #define CP_SET_RENDER_MODE_3_VSC_ENABLE                         0x00000008
1224 #define CP_SET_RENDER_MODE_3_GMEM_ENABLE                        0x00000010
1225
1226 #define REG_CP_SET_RENDER_MODE_4                                0x00000004
1227
1228 #define REG_CP_SET_RENDER_MODE_5                                0x00000005
1229 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK                   0xffffffff
1230 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT                  0
1231 static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val)
1232 {
1233         return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK;
1234 }
1235
1236 #define REG_CP_SET_RENDER_MODE_6                                0x00000006
1237 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK                    0xffffffff
1238 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT                   0
1239 static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val)
1240 {
1241         return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK;
1242 }
1243
1244 #define REG_CP_SET_RENDER_MODE_7                                0x00000007
1245 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK                    0xffffffff
1246 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT                   0
1247 static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val)
1248 {
1249         return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK;
1250 }
1251
1252 #define REG_CP_COMPUTE_CHECKPOINT_0                             0x00000000
1253 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK                 0xffffffff
1254 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT                0
1255 static inline uint32_t CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val)
1256 {
1257         return ((val) << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK;
1258 }
1259
1260 #define REG_CP_COMPUTE_CHECKPOINT_1                             0x00000001
1261 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK                 0xffffffff
1262 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT                0
1263 static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val)
1264 {
1265         return ((val) << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK;
1266 }
1267
1268 #define REG_CP_COMPUTE_CHECKPOINT_2                             0x00000002
1269
1270 #define REG_CP_COMPUTE_CHECKPOINT_3                             0x00000003
1271 #define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK                0xffffffff
1272 #define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT               0
1273 static inline uint32_t CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN(uint32_t val)
1274 {
1275         return ((val) << CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK;
1276 }
1277
1278 #define REG_CP_COMPUTE_CHECKPOINT_4                             0x00000004
1279
1280 #define REG_CP_COMPUTE_CHECKPOINT_5                             0x00000005
1281 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK                 0xffffffff
1282 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT                0
1283 static inline uint32_t CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val)
1284 {
1285         return ((val) << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK;
1286 }
1287
1288 #define REG_CP_COMPUTE_CHECKPOINT_6                             0x00000006
1289 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK                 0xffffffff
1290 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT                0
1291 static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val)
1292 {
1293         return ((val) << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK;
1294 }
1295
1296 #define REG_CP_COMPUTE_CHECKPOINT_7                             0x00000007
1297
1298 #define REG_CP_PERFCOUNTER_ACTION_0                             0x00000000
1299
1300 #define REG_CP_PERFCOUNTER_ACTION_1                             0x00000001
1301 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK                 0xffffffff
1302 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT                0
1303 static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val)
1304 {
1305         return ((val) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK;
1306 }
1307
1308 #define REG_CP_PERFCOUNTER_ACTION_2                             0x00000002
1309 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK                 0xffffffff
1310 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT                0
1311 static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val)
1312 {
1313         return ((val) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK;
1314 }
1315
1316 #define REG_CP_EVENT_WRITE_0                                    0x00000000
1317 #define CP_EVENT_WRITE_0_EVENT__MASK                            0x000000ff
1318 #define CP_EVENT_WRITE_0_EVENT__SHIFT                           0
1319 static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)
1320 {
1321         return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK;
1322 }
1323 #define CP_EVENT_WRITE_0_TIMESTAMP                              0x40000000
1324
1325 #define REG_CP_EVENT_WRITE_1                                    0x00000001
1326 #define CP_EVENT_WRITE_1_ADDR_0_LO__MASK                        0xffffffff
1327 #define CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT                       0
1328 static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val)
1329 {
1330         return ((val) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK;
1331 }
1332
1333 #define REG_CP_EVENT_WRITE_2                                    0x00000002
1334 #define CP_EVENT_WRITE_2_ADDR_0_HI__MASK                        0xffffffff
1335 #define CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT                       0
1336 static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val)
1337 {
1338         return ((val) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK;
1339 }
1340
1341 #define REG_CP_EVENT_WRITE_3                                    0x00000003
1342
1343 #define REG_CP_BLIT_0                                           0x00000000
1344 #define CP_BLIT_0_OP__MASK                                      0x0000000f
1345 #define CP_BLIT_0_OP__SHIFT                                     0
1346 static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val)
1347 {
1348         return ((val) << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK;
1349 }
1350
1351 #define REG_CP_BLIT_1                                           0x00000001
1352 #define CP_BLIT_1_SRC_X1__MASK                                  0x00003fff
1353 #define CP_BLIT_1_SRC_X1__SHIFT                                 0
1354 static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val)
1355 {
1356         return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK;
1357 }
1358 #define CP_BLIT_1_SRC_Y1__MASK                                  0x3fff0000
1359 #define CP_BLIT_1_SRC_Y1__SHIFT                                 16
1360 static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val)
1361 {
1362         return ((val) << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK;
1363 }
1364
1365 #define REG_CP_BLIT_2                                           0x00000002
1366 #define CP_BLIT_2_SRC_X2__MASK                                  0x00003fff
1367 #define CP_BLIT_2_SRC_X2__SHIFT                                 0
1368 static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val)
1369 {
1370         return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK;
1371 }
1372 #define CP_BLIT_2_SRC_Y2__MASK                                  0x3fff0000
1373 #define CP_BLIT_2_SRC_Y2__SHIFT                                 16
1374 static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val)
1375 {
1376         return ((val) << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK;
1377 }
1378
1379 #define REG_CP_BLIT_3                                           0x00000003
1380 #define CP_BLIT_3_DST_X1__MASK                                  0x00003fff
1381 #define CP_BLIT_3_DST_X1__SHIFT                                 0
1382 static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val)
1383 {
1384         return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK;
1385 }
1386 #define CP_BLIT_3_DST_Y1__MASK                                  0x3fff0000
1387 #define CP_BLIT_3_DST_Y1__SHIFT                                 16
1388 static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val)
1389 {
1390         return ((val) << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK;
1391 }
1392
1393 #define REG_CP_BLIT_4                                           0x00000004
1394 #define CP_BLIT_4_DST_X2__MASK                                  0x00003fff
1395 #define CP_BLIT_4_DST_X2__SHIFT                                 0
1396 static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val)
1397 {
1398         return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK;
1399 }
1400 #define CP_BLIT_4_DST_Y2__MASK                                  0x3fff0000
1401 #define CP_BLIT_4_DST_Y2__SHIFT                                 16
1402 static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val)
1403 {
1404         return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK;
1405 }
1406
1407 #define REG_CP_EXEC_CS_0                                        0x00000000
1408
1409 #define REG_CP_EXEC_CS_1                                        0x00000001
1410 #define CP_EXEC_CS_1_NGROUPS_X__MASK                            0xffffffff
1411 #define CP_EXEC_CS_1_NGROUPS_X__SHIFT                           0
1412 static inline uint32_t CP_EXEC_CS_1_NGROUPS_X(uint32_t val)
1413 {
1414         return ((val) << CP_EXEC_CS_1_NGROUPS_X__SHIFT) & CP_EXEC_CS_1_NGROUPS_X__MASK;
1415 }
1416
1417 #define REG_CP_EXEC_CS_2                                        0x00000002
1418 #define CP_EXEC_CS_2_NGROUPS_Y__MASK                            0xffffffff
1419 #define CP_EXEC_CS_2_NGROUPS_Y__SHIFT                           0
1420 static inline uint32_t CP_EXEC_CS_2_NGROUPS_Y(uint32_t val)
1421 {
1422         return ((val) << CP_EXEC_CS_2_NGROUPS_Y__SHIFT) & CP_EXEC_CS_2_NGROUPS_Y__MASK;
1423 }
1424
1425 #define REG_CP_EXEC_CS_3                                        0x00000003
1426 #define CP_EXEC_CS_3_NGROUPS_Z__MASK                            0xffffffff
1427 #define CP_EXEC_CS_3_NGROUPS_Z__SHIFT                           0
1428 static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val)
1429 {
1430         return ((val) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK;
1431 }
1432
1433 #define REG_A4XX_CP_EXEC_CS_INDIRECT_0                          0x00000000
1434
1435
1436 #define REG_A4XX_CP_EXEC_CS_INDIRECT_1                          0x00000001
1437 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK                   0xffffffff
1438 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT                  0
1439 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val)
1440 {
1441         return ((val) << A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK;
1442 }
1443
1444 #define REG_A4XX_CP_EXEC_CS_INDIRECT_2                          0x00000002
1445 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK             0x00000ffc
1446 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT            2
1447 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val)
1448 {
1449         return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK;
1450 }
1451 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK             0x003ff000
1452 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT            12
1453 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val)
1454 {
1455         return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK;
1456 }
1457 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK             0xffc00000
1458 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT            22
1459 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val)
1460 {
1461         return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK;
1462 }
1463
1464
1465 #define REG_A5XX_CP_EXEC_CS_INDIRECT_1                          0x00000001
1466 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK                0xffffffff
1467 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT               0
1468 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val)
1469 {
1470         return ((val) << A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK;
1471 }
1472
1473 #define REG_A5XX_CP_EXEC_CS_INDIRECT_2                          0x00000002
1474 #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK                0xffffffff
1475 #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT               0
1476 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val)
1477 {
1478         return ((val) << A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK;
1479 }
1480
1481 #define REG_A5XX_CP_EXEC_CS_INDIRECT_3                          0x00000003
1482 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK             0x00000ffc
1483 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT            2
1484 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val)
1485 {
1486         return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK;
1487 }
1488 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK             0x003ff000
1489 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT            12
1490 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val)
1491 {
1492         return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK;
1493 }
1494 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK             0xffc00000
1495 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT            22
1496 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val)
1497 {
1498         return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK;
1499 }
1500
1501 #define REG_A2XX_CP_SET_MARKER_0                                0x00000000
1502 #define A2XX_CP_SET_MARKER_0_MARKER__MASK                       0x0000000f
1503 #define A2XX_CP_SET_MARKER_0_MARKER__SHIFT                      0
1504 static inline uint32_t A2XX_CP_SET_MARKER_0_MARKER(uint32_t val)
1505 {
1506         return ((val) << A2XX_CP_SET_MARKER_0_MARKER__SHIFT) & A2XX_CP_SET_MARKER_0_MARKER__MASK;
1507 }
1508 #define A2XX_CP_SET_MARKER_0_MODE__MASK                         0x0000000f
1509 #define A2XX_CP_SET_MARKER_0_MODE__SHIFT                        0
1510 static inline uint32_t A2XX_CP_SET_MARKER_0_MODE(enum a6xx_render_mode val)
1511 {
1512         return ((val) << A2XX_CP_SET_MARKER_0_MODE__SHIFT) & A2XX_CP_SET_MARKER_0_MODE__MASK;
1513 }
1514 #define A2XX_CP_SET_MARKER_0_IFPC                               0x00000100
1515
1516 static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
1517
1518 static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
1519 #define A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK              0x00000007
1520 #define A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT             0
1521 static inline uint32_t A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val)
1522 {
1523         return ((val) << A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT) & A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK;
1524 }
1525
1526 static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
1527 #define A2XX_CP_SET_PSEUDO_REG__1_LO__MASK                      0xffffffff
1528 #define A2XX_CP_SET_PSEUDO_REG__1_LO__SHIFT                     0
1529 static inline uint32_t A2XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val)
1530 {
1531         return ((val) << A2XX_CP_SET_PSEUDO_REG__1_LO__SHIFT) & A2XX_CP_SET_PSEUDO_REG__1_LO__MASK;
1532 }
1533
1534 static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
1535 #define A2XX_CP_SET_PSEUDO_REG__2_HI__MASK                      0xffffffff
1536 #define A2XX_CP_SET_PSEUDO_REG__2_HI__SHIFT                     0
1537 static inline uint32_t A2XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val)
1538 {
1539         return ((val) << A2XX_CP_SET_PSEUDO_REG__2_HI__SHIFT) & A2XX_CP_SET_PSEUDO_REG__2_HI__MASK;
1540 }
1541
1542 #define REG_A2XX_CP_REG_TEST_0                                  0x00000000
1543 #define A2XX_CP_REG_TEST_0_REG__MASK                            0x00000fff
1544 #define A2XX_CP_REG_TEST_0_REG__SHIFT                           0
1545 static inline uint32_t A2XX_CP_REG_TEST_0_REG(uint32_t val)
1546 {
1547         return ((val) << A2XX_CP_REG_TEST_0_REG__SHIFT) & A2XX_CP_REG_TEST_0_REG__MASK;
1548 }
1549 #define A2XX_CP_REG_TEST_0_BIT__MASK                            0x01f00000
1550 #define A2XX_CP_REG_TEST_0_BIT__SHIFT                           20
1551 static inline uint32_t A2XX_CP_REG_TEST_0_BIT(uint32_t val)
1552 {
1553         return ((val) << A2XX_CP_REG_TEST_0_BIT__SHIFT) & A2XX_CP_REG_TEST_0_BIT__MASK;
1554 }
1555 #define A2XX_CP_REG_TEST_0_UNK25                                0x02000000
1556
1557
1558 #endif /* ADRENO_PM4_XML */