2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
5 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #ifndef __ADRENO_GPU_H__
21 #define __ADRENO_GPU_H__
23 #include <linux/firmware.h>
27 #include "adreno_common.xml.h"
28 #include "adreno_pm4.xml.h"
30 #define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = (_reg) + 1
32 #define REG_ADRENO_SKIP(_offset) [_offset] = REG_SKIP
35 * adreno_regs: List of registers that are used in across all
36 * 3D devices. Each device type has different offset value for the same
37 * register, so an array of register offsets are declared for every device
38 * and are indexed by the enumeration values defined in this enum
41 REG_ADRENO_CP_RB_BASE,
42 REG_ADRENO_CP_RB_BASE_HI,
43 REG_ADRENO_CP_RB_RPTR_ADDR,
44 REG_ADRENO_CP_RB_RPTR_ADDR_HI,
45 REG_ADRENO_CP_RB_RPTR,
46 REG_ADRENO_CP_RB_WPTR,
47 REG_ADRENO_CP_RB_CNTL,
48 REG_ADRENO_REGISTER_MAX,
52 ADRENO_QUIRK_TWO_PASS_USE_WFI = 1,
53 ADRENO_QUIRK_FAULT_DETECT_MASK = 2,
63 #define ADRENO_REV(core, major, minor, patchid) \
64 ((struct adreno_rev){ core, major, minor, patchid })
66 struct adreno_gpu_funcs {
67 struct msm_gpu_funcs base;
68 int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
72 struct adreno_rev rev;
75 const char *pm4fw, *pfpfw;
78 enum adreno_quirks quirks;
79 struct msm_gpu *(*init)(struct drm_device *dev);
83 const struct adreno_info *adreno_info(struct adreno_rev rev);
85 #define rbmemptr(adreno_gpu, member) \
86 ((adreno_gpu)->memptrs_iova + offsetof(struct adreno_rbmemptrs, member))
88 struct adreno_rbmemptrs {
89 volatile uint32_t rptr;
90 volatile uint32_t fence;
95 struct adreno_rev rev;
96 const struct adreno_info *info;
97 uint32_t gmem; /* actual gmem size */
98 uint32_t revn; /* numeric revision name */
99 const struct adreno_gpu_funcs *funcs;
101 /* interesting register offsets to dump: */
102 const unsigned int *registers;
105 const struct firmware *pm4, *pfp;
107 /* ringbuffer rptr/wptr: */
108 // TODO should this be in msm_ringbuffer? I think it would be
109 // different for z180..
110 struct adreno_rbmemptrs *memptrs;
111 struct drm_gem_object *memptrs_bo;
112 uint64_t memptrs_iova;
115 * Register offsets are different between some GPUs.
116 * GPU specific offsets will be exported by GPU specific
117 * code (a3xx_gpu.c) and stored in this common location.
119 const unsigned int *reg_offsets;
121 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
123 /* platform config data (ie. from DT, or pdata) */
124 struct adreno_platform_config {
125 struct adreno_rev rev;
126 uint32_t fast_rate, bus_freq;
127 #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
128 struct msm_bus_scale_pdata *bus_scale_table;
132 #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
134 #define spin_until(X) ({ \
135 int __ret = -ETIMEDOUT; \
136 unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \
142 } while (time_before(jiffies, __t)); \
147 static inline bool adreno_is_a3xx(struct adreno_gpu *gpu)
149 return (gpu->revn >= 300) && (gpu->revn < 400);
152 static inline bool adreno_is_a305(struct adreno_gpu *gpu)
154 return gpu->revn == 305;
157 static inline bool adreno_is_a306(struct adreno_gpu *gpu)
159 /* yes, 307, because a305c is 306 */
160 return gpu->revn == 307;
163 static inline bool adreno_is_a320(struct adreno_gpu *gpu)
165 return gpu->revn == 320;
168 static inline bool adreno_is_a330(struct adreno_gpu *gpu)
170 return gpu->revn == 330;
173 static inline bool adreno_is_a330v2(struct adreno_gpu *gpu)
175 return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
178 static inline bool adreno_is_a4xx(struct adreno_gpu *gpu)
180 return (gpu->revn >= 400) && (gpu->revn < 500);
183 static inline int adreno_is_a420(struct adreno_gpu *gpu)
185 return gpu->revn == 420;
188 static inline int adreno_is_a430(struct adreno_gpu *gpu)
190 return gpu->revn == 430;
193 static inline int adreno_is_a530(struct adreno_gpu *gpu)
195 return gpu->revn == 530;
198 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
199 int adreno_hw_init(struct msm_gpu *gpu);
200 uint32_t adreno_last_fence(struct msm_gpu *gpu);
201 void adreno_recover(struct msm_gpu *gpu);
202 void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
203 struct msm_file_private *ctx);
204 void adreno_flush(struct msm_gpu *gpu);
205 bool adreno_idle(struct msm_gpu *gpu);
206 #ifdef CONFIG_DEBUG_FS
207 void adreno_show(struct msm_gpu *gpu, struct seq_file *m);
209 void adreno_dump_info(struct msm_gpu *gpu);
210 void adreno_dump(struct msm_gpu *gpu);
211 void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords);
213 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
214 struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs);
215 void adreno_gpu_cleanup(struct adreno_gpu *gpu);
218 /* ringbuffer helpers (the parts that are adreno specific) */
221 OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
223 adreno_wait_ring(ring->gpu, cnt+1);
224 OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
229 OUT_PKT2(struct msm_ringbuffer *ring)
231 adreno_wait_ring(ring->gpu, 1);
232 OUT_RING(ring, CP_TYPE2_PKT);
236 OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
238 adreno_wait_ring(ring->gpu, cnt+1);
239 OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
242 static inline u32 PM4_PARITY(u32 val)
244 return (0x9669 >> (0xF & (val ^
245 (val >> 4) ^ (val >> 8) ^ (val >> 12) ^
246 (val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^
250 /* Maximum number of values that can be executed for one opcode */
251 #define TYPE4_MAX_PAYLOAD 127
253 #define PKT4(_reg, _cnt) \
254 (CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \
255 (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27))
258 OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
260 adreno_wait_ring(ring->gpu, cnt + 1);
261 OUT_RING(ring, PKT4(regindx, cnt));
265 OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
267 adreno_wait_ring(ring->gpu, cnt + 1);
268 OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) |
269 ((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23));
273 * adreno_reg_check() - Checks the validity of a register enum
274 * @gpu: Pointer to struct adreno_gpu
275 * @offset_name: The register enum that is checked
277 static inline bool adreno_reg_check(struct adreno_gpu *gpu,
278 enum adreno_regs offset_name)
280 if (offset_name >= REG_ADRENO_REGISTER_MAX ||
281 !gpu->reg_offsets[offset_name]) {
286 * REG_SKIP is a special value that tell us that the register in
287 * question isn't implemented on target but don't trigger a BUG(). This
288 * is used to cleanly implement adreno_gpu_write64() and
289 * adreno_gpu_read64() in a generic fashion
291 if (gpu->reg_offsets[offset_name] == REG_SKIP)
297 static inline u32 adreno_gpu_read(struct adreno_gpu *gpu,
298 enum adreno_regs offset_name)
300 u32 reg = gpu->reg_offsets[offset_name];
302 if(adreno_reg_check(gpu,offset_name))
303 val = gpu_read(&gpu->base, reg - 1);
307 static inline void adreno_gpu_write(struct adreno_gpu *gpu,
308 enum adreno_regs offset_name, u32 data)
310 u32 reg = gpu->reg_offsets[offset_name];
311 if(adreno_reg_check(gpu, offset_name))
312 gpu_write(&gpu->base, reg - 1, data);
315 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
316 struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
317 struct msm_gpu *a5xx_gpu_init(struct drm_device *dev);
319 static inline void adreno_gpu_write64(struct adreno_gpu *gpu,
320 enum adreno_regs lo, enum adreno_regs hi, u64 data)
322 adreno_gpu_write(gpu, lo, lower_32_bits(data));
323 adreno_gpu_write(gpu, hi, upper_32_bits(data));
327 * Given a register and a count, return a value to program into
328 * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
329 * registers starting at _reg.
331 * The register base needs to be a multiple of the length. If it is not, the
332 * hardware will quietly mask off the bits for you and shift the size. For
333 * example, if you intend the protection to start at 0x07 for a length of 4
334 * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might
335 * expose registers you intended to protect!
337 #define ADRENO_PROTECT_RW(_reg, _len) \
338 ((1 << 30) | (1 << 29) | \
339 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
342 * Same as above, but allow reads over the range. For areas of mixed use (such
343 * as performance counters) this allows us to protect a much larger range with a
346 #define ADRENO_PROTECT_RDONLY(_reg, _len) \
348 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
350 #endif /* __ADRENO_GPU_H__ */