drivers/gpu/drm/msm/adreno/adreno_device.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013-2014 Red Hat
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  *
   6  * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
   7  */
   8
   9 #include "adreno_gpu.h"
  10
  11 bool hang_debug = false;
  12 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
  13 module_param_named(hang_debug, hang_debug, bool, 0600);
  14
  15 bool snapshot_debugbus = false;
  16 MODULE_PARM_DESC(snapshot_debugbus, "Include debugbus sections in GPU devcoredump (if not fused off)");
  17 module_param_named(snapshot_debugbus, snapshot_debugbus, bool, 0600);
  18
  19 bool allow_vram_carveout = false;
  20 MODULE_PARM_DESC(allow_vram_carveout, "Allow using VRAM Carveout, in place of IOMMU");
  21 module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600);
  22
  23 static const struct adreno_info gpulist[] = {
  24         {
  25                 .rev   = ADRENO_REV(2, 0, 0, 0),
  26                 .revn  = 200,
  27                 .name  = "A200",
  28                 .fw = {
  29                         [ADRENO_FW_PM4] = "/*(DEBLOBBED)*/",
  30                         [ADRENO_FW_PFP] = "/*(DEBLOBBED)*/",
  31                 },
  32                 .gmem  = SZ_256K,
  33                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
  34                 .init  = a2xx_gpu_init,
  35         }, { /* a200 on i.mx51 has only 128kib gmem */
  36                 .rev   = ADRENO_REV(2, 0, 0, 1),
  37                 .revn  = 201,
  38                 .name  = "A200",
  39                 .fw = {
  40                         [ADRENO_FW_PM4] = "/*(DEBLOBBED)*/",
  41                         [ADRENO_FW_PFP] = "/*(DEBLOBBED)*/",
  42                 },
  43                 .gmem  = SZ_128K,
  44                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
  45                 .init  = a2xx_gpu_init,
  46         }, {
  47                 .rev   = ADRENO_REV(2, 2, 0, ANY_ID),
  48                 .revn  = 220,
  49                 .name  = "A220",
  50                 .fw = {
  51                         [ADRENO_FW_PM4] = "/*(DEBLOBBED)*/",
  52                         [ADRENO_FW_PFP] = "/*(DEBLOBBED)*/",
  53                 },
  54                 .gmem  = SZ_512K,
  55                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
  56                 .init  = a2xx_gpu_init,
  57         }, {
  58                 .rev   = ADRENO_REV(3, 0, 5, ANY_ID),
  59                 .revn  = 305,
  60                 .name  = "A305",
  61                 .fw = {
  62                         [ADRENO_FW_PM4] = "/*(DEBLOBBED)*/",
  63                         [ADRENO_FW_PFP] = "/*(DEBLOBBED)*/",
  64                 },
  65                 .gmem  = SZ_256K,
  66                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
  67                 .init  = a3xx_gpu_init,
  68         }, {
  69                 .rev   = ADRENO_REV(3, 0, 6, 0),
  70                 .revn  = 307,        /* because a305c is revn==306 */
  71                 .name  = "A306",
  72                 .fw = {
  73                         [ADRENO_FW_PM4] = "/*(DEBLOBBED)*/",
  74                         [ADRENO_FW_PFP] = "/*(DEBLOBBED)*/",
  75                 },
  76                 .gmem  = SZ_128K,
  77                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
  78                 .init  = a3xx_gpu_init,
  79         }, {
  80                 .rev   = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
  81                 .revn  = 320,
  82                 .name  = "A320",
  83                 .fw = {
  84                         [ADRENO_FW_PM4] = "/*(DEBLOBBED)*/",
  85                         [ADRENO_FW_PFP] = "/*(DEBLOBBED)*/",
  86                 },
  87                 .gmem  = SZ_512K,
  88                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
  89                 .init  = a3xx_gpu_init,
  90         }, {
  91                 .rev   = ADRENO_REV(3, 3, 0, ANY_ID),
  92                 .revn  = 330,
  93                 .name  = "A330",
  94                 .fw = {
  95                         [ADRENO_FW_PM4] = "/*(DEBLOBBED)*/",
  96                         [ADRENO_FW_PFP] = "/*(DEBLOBBED)*/",
  97                 },
  98                 .gmem  = SZ_1M,
  99                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
 100                 .init  = a3xx_gpu_init,
 101         }, {
 102                 .rev   = ADRENO_REV(4, 0, 5, ANY_ID),
 103                 .revn  = 405,
 104                 .name  = "A405",
 105                 .fw = {
 106                         [ADRENO_FW_PM4] = "/*(DEBLOBBED)*/",
 107                         [ADRENO_FW_PFP] = "/*(DEBLOBBED)*/",
 108                 },
 109                 .gmem  = SZ_256K,
 110                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
 111                 .init  = a4xx_gpu_init,
 112         }, {
 113                 .rev   = ADRENO_REV(4, 2, 0, ANY_ID),
 114                 .revn  = 420,
 115                 .name  = "A420",
 116                 .fw = {
 117                         [ADRENO_FW_PM4] = "/*(DEBLOBBED)*/",
 118                         [ADRENO_FW_PFP] = "/*(DEBLOBBED)*/",
 119                 },
 120                 .gmem  = (SZ_1M + SZ_512K),
 121                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
 122                 .init  = a4xx_gpu_init,
 123         }, {
 124                 .rev   = ADRENO_REV(4, 3, 0, ANY_ID),
 125                 .revn  = 430,
 126                 .name  = "A430",
 127                 .fw = {
 128                         [ADRENO_FW_PM4] = "/*(DEBLOBBED)*/",
 129                         [ADRENO_FW_PFP] = "/*(DEBLOBBED)*/",
 130                 },
 131                 .gmem  = (SZ_1M + SZ_512K),
 132                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
 133                 .init  = a4xx_gpu_init,
 134         }, {
 135                 .rev   = ADRENO_REV(5, 0, 6, ANY_ID),
 136                 .revn = 506,
 137                 .name = "A506",
 138                 .fw = {
 139                         [ADRENO_FW_PM4] = "/*(DEBLOBBED)*/",
 140                         [ADRENO_FW_PFP] = "/*(DEBLOBBED)*/",
 141                 },
 142                 .gmem = (SZ_128K + SZ_8K),
 143                 /*
 144                  * Increase inactive period to 250 to avoid bouncing
 145                  * the GDSC which appears to make it grumpy
 146                  */
 147                 .inactive_period = 250,
 148                 .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
 149                           ADRENO_QUIRK_LMLOADKILL_DISABLE,
 150                 .init = a5xx_gpu_init,
 151                 .zapfw = "/*(DEBLOBBED)*/",
 152         }, {
 153                 .rev   = ADRENO_REV(5, 0, 8, ANY_ID),
 154                 .revn = 508,
 155                 .name = "A508",
 156                 .fw = {
 157                         [ADRENO_FW_PM4] = "/*(DEBLOBBED)*/",
 158                         [ADRENO_FW_PFP] = "/*(DEBLOBBED)*/",
 159                 },
 160                 .gmem = (SZ_128K + SZ_8K),
 161                 /*
 162                  * Increase inactive period to 250 to avoid bouncing
 163                  * the GDSC which appears to make it grumpy
 164                  */
 165                 .inactive_period = 250,
 166                 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
 167                 .init = a5xx_gpu_init,
 168                 .zapfw = "/*(DEBLOBBED)*/",
 169         }, {
 170                 .rev   = ADRENO_REV(5, 0, 9, ANY_ID),
 171                 .revn = 509,
 172                 .name = "A509",
 173                 .fw = {
 174                         [ADRENO_FW_PM4] = "/*(DEBLOBBED)*/",
 175                         [ADRENO_FW_PFP] = "/*(DEBLOBBED)*/",
 176                 },
 177                 .gmem = (SZ_256K + SZ_16K),
 178                 /*
 179                  * Increase inactive period to 250 to avoid bouncing
 180                  * the GDSC which appears to make it grumpy
 181                  */
 182                 .inactive_period = 250,
 183                 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
 184                 .init = a5xx_gpu_init,
 185                 /* Adreno 509 uses the same ZAP as 512 */
 186                 .zapfw = "/*(DEBLOBBED)*/",
 187         }, {
 188                 .rev   = ADRENO_REV(5, 1, 0, ANY_ID),
 189                 .revn = 510,
 190                 .name = "A510",
 191                 .fw = {
 192                         [ADRENO_FW_PM4] = "/*(DEBLOBBED)*/",
 193                         [ADRENO_FW_PFP] = "/*(DEBLOBBED)*/",
 194                 },
 195                 .gmem = SZ_256K,
 196                 /*
 197                  * Increase inactive period to 250 to avoid bouncing
 198                  * the GDSC which appears to make it grumpy
 199                  */
 200                 .inactive_period = 250,
 201                 .init = a5xx_gpu_init,
 202         }, {
 203                 .rev   = ADRENO_REV(5, 1, 2, ANY_ID),
 204                 .revn = 512,
 205                 .name = "A512",
 206                 .fw = {
 207                         [ADRENO_FW_PM4] = "/*(DEBLOBBED)*/",
 208                         [ADRENO_FW_PFP] = "/*(DEBLOBBED)*/",
 209                 },
 210                 .gmem = (SZ_256K + SZ_16K),
 211                 /*
 212                  * Increase inactive period to 250 to avoid bouncing
 213                  * the GDSC which appears to make it grumpy
 214                  */
 215                 .inactive_period = 250,
 216                 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
 217                 .init = a5xx_gpu_init,
 218                 .zapfw = "/*(DEBLOBBED)*/",
 219         }, {
 220                 .rev = ADRENO_REV(5, 3, 0, 2),
 221                 .revn = 530,
 222                 .name = "A530",
 223                 .fw = {
 224                         [ADRENO_FW_PM4] = "/*(DEBLOBBED)*/",
 225                         [ADRENO_FW_PFP] = "/*(DEBLOBBED)*/",
 226                         [ADRENO_FW_GPMU] = "/*(DEBLOBBED)*/",
 227                 },
 228                 .gmem = SZ_1M,
 229                 /*
 230                  * Increase inactive period to 250 to avoid bouncing
 231                  * the GDSC which appears to make it grumpy
 232                  */
 233                 .inactive_period = 250,
 234                 .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
 235                         ADRENO_QUIRK_FAULT_DETECT_MASK,
 236                 .init = a5xx_gpu_init,
 237                 .zapfw = "/*(DEBLOBBED)*/",
 238         }, {
 239                 .rev = ADRENO_REV(5, 4, 0, ANY_ID),
 240                 .revn = 540,
 241                 .name = "A540",
 242                 .fw = {
 243                         [ADRENO_FW_PM4] = "/*(DEBLOBBED)*/",
 244                         [ADRENO_FW_PFP] = "/*(DEBLOBBED)*/",
 245                         [ADRENO_FW_GPMU] = "/*(DEBLOBBED)*/",
 246                 },
 247                 .gmem = SZ_1M,
 248                 /*
 249                  * Increase inactive period to 250 to avoid bouncing
 250                  * the GDSC which appears to make it grumpy
 251                  */
 252                 .inactive_period = 250,
 253                 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
 254                 .init = a5xx_gpu_init,
 255                 .zapfw = "/*(DEBLOBBED)*/",
 256         }, {
 257                 .rev = ADRENO_REV(6, 1, 8, ANY_ID),
 258                 .revn = 618,
 259                 .name = "A618",
 260                 .fw = {
 261                         [ADRENO_FW_SQE] = "/*(DEBLOBBED)*/",
 262                         [ADRENO_FW_GMU] = "/*(DEBLOBBED)*/",
 263                 },
 264                 .gmem = SZ_512K,
 265                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
 266                 .init = a6xx_gpu_init,
 267         }, {
 268                 .rev = ADRENO_REV(6, 3, 0, ANY_ID),
 269                 .revn = 630,
 270                 .name = "A630",
 271                 .fw = {
 272                         [ADRENO_FW_SQE] = "/*(DEBLOBBED)*/",
 273                         [ADRENO_FW_GMU] = "/*(DEBLOBBED)*/",
 274                 },
 275                 .gmem = SZ_1M,
 276                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
 277                 .init = a6xx_gpu_init,
 278                 .zapfw = "/*(DEBLOBBED)*/",
 279                 .hwcg = a630_hwcg,
 280         }, {
 281                 .rev = ADRENO_REV(6, 4, 0, ANY_ID),
 282                 .revn = 640,
 283                 .name = "A640",
 284                 .fw = {
 285                         [ADRENO_FW_SQE] = "/*(DEBLOBBED)*/",
 286                         [ADRENO_FW_GMU] = "/*(DEBLOBBED)*/",
 287                 },
 288                 .gmem = SZ_1M,
 289                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
 290                 .init = a6xx_gpu_init,
 291                 .zapfw = "/*(DEBLOBBED)*/",
 292                 .hwcg = a640_hwcg,
 293         }, {
 294                 .rev = ADRENO_REV(6, 5, 0, ANY_ID),
 295                 .revn = 650,
 296                 .name = "A650",
 297                 .fw = {
 298                         [ADRENO_FW_SQE] = "/*(DEBLOBBED)*/",
 299                         [ADRENO_FW_GMU] = "/*(DEBLOBBED)*/",
 300                 },
 301                 .gmem = SZ_1M + SZ_128K,
 302                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
 303                 .init = a6xx_gpu_init,
 304                 .zapfw = "/*(DEBLOBBED)*/",
 305                 .hwcg = a650_hwcg,
 306         }, {
 307                 .rev = ADRENO_REV(6, 6, 0, ANY_ID),
 308                 .revn = 660,
 309                 .name = "A660",
 310                 .fw = {
 311                         [ADRENO_FW_SQE] = "/*(DEBLOBBED)*/",
 312                         [ADRENO_FW_GMU] = "/*(DEBLOBBED)*/",
 313                 },
 314                 .gmem = SZ_1M + SZ_512K,
 315                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
 316                 .init = a6xx_gpu_init,
 317                 .zapfw = "/*(DEBLOBBED)*/",
 318                 .hwcg = a660_hwcg,
 319         }, {
 320                 .rev = ADRENO_REV(6, 3, 5, ANY_ID),
 321                 .fw = {
 322                         [ADRENO_FW_SQE] = "/*(DEBLOBBED)*/",
 323                         [ADRENO_FW_GMU] = "/*(DEBLOBBED)*/",
 324                 },
 325                 .gmem = SZ_512K,
 326                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
 327                 .init = a6xx_gpu_init,
 328                 .hwcg = a660_hwcg,
 329         }, {
 330                 .rev = ADRENO_REV(6, 8, 0, ANY_ID),
 331                 .revn = 680,
 332                 .name = "A680",
 333                 .fw = {
 334                         [ADRENO_FW_SQE] = "/*(DEBLOBBED)*/",
 335                         [ADRENO_FW_GMU] = "/*(DEBLOBBED)*/",
 336                 },
 337                 .gmem = SZ_2M,
 338                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
 339                 .init = a6xx_gpu_init,
 340                 .zapfw = "/*(DEBLOBBED)*/",
 341                 .hwcg = a640_hwcg,
 342         },
 343 };
 344
 345 /*(DEBLOBBED)*/
 346
 347 static inline bool _rev_match(uint8_t entry, uint8_t id)
 348 {
 349         return (entry == ANY_ID) || (entry == id);
 350 }
 351
 352 bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2)
 353 {
 354
 355         return _rev_match(rev1.core, rev2.core) &&
 356                 _rev_match(rev1.major, rev2.major) &&
 357                 _rev_match(rev1.minor, rev2.minor) &&
 358                 _rev_match(rev1.patchid, rev2.patchid);
 359 }
 360
 361 const struct adreno_info *adreno_info(struct adreno_rev rev)
 362 {
 363         int i;
 364
 365         /* identify gpu: */
 366         for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
 367                 const struct adreno_info *info = &gpulist[i];
 368                 if (adreno_cmp_rev(info->rev, rev))
 369                         return info;
 370         }
 371
 372         return NULL;
 373 }
 374
 375 struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
 376 {
 377         struct msm_drm_private *priv = dev->dev_private;
 378         struct platform_device *pdev = priv->gpu_pdev;
 379         struct msm_gpu *gpu = NULL;
 380         struct adreno_gpu *adreno_gpu;
 381         int ret;
 382
 383         if (pdev)
 384                 gpu = dev_to_gpu(&pdev->dev);
 385
 386         if (!gpu) {
 387                 dev_err_once(dev->dev, "no GPU device was found\n");
 388                 return NULL;
 389         }
 390
 391         adreno_gpu = to_adreno_gpu(gpu);
 392
 393         /*
 394          * The number one reason for HW init to fail is if the firmware isn't
 395          * loaded yet. Try that first and don't bother continuing on
 396          * otherwise
 397          */
 398
 399         ret = adreno_load_fw(adreno_gpu);
 400         if (ret)
 401                 return NULL;
 402
 403         /* Make sure pm runtime is active and reset any previous errors */
 404         pm_runtime_set_active(&pdev->dev);
 405
 406         ret = pm_runtime_get_sync(&pdev->dev);
 407         if (ret < 0) {
 408                 pm_runtime_put_sync(&pdev->dev);
 409                 DRM_DEV_ERROR(dev->dev, "Couldn't power up the GPU: %d\n", ret);
 410                 return NULL;
 411         }
 412
 413         mutex_lock(&gpu->lock);
 414         ret = msm_gpu_hw_init(gpu);
 415         mutex_unlock(&gpu->lock);
 416         pm_runtime_put_autosuspend(&pdev->dev);
 417         if (ret) {
 418                 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret);
 419                 return NULL;
 420         }
 421
 422 #ifdef CONFIG_DEBUG_FS
 423         if (gpu->funcs->debugfs_init) {
 424                 gpu->funcs->debugfs_init(gpu, dev->primary);
 425                 gpu->funcs->debugfs_init(gpu, dev->render);
 426         }
 427 #endif
 428
 429         return gpu;
 430 }
 431
 432 static int find_chipid(struct device *dev, struct adreno_rev *rev)
 433 {
 434         struct device_node *node = dev->of_node;
 435         const char *compat;
 436         int ret;
 437         u32 chipid;
 438
 439         /* first search the compat strings for qcom,adreno-XYZ.W: */
 440         ret = of_property_read_string_index(node, "compatible", 0, &compat);
 441         if (ret == 0) {
 442                 unsigned int r, patch;
 443
 444                 if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 ||
 445                     sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) {
 446                         rev->core = r / 100;
 447                         r %= 100;
 448                         rev->major = r / 10;
 449                         r %= 10;
 450                         rev->minor = r;
 451                         rev->patchid = patch;
 452
 453                         return 0;
 454                 }
 455         }
 456
 457         /* and if that fails, fall back to legacy "qcom,chipid" property: */
 458         ret = of_property_read_u32(node, "qcom,chipid", &chipid);
 459         if (ret) {
 460                 DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret);
 461                 return ret;
 462         }
 463
 464         rev->core = (chipid >> 24) & 0xff;
 465         rev->major = (chipid >> 16) & 0xff;
 466         rev->minor = (chipid >> 8) & 0xff;
 467         rev->patchid = (chipid & 0xff);
 468
 469         dev_warn(dev, "Using legacy qcom,chipid binding!\n");
 470         dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n",
 471                 rev->core, rev->major, rev->minor, rev->patchid);
 472
 473         return 0;
 474 }
 475
 476 static int adreno_bind(struct device *dev, struct device *master, void *data)
 477 {
 478         static struct adreno_platform_config config = {};
 479         const struct adreno_info *info;
 480         struct msm_drm_private *priv = dev_get_drvdata(master);
 481         struct drm_device *drm = priv->dev;
 482         struct msm_gpu *gpu;
 483         int ret;
 484
 485         ret = find_chipid(dev, &config.rev);
 486         if (ret)
 487                 return ret;
 488
 489         dev->platform_data = &config;
 490         priv->gpu_pdev = to_platform_device(dev);
 491
 492         info = adreno_info(config.rev);
 493
 494         if (!info) {
 495                 dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
 496                         config.rev.core, config.rev.major,
 497                         config.rev.minor, config.rev.patchid);
 498                 return -ENXIO;
 499         }
 500
 501         DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major,
 502                 config.rev.minor, config.rev.patchid);
 503
 504         priv->is_a2xx = config.rev.core == 2;
 505         priv->has_cached_coherent = config.rev.core >= 6;
 506
 507         gpu = info->init(drm);
 508         if (IS_ERR(gpu)) {
 509                 dev_warn(drm->dev, "failed to load adreno gpu\n");
 510                 return PTR_ERR(gpu);
 511         }
 512
 513         return 0;
 514 }
 515
 516 static void adreno_unbind(struct device *dev, struct device *master,
 517                 void *data)
 518 {
 519         struct msm_drm_private *priv = dev_get_drvdata(master);
 520         struct msm_gpu *gpu = dev_to_gpu(dev);
 521
 522         pm_runtime_force_suspend(dev);
 523         gpu->funcs->destroy(gpu);
 524
 525         priv->gpu_pdev = NULL;
 526 }
 527
 528 static const struct component_ops a3xx_ops = {
 529                 .bind   = adreno_bind,
 530                 .unbind = adreno_unbind,
 531 };
 532
 533 static void adreno_device_register_headless(void)
 534 {
 535         /* on imx5, we don't have a top-level mdp/dpu node
 536          * this creates a dummy node for the driver for that case
 537          */
 538         struct platform_device_info dummy_info = {
 539                 .parent = NULL,
 540                 .name = "msm",
 541                 .id = -1,
 542                 .res = NULL,
 543                 .num_res = 0,
 544                 .data = NULL,
 545                 .size_data = 0,
 546                 .dma_mask = ~0,
 547         };
 548         platform_device_register_full(&dummy_info);
 549 }
 550
 551 static int adreno_probe(struct platform_device *pdev)
 552 {
 553
 554         int ret;
 555
 556         ret = component_add(&pdev->dev, &a3xx_ops);
 557         if (ret)
 558                 return ret;
 559
 560         if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon"))
 561                 adreno_device_register_headless();
 562
 563         return 0;
 564 }
 565
 566 static int adreno_remove(struct platform_device *pdev)
 567 {
 568         component_del(&pdev->dev, &a3xx_ops);
 569         return 0;
 570 }
 571
 572 static void adreno_shutdown(struct platform_device *pdev)
 573 {
 574         pm_runtime_force_suspend(&pdev->dev);
 575 }
 576
 577 static const struct of_device_id dt_match[] = {
 578         { .compatible = "qcom,adreno" },
 579         { .compatible = "qcom,adreno-3xx" },
 580         /* for compatibility with imx5 gpu: */
 581         { .compatible = "amd,imageon" },
 582         /* for backwards compat w/ downstream kgsl DT files: */
 583         { .compatible = "qcom,kgsl-3d0" },
 584         {}
 585 };
 586
 587 static int adreno_runtime_resume(struct device *dev)
 588 {
 589         struct msm_gpu *gpu = dev_to_gpu(dev);
 590
 591         return gpu->funcs->pm_resume(gpu);
 592 }
 593
 594 static int adreno_runtime_suspend(struct device *dev)
 595 {
 596         struct msm_gpu *gpu = dev_to_gpu(dev);
 597
 598         /*
 599          * We should be holding a runpm ref, which will prevent
 600          * runtime suspend.  In the system suspend path, we've
 601          * already waited for active jobs to complete.
 602          */
 603         WARN_ON_ONCE(gpu->active_submits);
 604
 605         return gpu->funcs->pm_suspend(gpu);
 606 }
 607
 608 static void suspend_scheduler(struct msm_gpu *gpu)
 609 {
 610         int i;
 611
 612         /*
 613          * Shut down the scheduler before we force suspend, so that
 614          * suspend isn't racing with scheduler kthread feeding us
 615          * more work.
 616          *
 617          * Note, we just want to park the thread, and let any jobs
 618          * that are already on the hw queue complete normally, as
 619          * opposed to the drm_sched_stop() path used for handling
 620          * faulting/timed-out jobs.  We can't really cancel any jobs
 621          * already on the hw queue without racing with the GPU.
 622          */
 623         for (i = 0; i < gpu->nr_rings; i++) {
 624                 struct drm_gpu_scheduler *sched = &gpu->rb[i]->sched;
 625                 kthread_park(sched->thread);
 626         }
 627 }
 628
 629 static void resume_scheduler(struct msm_gpu *gpu)
 630 {
 631         int i;
 632
 633         for (i = 0; i < gpu->nr_rings; i++) {
 634                 struct drm_gpu_scheduler *sched = &gpu->rb[i]->sched;
 635                 kthread_unpark(sched->thread);
 636         }
 637 }
 638
 639 static int adreno_system_suspend(struct device *dev)
 640 {
 641         struct msm_gpu *gpu = dev_to_gpu(dev);
 642         int remaining, ret;
 643
 644         suspend_scheduler(gpu);
 645
 646         remaining = wait_event_timeout(gpu->retire_event,
 647                                        gpu->active_submits == 0,
 648                                        msecs_to_jiffies(1000));
 649         if (remaining == 0) {
 650                 dev_err(dev, "Timeout waiting for GPU to suspend\n");
 651                 ret = -EBUSY;
 652                 goto out;
 653         }
 654
 655         ret = pm_runtime_force_suspend(dev);
 656 out:
 657         if (ret)
 658                 resume_scheduler(gpu);
 659
 660         return ret;
 661 }
 662
 663 static int adreno_system_resume(struct device *dev)
 664 {
 665         resume_scheduler(dev_to_gpu(dev));
 666         return pm_runtime_force_resume(dev);
 667 }
 668
 669 static const struct dev_pm_ops adreno_pm_ops = {
 670         SYSTEM_SLEEP_PM_OPS(adreno_system_suspend, adreno_system_resume)
 671         RUNTIME_PM_OPS(adreno_runtime_suspend, adreno_runtime_resume, NULL)
 672 };
 673
 674 static struct platform_driver adreno_driver = {
 675         .probe = adreno_probe,
 676         .remove = adreno_remove,
 677         .shutdown = adreno_shutdown,
 678         .driver = {
 679                 .name = "adreno",
 680                 .of_match_table = dt_match,
 681                 .pm = &adreno_pm_ops,
 682         },
 683 };
 684
 685 void __init adreno_register(void)
 686 {
 687         platform_driver_register(&adreno_driver);
 688 }
 689
 690 void __exit adreno_unregister(void)
 691 {
 692         platform_driver_unregister(&adreno_driver);
 693 }