2 * Copyright (C) 2013-2014 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
5 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/pm_opp.h>
21 #include "adreno_gpu.h"
25 bool hang_debug = false;
26 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
27 module_param_named(hang_debug, hang_debug, bool, 0600);
29 static const struct adreno_info gpulist[] = {
31 .rev = ADRENO_REV(3, 0, 5, ANY_ID),
34 .pm4fw = "/*(DEBLOBBED)*/",
35 .pfpfw = "/*(DEBLOBBED)*/",
37 .init = a3xx_gpu_init,
39 .rev = ADRENO_REV(3, 0, 6, 0),
40 .revn = 307, /* because a305c is revn==306 */
42 .pm4fw = "/*(DEBLOBBED)*/",
43 .pfpfw = "/*(DEBLOBBED)*/",
45 .init = a3xx_gpu_init,
47 .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
50 .pm4fw = "/*(DEBLOBBED)*/",
51 .pfpfw = "/*(DEBLOBBED)*/",
53 .init = a3xx_gpu_init,
55 .rev = ADRENO_REV(3, 3, 0, ANY_ID),
58 .pm4fw = "/*(DEBLOBBED)*/",
59 .pfpfw = "/*(DEBLOBBED)*/",
61 .init = a3xx_gpu_init,
63 .rev = ADRENO_REV(4, 2, 0, ANY_ID),
66 .pm4fw = "/*(DEBLOBBED)*/",
67 .pfpfw = "/*(DEBLOBBED)*/",
68 .gmem = (SZ_1M + SZ_512K),
69 .init = a4xx_gpu_init,
71 .rev = ADRENO_REV(4, 3, 0, ANY_ID),
74 .pm4fw = "/*(DEBLOBBED)*/",
75 .pfpfw = "/*(DEBLOBBED)*/",
76 .gmem = (SZ_1M + SZ_512K),
77 .init = a4xx_gpu_init,
79 .rev = ADRENO_REV(5, 3, 0, 2),
82 .pm4fw = "/*(DEBLOBBED)*/",
83 .pfpfw = "/*(DEBLOBBED)*/",
85 .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
86 ADRENO_QUIRK_FAULT_DETECT_MASK,
87 .init = a5xx_gpu_init,
88 .gpmufw = "/*(DEBLOBBED)*/",
89 .zapfw = "/*(DEBLOBBED)*/",
95 static inline bool _rev_match(uint8_t entry, uint8_t id)
97 return (entry == ANY_ID) || (entry == id);
100 const struct adreno_info *adreno_info(struct adreno_rev rev)
105 for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
106 const struct adreno_info *info = &gpulist[i];
107 if (_rev_match(info->rev.core, rev.core) &&
108 _rev_match(info->rev.major, rev.major) &&
109 _rev_match(info->rev.minor, rev.minor) &&
110 _rev_match(info->rev.patchid, rev.patchid))
117 struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
119 struct msm_drm_private *priv = dev->dev_private;
120 struct platform_device *pdev = priv->gpu_pdev;
121 struct adreno_platform_config *config;
122 struct adreno_rev rev;
123 const struct adreno_info *info;
124 struct msm_gpu *gpu = NULL;
127 dev_err(dev->dev, "no adreno device\n");
131 config = pdev->dev.platform_data;
133 info = adreno_info(config->rev);
136 dev_warn(dev->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
137 rev.core, rev.major, rev.minor, rev.patchid);
141 DBG("Found GPU: %u.%u.%u.%u", rev.core, rev.major,
142 rev.minor, rev.patchid);
144 gpu = info->init(dev);
146 dev_warn(dev->dev, "failed to load adreno gpu\n");
154 pm_runtime_get_sync(&pdev->dev);
155 mutex_lock(&dev->struct_mutex);
156 ret = msm_gpu_hw_init(gpu);
157 mutex_unlock(&dev->struct_mutex);
158 pm_runtime_put_sync(&pdev->dev);
160 dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
161 gpu->funcs->destroy(gpu);
169 static void set_gpu_pdev(struct drm_device *dev,
170 struct platform_device *pdev)
172 struct msm_drm_private *priv = dev->dev_private;
173 priv->gpu_pdev = pdev;
176 static int find_chipid(struct device *dev, u32 *chipid)
178 struct device_node *node = dev->of_node;
182 /* first search the compat strings for qcom,adreno-XYZ.W: */
183 ret = of_property_read_string_index(node, "compatible", 0, &compat);
187 if (sscanf(compat, "qcom,adreno-%u.%u", &rev, &patch) == 2) {
189 *chipid |= (rev / 100) << 24; /* core */
191 *chipid |= (rev / 10) << 16; /* major */
193 *chipid |= rev << 8; /* minor */
200 /* and if that fails, fall back to legacy "qcom,chipid" property: */
201 ret = of_property_read_u32(node, "qcom,chipid", chipid);
205 dev_warn(dev, "Using legacy qcom,chipid binding!\n");
206 dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n",
207 (*chipid >> 24) & 0xff, (*chipid >> 16) & 0xff,
208 (*chipid >> 8) & 0xff, *chipid & 0xff);
213 /* Get legacy powerlevels from qcom,gpu-pwrlevels and populate the opp table */
214 static int adreno_get_legacy_pwrlevels(struct device *dev)
216 struct device_node *child, *node;
219 node = of_get_compatible_child(dev->of_node, "qcom,gpu-pwrlevels");
221 dev_err(dev, "Could not find the GPU powerlevels\n");
225 for_each_child_of_node(node, child) {
228 ret = of_property_read_u32(child, "qcom,gpu-freq", &val);
233 * Skip the intentionally bogus clock value found at the bottom
234 * of most legacy frequency tables
237 dev_pm_opp_add(dev, val, 0);
245 static int adreno_get_pwrlevels(struct device *dev,
246 struct adreno_platform_config *config)
248 unsigned long freq = ULONG_MAX;
249 struct dev_pm_opp *opp;
252 /* You down with OPP? */
253 if (!of_find_property(dev->of_node, "operating-points-v2", NULL))
254 ret = adreno_get_legacy_pwrlevels(dev);
256 ret = dev_pm_opp_of_add_table(dev);
261 /* Find the fastest defined rate */
262 opp = dev_pm_opp_find_freq_floor(dev, &freq);
264 config->fast_rate = dev_pm_opp_get_freq(opp);
266 if (!config->fast_rate) {
268 "Could not find clock rate. Using default\n");
269 /* Pick a suitably safe clock speed for any target */
270 config->fast_rate = 200000000;
276 static int adreno_bind(struct device *dev, struct device *master, void *data)
278 static struct adreno_platform_config config = {};
282 ret = find_chipid(dev, &val);
284 dev_err(dev, "could not find chipid: %d\n", ret);
288 config.rev = ADRENO_REV((val >> 24) & 0xff,
289 (val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff);
291 /* find clock rates: */
292 config.fast_rate = 0;
294 ret = adreno_get_pwrlevels(dev, &config);
298 dev->platform_data = &config;
299 set_gpu_pdev(dev_get_drvdata(master), to_platform_device(dev));
303 static void adreno_unbind(struct device *dev, struct device *master,
306 set_gpu_pdev(dev_get_drvdata(master), NULL);
309 static const struct component_ops a3xx_ops = {
311 .unbind = adreno_unbind,
314 static int adreno_probe(struct platform_device *pdev)
316 return component_add(&pdev->dev, &a3xx_ops);
319 static int adreno_remove(struct platform_device *pdev)
321 component_del(&pdev->dev, &a3xx_ops);
325 static const struct of_device_id dt_match[] = {
326 { .compatible = "qcom,adreno" },
327 { .compatible = "qcom,adreno-3xx" },
328 /* for backwards compat w/ downstream kgsl DT files: */
329 { .compatible = "qcom,kgsl-3d0" },
334 static int adreno_resume(struct device *dev)
336 struct platform_device *pdev = to_platform_device(dev);
337 struct msm_gpu *gpu = platform_get_drvdata(pdev);
339 return gpu->funcs->pm_resume(gpu);
342 static int adreno_suspend(struct device *dev)
344 struct platform_device *pdev = to_platform_device(dev);
345 struct msm_gpu *gpu = platform_get_drvdata(pdev);
347 return gpu->funcs->pm_suspend(gpu);
351 static const struct dev_pm_ops adreno_pm_ops = {
352 SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL)
355 static struct platform_driver adreno_driver = {
356 .probe = adreno_probe,
357 .remove = adreno_remove,
360 .of_match_table = dt_match,
361 .pm = &adreno_pm_ops,
365 void __init adreno_register(void)
367 platform_driver_register(&adreno_driver);
370 void __exit adreno_unregister(void)
372 platform_driver_unregister(&adreno_driver);