2 * Copyright (C) 2013-2014 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
5 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "adreno_gpu.h"
24 bool hang_debug = false;
25 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
26 module_param_named(hang_debug, hang_debug, bool, 0600);
28 static const struct adreno_info gpulist[] = {
30 .rev = ADRENO_REV(3, 0, 5, ANY_ID),
33 .pm4fw = "/*(DEBLOBBED)*/",
34 .pfpfw = "/*(DEBLOBBED)*/",
36 .init = a3xx_gpu_init,
38 .rev = ADRENO_REV(3, 0, 6, 0),
39 .revn = 307, /* because a305c is revn==306 */
41 .pm4fw = "/*(DEBLOBBED)*/",
42 .pfpfw = "/*(DEBLOBBED)*/",
44 .init = a3xx_gpu_init,
46 .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
49 .pm4fw = "/*(DEBLOBBED)*/",
50 .pfpfw = "/*(DEBLOBBED)*/",
52 .init = a3xx_gpu_init,
54 .rev = ADRENO_REV(3, 3, 0, ANY_ID),
57 .pm4fw = "/*(DEBLOBBED)*/",
58 .pfpfw = "/*(DEBLOBBED)*/",
60 .init = a3xx_gpu_init,
62 .rev = ADRENO_REV(4, 2, 0, ANY_ID),
65 .pm4fw = "/*(DEBLOBBED)*/",
66 .pfpfw = "/*(DEBLOBBED)*/",
67 .gmem = (SZ_1M + SZ_512K),
68 .init = a4xx_gpu_init,
70 .rev = ADRENO_REV(4, 3, 0, ANY_ID),
73 .pm4fw = "/*(DEBLOBBED)*/",
74 .pfpfw = "/*(DEBLOBBED)*/",
75 .gmem = (SZ_1M + SZ_512K),
76 .init = a4xx_gpu_init,
82 static inline bool _rev_match(uint8_t entry, uint8_t id)
84 return (entry == ANY_ID) || (entry == id);
87 const struct adreno_info *adreno_info(struct adreno_rev rev)
92 for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
93 const struct adreno_info *info = &gpulist[i];
94 if (_rev_match(info->rev.core, rev.core) &&
95 _rev_match(info->rev.major, rev.major) &&
96 _rev_match(info->rev.minor, rev.minor) &&
97 _rev_match(info->rev.patchid, rev.patchid))
104 struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
106 struct msm_drm_private *priv = dev->dev_private;
107 struct platform_device *pdev = priv->gpu_pdev;
108 struct adreno_platform_config *config;
109 struct adreno_rev rev;
110 const struct adreno_info *info;
111 struct msm_gpu *gpu = NULL;
114 dev_err(dev->dev, "no adreno device\n");
118 config = pdev->dev.platform_data;
120 info = adreno_info(config->rev);
123 dev_warn(dev->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
124 rev.core, rev.major, rev.minor, rev.patchid);
128 DBG("Found GPU: %u.%u.%u.%u", rev.core, rev.major,
129 rev.minor, rev.patchid);
131 gpu = info->init(dev);
133 dev_warn(dev->dev, "failed to load adreno gpu\n");
140 mutex_lock(&dev->struct_mutex);
141 gpu->funcs->pm_resume(gpu);
142 mutex_unlock(&dev->struct_mutex);
143 ret = gpu->funcs->hw_init(gpu);
145 dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
146 gpu->funcs->destroy(gpu);
149 /* give inactive pm a chance to kick in: */
157 static void set_gpu_pdev(struct drm_device *dev,
158 struct platform_device *pdev)
160 struct msm_drm_private *priv = dev->dev_private;
161 priv->gpu_pdev = pdev;
164 static int adreno_bind(struct device *dev, struct device *master, void *data)
166 static struct adreno_platform_config config = {};
167 struct device_node *child, *node = dev->of_node;
171 ret = of_property_read_u32(node, "qcom,chipid", &val);
173 dev_err(dev, "could not find chipid: %d\n", ret);
177 config.rev = ADRENO_REV((val >> 24) & 0xff,
178 (val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff);
180 /* find clock rates: */
181 config.fast_rate = 0;
182 config.slow_rate = ~0;
183 for_each_child_of_node(node, child) {
184 if (of_device_is_compatible(child, "qcom,gpu-pwrlevels")) {
185 struct device_node *pwrlvl;
186 for_each_child_of_node(child, pwrlvl) {
187 ret = of_property_read_u32(pwrlvl, "qcom,gpu-freq", &val);
189 dev_err(dev, "could not find gpu-freq: %d\n", ret);
192 config.fast_rate = max(config.fast_rate, val);
193 config.slow_rate = min(config.slow_rate, val);
198 if (!config.fast_rate) {
199 dev_err(dev, "could not find clk rates\n");
203 dev->platform_data = &config;
204 set_gpu_pdev(dev_get_drvdata(master), to_platform_device(dev));
208 static void adreno_unbind(struct device *dev, struct device *master,
211 set_gpu_pdev(dev_get_drvdata(master), NULL);
214 static const struct component_ops a3xx_ops = {
216 .unbind = adreno_unbind,
219 static int adreno_probe(struct platform_device *pdev)
221 return component_add(&pdev->dev, &a3xx_ops);
224 static int adreno_remove(struct platform_device *pdev)
226 component_del(&pdev->dev, &a3xx_ops);
230 static const struct of_device_id dt_match[] = {
231 { .compatible = "qcom,adreno-3xx" },
232 /* for backwards compat w/ downstream kgsl DT files: */
233 { .compatible = "qcom,kgsl-3d0" },
237 static struct platform_driver adreno_driver = {
238 .probe = adreno_probe,
239 .remove = adreno_remove,
242 .of_match_table = dt_match,
246 void __init adreno_register(void)
248 platform_driver_register(&adreno_driver);
251 void __exit adreno_unregister(void)
253 platform_driver_unregister(&adreno_driver);