1 #ifndef ADRENO_COMMON_XML
2 #define ADRENO_COMMON_XML
4 /* Autogenerated file, DO NOT EDIT manually!
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31866 bytes, from 2017-06-06 18:26:14)
16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 139480 bytes, from 2017-06-16 12:44:39)
19 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
21 Copyright (C) 2013-2017 by the following authors:
22 - Rob Clark <robdclark@gmail.com> (robclark)
23 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
25 Permission is hereby granted, free of charge, to any person obtaining
26 a copy of this software and associated documentation files (the
27 "Software"), to deal in the Software without restriction, including
28 without limitation the rights to use, copy, modify, merge, publish,
29 distribute, sublicense, and/or sell copies of the Software, and to
30 permit persons to whom the Software is furnished to do so, subject to
31 the following conditions:
33 The above copyright notice and this permission notice (including the
34 next paragraph) shall be included in all copies or substantial
35 portions of the Software.
37 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
39 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
40 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
41 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
42 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
43 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
47 enum adreno_pa_su_sc_draw {
50 PC_DRAW_TRIANGLES = 2,
53 enum adreno_compare_func {
64 enum adreno_stencil_op {
68 STENCIL_INCR_CLAMP = 3,
69 STENCIL_DECR_CLAMP = 4,
71 STENCIL_INCR_WRAP = 6,
72 STENCIL_DECR_WRAP = 7,
75 enum adreno_rb_blend_factor {
79 FACTOR_ONE_MINUS_SRC_COLOR = 5,
81 FACTOR_ONE_MINUS_SRC_ALPHA = 7,
83 FACTOR_ONE_MINUS_DST_COLOR = 9,
84 FACTOR_DST_ALPHA = 10,
85 FACTOR_ONE_MINUS_DST_ALPHA = 11,
86 FACTOR_CONSTANT_COLOR = 12,
87 FACTOR_ONE_MINUS_CONSTANT_COLOR = 13,
88 FACTOR_CONSTANT_ALPHA = 14,
89 FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15,
90 FACTOR_SRC_ALPHA_SATURATE = 16,
91 FACTOR_SRC1_COLOR = 20,
92 FACTOR_ONE_MINUS_SRC1_COLOR = 21,
93 FACTOR_SRC1_ALPHA = 22,
94 FACTOR_ONE_MINUS_SRC1_ALPHA = 23,
97 enum adreno_rb_surface_endian {
106 enum adreno_rb_dither_mode {
109 DITHER_IF_ALPHA_OFF = 2,
112 enum adreno_rb_depth_format {
118 enum adreno_rb_copy_control_mode {
121 RB_COPY_DEPTH_STENCIL = 5,
127 ROP_AND_INVERTED = 2,
128 ROP_COPY_INVERTED = 3,
135 ROP_OR_INVERTED = 11,
141 enum a3xx_render_mode {
142 RB_RENDERING_PASS = 0,
148 enum a3xx_msaa_samples {
154 enum a3xx_threadmode {
159 enum a3xx_instrbuffermode {
164 enum a3xx_threadsize {
169 enum a3xx_color_swap {
176 enum a3xx_rb_blend_opcode {
177 BLEND_DST_PLUS_SRC = 0,
178 BLEND_SRC_MINUS_DST = 1,
179 BLEND_DST_MINUS_SRC = 2,
180 BLEND_MIN_DST_SRC = 3,
181 BLEND_MAX_DST_SRC = 4,
184 #define REG_AXXX_CP_RB_BASE 0x000001c0
186 #define REG_AXXX_CP_RB_CNTL 0x000001c1
187 #define AXXX_CP_RB_CNTL_BUFSZ__MASK 0x0000003f
188 #define AXXX_CP_RB_CNTL_BUFSZ__SHIFT 0
189 static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val)
191 return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK;
193 #define AXXX_CP_RB_CNTL_BLKSZ__MASK 0x00003f00
194 #define AXXX_CP_RB_CNTL_BLKSZ__SHIFT 8
195 static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val)
197 return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK;
199 #define AXXX_CP_RB_CNTL_BUF_SWAP__MASK 0x00030000
200 #define AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT 16
201 static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val)
203 return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK;
205 #define AXXX_CP_RB_CNTL_POLL_EN 0x00100000
206 #define AXXX_CP_RB_CNTL_NO_UPDATE 0x08000000
207 #define AXXX_CP_RB_CNTL_RPTR_WR_EN 0x80000000
209 #define REG_AXXX_CP_RB_RPTR_ADDR 0x000001c3
210 #define AXXX_CP_RB_RPTR_ADDR_SWAP__MASK 0x00000003
211 #define AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT 0
212 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val)
214 return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK;
216 #define AXXX_CP_RB_RPTR_ADDR_ADDR__MASK 0xfffffffc
217 #define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT 2
218 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val)
220 return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK;
223 #define REG_AXXX_CP_RB_RPTR 0x000001c4
225 #define REG_AXXX_CP_RB_WPTR 0x000001c5
227 #define REG_AXXX_CP_RB_WPTR_DELAY 0x000001c6
229 #define REG_AXXX_CP_RB_RPTR_WR 0x000001c7
231 #define REG_AXXX_CP_RB_WPTR_BASE 0x000001c8
233 #define REG_AXXX_CP_QUEUE_THRESHOLDS 0x000001d5
234 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK 0x0000000f
235 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT 0
236 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val)
238 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK;
240 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK 0x00000f00
241 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT 8
242 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val)
244 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK;
246 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK 0x000f0000
247 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT 16
248 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val)
250 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK;
253 #define REG_AXXX_CP_MEQ_THRESHOLDS 0x000001d6
254 #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK 0x001f0000
255 #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT 16
256 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val)
258 return ((val) << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK;
260 #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK 0x1f000000
261 #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT 24
262 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val)
264 return ((val) << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK;
267 #define REG_AXXX_CP_CSQ_AVAIL 0x000001d7
268 #define AXXX_CP_CSQ_AVAIL_RING__MASK 0x0000007f
269 #define AXXX_CP_CSQ_AVAIL_RING__SHIFT 0
270 static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val)
272 return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK;
274 #define AXXX_CP_CSQ_AVAIL_IB1__MASK 0x00007f00
275 #define AXXX_CP_CSQ_AVAIL_IB1__SHIFT 8
276 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val)
278 return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK;
280 #define AXXX_CP_CSQ_AVAIL_IB2__MASK 0x007f0000
281 #define AXXX_CP_CSQ_AVAIL_IB2__SHIFT 16
282 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val)
284 return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK;
287 #define REG_AXXX_CP_STQ_AVAIL 0x000001d8
288 #define AXXX_CP_STQ_AVAIL_ST__MASK 0x0000007f
289 #define AXXX_CP_STQ_AVAIL_ST__SHIFT 0
290 static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val)
292 return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK;
295 #define REG_AXXX_CP_MEQ_AVAIL 0x000001d9
296 #define AXXX_CP_MEQ_AVAIL_MEQ__MASK 0x0000001f
297 #define AXXX_CP_MEQ_AVAIL_MEQ__SHIFT 0
298 static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val)
300 return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK;
303 #define REG_AXXX_SCRATCH_UMSK 0x000001dc
304 #define AXXX_SCRATCH_UMSK_UMSK__MASK 0x000000ff
305 #define AXXX_SCRATCH_UMSK_UMSK__SHIFT 0
306 static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val)
308 return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK;
310 #define AXXX_SCRATCH_UMSK_SWAP__MASK 0x00030000
311 #define AXXX_SCRATCH_UMSK_SWAP__SHIFT 16
312 static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val)
314 return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK;
317 #define REG_AXXX_SCRATCH_ADDR 0x000001dd
319 #define REG_AXXX_CP_ME_RDADDR 0x000001ea
321 #define REG_AXXX_CP_STATE_DEBUG_INDEX 0x000001ec
323 #define REG_AXXX_CP_STATE_DEBUG_DATA 0x000001ed
325 #define REG_AXXX_CP_INT_CNTL 0x000001f2
327 #define REG_AXXX_CP_INT_STATUS 0x000001f3
329 #define REG_AXXX_CP_INT_ACK 0x000001f4
331 #define REG_AXXX_CP_ME_CNTL 0x000001f6
332 #define AXXX_CP_ME_CNTL_BUSY 0x20000000
333 #define AXXX_CP_ME_CNTL_HALT 0x10000000
335 #define REG_AXXX_CP_ME_STATUS 0x000001f7
337 #define REG_AXXX_CP_ME_RAM_WADDR 0x000001f8
339 #define REG_AXXX_CP_ME_RAM_RADDR 0x000001f9
341 #define REG_AXXX_CP_ME_RAM_DATA 0x000001fa
343 #define REG_AXXX_CP_DEBUG 0x000001fc
344 #define AXXX_CP_DEBUG_PREDICATE_DISABLE 0x00800000
345 #define AXXX_CP_DEBUG_PROG_END_PTR_ENABLE 0x01000000
346 #define AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE 0x02000000
347 #define AXXX_CP_DEBUG_PREFETCH_PASS_NOPS 0x04000000
348 #define AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE 0x08000000
349 #define AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE 0x10000000
350 #define AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL 0x40000000
351 #define AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE 0x80000000
353 #define REG_AXXX_CP_CSQ_RB_STAT 0x000001fd
354 #define AXXX_CP_CSQ_RB_STAT_RPTR__MASK 0x0000007f
355 #define AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT 0
356 static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val)
358 return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK;
360 #define AXXX_CP_CSQ_RB_STAT_WPTR__MASK 0x007f0000
361 #define AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT 16
362 static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val)
364 return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK;
367 #define REG_AXXX_CP_CSQ_IB1_STAT 0x000001fe
368 #define AXXX_CP_CSQ_IB1_STAT_RPTR__MASK 0x0000007f
369 #define AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT 0
370 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val)
372 return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK;
374 #define AXXX_CP_CSQ_IB1_STAT_WPTR__MASK 0x007f0000
375 #define AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT 16
376 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val)
378 return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK;
381 #define REG_AXXX_CP_CSQ_IB2_STAT 0x000001ff
382 #define AXXX_CP_CSQ_IB2_STAT_RPTR__MASK 0x0000007f
383 #define AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT 0
384 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val)
386 return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK;
388 #define AXXX_CP_CSQ_IB2_STAT_WPTR__MASK 0x007f0000
389 #define AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT 16
390 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)
392 return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK;
395 #define REG_AXXX_CP_NON_PREFETCH_CNTRS 0x00000440
397 #define REG_AXXX_CP_STQ_ST_STAT 0x00000443
399 #define REG_AXXX_CP_ST_BASE 0x0000044d
401 #define REG_AXXX_CP_ST_BUFSZ 0x0000044e
403 #define REG_AXXX_CP_MEQ_STAT 0x0000044f
405 #define REG_AXXX_CP_MIU_TAG_STAT 0x00000452
407 #define REG_AXXX_CP_BIN_MASK_LO 0x00000454
409 #define REG_AXXX_CP_BIN_MASK_HI 0x00000455
411 #define REG_AXXX_CP_BIN_SELECT_LO 0x00000456
413 #define REG_AXXX_CP_BIN_SELECT_HI 0x00000457
415 #define REG_AXXX_CP_IB1_BASE 0x00000458
417 #define REG_AXXX_CP_IB1_BUFSZ 0x00000459
419 #define REG_AXXX_CP_IB2_BASE 0x0000045a
421 #define REG_AXXX_CP_IB2_BUFSZ 0x0000045b
423 #define REG_AXXX_CP_STAT 0x0000047f
424 #define AXXX_CP_STAT_CP_BUSY 0x80000000
425 #define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY 0x40000000
426 #define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY 0x20000000
427 #define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY 0x10000000
428 #define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY 0x08000000
429 #define AXXX_CP_STAT_ME_BUSY 0x04000000
430 #define AXXX_CP_STAT_MIU_WR_C_BUSY 0x02000000
431 #define AXXX_CP_STAT_CP_3D_BUSY 0x00800000
432 #define AXXX_CP_STAT_CP_NRT_BUSY 0x00400000
433 #define AXXX_CP_STAT_RBIU_SCRATCH_BUSY 0x00200000
434 #define AXXX_CP_STAT_RCIU_ME_BUSY 0x00100000
435 #define AXXX_CP_STAT_RCIU_PFP_BUSY 0x00080000
436 #define AXXX_CP_STAT_MEQ_RING_BUSY 0x00040000
437 #define AXXX_CP_STAT_PFP_BUSY 0x00020000
438 #define AXXX_CP_STAT_ST_QUEUE_BUSY 0x00010000
439 #define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY 0x00002000
440 #define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY 0x00001000
441 #define AXXX_CP_STAT_RING_QUEUE_BUSY 0x00000800
442 #define AXXX_CP_STAT_CSF_BUSY 0x00000400
443 #define AXXX_CP_STAT_CSF_ST_BUSY 0x00000200
444 #define AXXX_CP_STAT_EVENT_BUSY 0x00000100
445 #define AXXX_CP_STAT_CSF_INDIRECT2_BUSY 0x00000080
446 #define AXXX_CP_STAT_CSF_INDIRECTS_BUSY 0x00000040
447 #define AXXX_CP_STAT_CSF_RING_BUSY 0x00000020
448 #define AXXX_CP_STAT_RCIU_BUSY 0x00000010
449 #define AXXX_CP_STAT_RBIU_BUSY 0x00000008
450 #define AXXX_CP_STAT_MIU_RD_RETURN_BUSY 0x00000004
451 #define AXXX_CP_STAT_MIU_RD_REQ_BUSY 0x00000002
452 #define AXXX_CP_STAT_MIU_WR_BUSY 0x00000001
454 #define REG_AXXX_CP_SCRATCH_REG0 0x00000578
456 #define REG_AXXX_CP_SCRATCH_REG1 0x00000579
458 #define REG_AXXX_CP_SCRATCH_REG2 0x0000057a
460 #define REG_AXXX_CP_SCRATCH_REG3 0x0000057b
462 #define REG_AXXX_CP_SCRATCH_REG4 0x0000057c
464 #define REG_AXXX_CP_SCRATCH_REG5 0x0000057d
466 #define REG_AXXX_CP_SCRATCH_REG6 0x0000057e
468 #define REG_AXXX_CP_SCRATCH_REG7 0x0000057f
470 #define REG_AXXX_CP_ME_VS_EVENT_SRC 0x00000600
472 #define REG_AXXX_CP_ME_VS_EVENT_ADDR 0x00000601
474 #define REG_AXXX_CP_ME_VS_EVENT_DATA 0x00000602
476 #define REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM 0x00000603
478 #define REG_AXXX_CP_ME_VS_EVENT_DATA_SWM 0x00000604
480 #define REG_AXXX_CP_ME_PS_EVENT_SRC 0x00000605
482 #define REG_AXXX_CP_ME_PS_EVENT_ADDR 0x00000606
484 #define REG_AXXX_CP_ME_PS_EVENT_DATA 0x00000607
486 #define REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM 0x00000608
488 #define REG_AXXX_CP_ME_PS_EVENT_DATA_SWM 0x00000609
490 #define REG_AXXX_CP_ME_CF_EVENT_SRC 0x0000060a
492 #define REG_AXXX_CP_ME_CF_EVENT_ADDR 0x0000060b
494 #define REG_AXXX_CP_ME_CF_EVENT_DATA 0x0000060c
496 #define REG_AXXX_CP_ME_NRT_ADDR 0x0000060d
498 #define REG_AXXX_CP_ME_NRT_DATA 0x0000060e
500 #define REG_AXXX_CP_ME_VS_FETCH_DONE_SRC 0x00000612
502 #define REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR 0x00000613
504 #define REG_AXXX_CP_ME_VS_FETCH_DONE_DATA 0x00000614
507 #endif /* ADRENO_COMMON_XML */