GNU Linux-libre 4.9.306-gnu1
[releases.git] / drivers / gpu / drm / msm / adreno / adreno_common.xml.h
1 #ifndef ADRENO_COMMON_XML
2 #define ADRENO_COMMON_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    398 bytes, from 2015-09-24 17:25:31)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2016-02-10 17:07:21)
13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2015-05-20 20:03:14)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  11518 bytes, from 2016-02-10 21:03:25)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  16166 bytes, from 2016-02-11 21:20:31)
16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83967 bytes, from 2016-02-10 17:07:21)
17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 109916 bytes, from 2016-02-20 18:44:48)
18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2015-09-24 17:30:00)
19
20 Copyright (C) 2013-2016 by the following authors:
21 - Rob Clark <robdclark@gmail.com> (robclark)
22 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
23
24 Permission is hereby granted, free of charge, to any person obtaining
25 a copy of this software and associated documentation files (the
26 "Software"), to deal in the Software without restriction, including
27 without limitation the rights to use, copy, modify, merge, publish,
28 distribute, sublicense, and/or sell copies of the Software, and to
29 permit persons to whom the Software is furnished to do so, subject to
30 the following conditions:
31
32 The above copyright notice and this permission notice (including the
33 next paragraph) shall be included in all copies or substantial
34 portions of the Software.
35
36 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
38 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
39 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
40 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
41 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
42 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45
46 enum adreno_pa_su_sc_draw {
47         PC_DRAW_POINTS = 0,
48         PC_DRAW_LINES = 1,
49         PC_DRAW_TRIANGLES = 2,
50 };
51
52 enum adreno_compare_func {
53         FUNC_NEVER = 0,
54         FUNC_LESS = 1,
55         FUNC_EQUAL = 2,
56         FUNC_LEQUAL = 3,
57         FUNC_GREATER = 4,
58         FUNC_NOTEQUAL = 5,
59         FUNC_GEQUAL = 6,
60         FUNC_ALWAYS = 7,
61 };
62
63 enum adreno_stencil_op {
64         STENCIL_KEEP = 0,
65         STENCIL_ZERO = 1,
66         STENCIL_REPLACE = 2,
67         STENCIL_INCR_CLAMP = 3,
68         STENCIL_DECR_CLAMP = 4,
69         STENCIL_INVERT = 5,
70         STENCIL_INCR_WRAP = 6,
71         STENCIL_DECR_WRAP = 7,
72 };
73
74 enum adreno_rb_blend_factor {
75         FACTOR_ZERO = 0,
76         FACTOR_ONE = 1,
77         FACTOR_SRC_COLOR = 4,
78         FACTOR_ONE_MINUS_SRC_COLOR = 5,
79         FACTOR_SRC_ALPHA = 6,
80         FACTOR_ONE_MINUS_SRC_ALPHA = 7,
81         FACTOR_DST_COLOR = 8,
82         FACTOR_ONE_MINUS_DST_COLOR = 9,
83         FACTOR_DST_ALPHA = 10,
84         FACTOR_ONE_MINUS_DST_ALPHA = 11,
85         FACTOR_CONSTANT_COLOR = 12,
86         FACTOR_ONE_MINUS_CONSTANT_COLOR = 13,
87         FACTOR_CONSTANT_ALPHA = 14,
88         FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15,
89         FACTOR_SRC_ALPHA_SATURATE = 16,
90         FACTOR_SRC1_COLOR = 20,
91         FACTOR_ONE_MINUS_SRC1_COLOR = 21,
92         FACTOR_SRC1_ALPHA = 22,
93         FACTOR_ONE_MINUS_SRC1_ALPHA = 23,
94 };
95
96 enum adreno_rb_surface_endian {
97         ENDIAN_NONE = 0,
98         ENDIAN_8IN16 = 1,
99         ENDIAN_8IN32 = 2,
100         ENDIAN_16IN32 = 3,
101         ENDIAN_8IN64 = 4,
102         ENDIAN_8IN128 = 5,
103 };
104
105 enum adreno_rb_dither_mode {
106         DITHER_DISABLE = 0,
107         DITHER_ALWAYS = 1,
108         DITHER_IF_ALPHA_OFF = 2,
109 };
110
111 enum adreno_rb_depth_format {
112         DEPTHX_16 = 0,
113         DEPTHX_24_8 = 1,
114         DEPTHX_32 = 2,
115 };
116
117 enum adreno_rb_copy_control_mode {
118         RB_COPY_RESOLVE = 1,
119         RB_COPY_CLEAR = 2,
120         RB_COPY_DEPTH_STENCIL = 5,
121 };
122
123 enum a3xx_rop_code {
124         ROP_CLEAR = 0,
125         ROP_NOR = 1,
126         ROP_AND_INVERTED = 2,
127         ROP_COPY_INVERTED = 3,
128         ROP_AND_REVERSE = 4,
129         ROP_INVERT = 5,
130         ROP_NAND = 7,
131         ROP_AND = 8,
132         ROP_EQUIV = 9,
133         ROP_NOOP = 10,
134         ROP_OR_INVERTED = 11,
135         ROP_OR_REVERSE = 13,
136         ROP_OR = 14,
137         ROP_SET = 15,
138 };
139
140 enum a3xx_render_mode {
141         RB_RENDERING_PASS = 0,
142         RB_TILING_PASS = 1,
143         RB_RESOLVE_PASS = 2,
144         RB_COMPUTE_PASS = 3,
145 };
146
147 enum a3xx_msaa_samples {
148         MSAA_ONE = 0,
149         MSAA_TWO = 1,
150         MSAA_FOUR = 2,
151 };
152
153 enum a3xx_threadmode {
154         MULTI = 0,
155         SINGLE = 1,
156 };
157
158 enum a3xx_instrbuffermode {
159         CACHE = 0,
160         BUFFER = 1,
161 };
162
163 enum a3xx_threadsize {
164         TWO_QUADS = 0,
165         FOUR_QUADS = 1,
166 };
167
168 enum a3xx_color_swap {
169         WZYX = 0,
170         WXYZ = 1,
171         ZYXW = 2,
172         XYZW = 3,
173 };
174
175 #define REG_AXXX_CP_RB_BASE                                     0x000001c0
176
177 #define REG_AXXX_CP_RB_CNTL                                     0x000001c1
178 #define AXXX_CP_RB_CNTL_BUFSZ__MASK                             0x0000003f
179 #define AXXX_CP_RB_CNTL_BUFSZ__SHIFT                            0
180 static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val)
181 {
182         return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK;
183 }
184 #define AXXX_CP_RB_CNTL_BLKSZ__MASK                             0x00003f00
185 #define AXXX_CP_RB_CNTL_BLKSZ__SHIFT                            8
186 static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val)
187 {
188         return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK;
189 }
190 #define AXXX_CP_RB_CNTL_BUF_SWAP__MASK                          0x00030000
191 #define AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT                         16
192 static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val)
193 {
194         return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK;
195 }
196 #define AXXX_CP_RB_CNTL_POLL_EN                                 0x00100000
197 #define AXXX_CP_RB_CNTL_NO_UPDATE                               0x08000000
198 #define AXXX_CP_RB_CNTL_RPTR_WR_EN                              0x80000000
199
200 #define REG_AXXX_CP_RB_RPTR_ADDR                                0x000001c3
201 #define AXXX_CP_RB_RPTR_ADDR_SWAP__MASK                         0x00000003
202 #define AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT                        0
203 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val)
204 {
205         return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK;
206 }
207 #define AXXX_CP_RB_RPTR_ADDR_ADDR__MASK                         0xfffffffc
208 #define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT                        2
209 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val)
210 {
211         return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK;
212 }
213
214 #define REG_AXXX_CP_RB_RPTR                                     0x000001c4
215
216 #define REG_AXXX_CP_RB_WPTR                                     0x000001c5
217
218 #define REG_AXXX_CP_RB_WPTR_DELAY                               0x000001c6
219
220 #define REG_AXXX_CP_RB_RPTR_WR                                  0x000001c7
221
222 #define REG_AXXX_CP_RB_WPTR_BASE                                0x000001c8
223
224 #define REG_AXXX_CP_QUEUE_THRESHOLDS                            0x000001d5
225 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK            0x0000000f
226 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT           0
227 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val)
228 {
229         return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK;
230 }
231 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK            0x00000f00
232 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT           8
233 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val)
234 {
235         return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK;
236 }
237 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK             0x000f0000
238 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT            16
239 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val)
240 {
241         return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK;
242 }
243
244 #define REG_AXXX_CP_MEQ_THRESHOLDS                              0x000001d6
245 #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK                    0x001f0000
246 #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT                   16
247 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val)
248 {
249         return ((val) << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK;
250 }
251 #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK                    0x1f000000
252 #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT                   24
253 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val)
254 {
255         return ((val) << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK;
256 }
257
258 #define REG_AXXX_CP_CSQ_AVAIL                                   0x000001d7
259 #define AXXX_CP_CSQ_AVAIL_RING__MASK                            0x0000007f
260 #define AXXX_CP_CSQ_AVAIL_RING__SHIFT                           0
261 static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val)
262 {
263         return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK;
264 }
265 #define AXXX_CP_CSQ_AVAIL_IB1__MASK                             0x00007f00
266 #define AXXX_CP_CSQ_AVAIL_IB1__SHIFT                            8
267 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val)
268 {
269         return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK;
270 }
271 #define AXXX_CP_CSQ_AVAIL_IB2__MASK                             0x007f0000
272 #define AXXX_CP_CSQ_AVAIL_IB2__SHIFT                            16
273 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val)
274 {
275         return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK;
276 }
277
278 #define REG_AXXX_CP_STQ_AVAIL                                   0x000001d8
279 #define AXXX_CP_STQ_AVAIL_ST__MASK                              0x0000007f
280 #define AXXX_CP_STQ_AVAIL_ST__SHIFT                             0
281 static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val)
282 {
283         return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK;
284 }
285
286 #define REG_AXXX_CP_MEQ_AVAIL                                   0x000001d9
287 #define AXXX_CP_MEQ_AVAIL_MEQ__MASK                             0x0000001f
288 #define AXXX_CP_MEQ_AVAIL_MEQ__SHIFT                            0
289 static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val)
290 {
291         return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK;
292 }
293
294 #define REG_AXXX_SCRATCH_UMSK                                   0x000001dc
295 #define AXXX_SCRATCH_UMSK_UMSK__MASK                            0x000000ff
296 #define AXXX_SCRATCH_UMSK_UMSK__SHIFT                           0
297 static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val)
298 {
299         return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK;
300 }
301 #define AXXX_SCRATCH_UMSK_SWAP__MASK                            0x00030000
302 #define AXXX_SCRATCH_UMSK_SWAP__SHIFT                           16
303 static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val)
304 {
305         return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK;
306 }
307
308 #define REG_AXXX_SCRATCH_ADDR                                   0x000001dd
309
310 #define REG_AXXX_CP_ME_RDADDR                                   0x000001ea
311
312 #define REG_AXXX_CP_STATE_DEBUG_INDEX                           0x000001ec
313
314 #define REG_AXXX_CP_STATE_DEBUG_DATA                            0x000001ed
315
316 #define REG_AXXX_CP_INT_CNTL                                    0x000001f2
317
318 #define REG_AXXX_CP_INT_STATUS                                  0x000001f3
319
320 #define REG_AXXX_CP_INT_ACK                                     0x000001f4
321
322 #define REG_AXXX_CP_ME_CNTL                                     0x000001f6
323 #define AXXX_CP_ME_CNTL_BUSY                                    0x20000000
324 #define AXXX_CP_ME_CNTL_HALT                                    0x10000000
325
326 #define REG_AXXX_CP_ME_STATUS                                   0x000001f7
327
328 #define REG_AXXX_CP_ME_RAM_WADDR                                0x000001f8
329
330 #define REG_AXXX_CP_ME_RAM_RADDR                                0x000001f9
331
332 #define REG_AXXX_CP_ME_RAM_DATA                                 0x000001fa
333
334 #define REG_AXXX_CP_DEBUG                                       0x000001fc
335 #define AXXX_CP_DEBUG_PREDICATE_DISABLE                         0x00800000
336 #define AXXX_CP_DEBUG_PROG_END_PTR_ENABLE                       0x01000000
337 #define AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE                   0x02000000
338 #define AXXX_CP_DEBUG_PREFETCH_PASS_NOPS                        0x04000000
339 #define AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE                       0x08000000
340 #define AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE                    0x10000000
341 #define AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL                    0x40000000
342 #define AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE                    0x80000000
343
344 #define REG_AXXX_CP_CSQ_RB_STAT                                 0x000001fd
345 #define AXXX_CP_CSQ_RB_STAT_RPTR__MASK                          0x0000007f
346 #define AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT                         0
347 static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val)
348 {
349         return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK;
350 }
351 #define AXXX_CP_CSQ_RB_STAT_WPTR__MASK                          0x007f0000
352 #define AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT                         16
353 static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val)
354 {
355         return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK;
356 }
357
358 #define REG_AXXX_CP_CSQ_IB1_STAT                                0x000001fe
359 #define AXXX_CP_CSQ_IB1_STAT_RPTR__MASK                         0x0000007f
360 #define AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT                        0
361 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val)
362 {
363         return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK;
364 }
365 #define AXXX_CP_CSQ_IB1_STAT_WPTR__MASK                         0x007f0000
366 #define AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT                        16
367 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val)
368 {
369         return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK;
370 }
371
372 #define REG_AXXX_CP_CSQ_IB2_STAT                                0x000001ff
373 #define AXXX_CP_CSQ_IB2_STAT_RPTR__MASK                         0x0000007f
374 #define AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT                        0
375 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val)
376 {
377         return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK;
378 }
379 #define AXXX_CP_CSQ_IB2_STAT_WPTR__MASK                         0x007f0000
380 #define AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT                        16
381 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)
382 {
383         return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK;
384 }
385
386 #define REG_AXXX_CP_NON_PREFETCH_CNTRS                          0x00000440
387
388 #define REG_AXXX_CP_STQ_ST_STAT                                 0x00000443
389
390 #define REG_AXXX_CP_ST_BASE                                     0x0000044d
391
392 #define REG_AXXX_CP_ST_BUFSZ                                    0x0000044e
393
394 #define REG_AXXX_CP_MEQ_STAT                                    0x0000044f
395
396 #define REG_AXXX_CP_MIU_TAG_STAT                                0x00000452
397
398 #define REG_AXXX_CP_BIN_MASK_LO                                 0x00000454
399
400 #define REG_AXXX_CP_BIN_MASK_HI                                 0x00000455
401
402 #define REG_AXXX_CP_BIN_SELECT_LO                               0x00000456
403
404 #define REG_AXXX_CP_BIN_SELECT_HI                               0x00000457
405
406 #define REG_AXXX_CP_IB1_BASE                                    0x00000458
407
408 #define REG_AXXX_CP_IB1_BUFSZ                                   0x00000459
409
410 #define REG_AXXX_CP_IB2_BASE                                    0x0000045a
411
412 #define REG_AXXX_CP_IB2_BUFSZ                                   0x0000045b
413
414 #define REG_AXXX_CP_STAT                                        0x0000047f
415
416 #define REG_AXXX_CP_SCRATCH_REG0                                0x00000578
417
418 #define REG_AXXX_CP_SCRATCH_REG1                                0x00000579
419
420 #define REG_AXXX_CP_SCRATCH_REG2                                0x0000057a
421
422 #define REG_AXXX_CP_SCRATCH_REG3                                0x0000057b
423
424 #define REG_AXXX_CP_SCRATCH_REG4                                0x0000057c
425
426 #define REG_AXXX_CP_SCRATCH_REG5                                0x0000057d
427
428 #define REG_AXXX_CP_SCRATCH_REG6                                0x0000057e
429
430 #define REG_AXXX_CP_SCRATCH_REG7                                0x0000057f
431
432 #define REG_AXXX_CP_ME_VS_EVENT_SRC                             0x00000600
433
434 #define REG_AXXX_CP_ME_VS_EVENT_ADDR                            0x00000601
435
436 #define REG_AXXX_CP_ME_VS_EVENT_DATA                            0x00000602
437
438 #define REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM                        0x00000603
439
440 #define REG_AXXX_CP_ME_VS_EVENT_DATA_SWM                        0x00000604
441
442 #define REG_AXXX_CP_ME_PS_EVENT_SRC                             0x00000605
443
444 #define REG_AXXX_CP_ME_PS_EVENT_ADDR                            0x00000606
445
446 #define REG_AXXX_CP_ME_PS_EVENT_DATA                            0x00000607
447
448 #define REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM                        0x00000608
449
450 #define REG_AXXX_CP_ME_PS_EVENT_DATA_SWM                        0x00000609
451
452 #define REG_AXXX_CP_ME_CF_EVENT_SRC                             0x0000060a
453
454 #define REG_AXXX_CP_ME_CF_EVENT_ADDR                            0x0000060b
455
456 #define REG_AXXX_CP_ME_CF_EVENT_DATA                            0x0000060c
457
458 #define REG_AXXX_CP_ME_NRT_ADDR                                 0x0000060d
459
460 #define REG_AXXX_CP_ME_NRT_DATA                                 0x0000060e
461
462 #define REG_AXXX_CP_ME_VS_FETCH_DONE_SRC                        0x00000612
463
464 #define REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR                       0x00000613
465
466 #define REG_AXXX_CP_ME_VS_FETCH_DONE_DATA                       0x00000614
467
468
469 #endif /* ADRENO_COMMON_XML */