1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2010 Matt Turner.
4 * Copyright 2012 Red Hat
6 * Authors: Matthew Garrett
11 #include <linux/delay.h>
13 #include <drm/drm_atomic_helper.h>
14 #include <drm/drm_atomic_state_helper.h>
15 #include <drm/drm_crtc_helper.h>
16 #include <drm/drm_damage_helper.h>
17 #include <drm/drm_format_helper.h>
18 #include <drm/drm_fourcc.h>
19 #include <drm/drm_gem_framebuffer_helper.h>
20 #include <drm/drm_plane_helper.h>
21 #include <drm/drm_print.h>
22 #include <drm/drm_probe_helper.h>
23 #include <drm/drm_simple_kms_helper.h>
25 #include "mgag200_drv.h"
27 #define MGAG200_LUT_SIZE 256
30 * This file contains setup code for the CRTC.
33 static void mga_crtc_load_lut(struct drm_crtc *crtc)
35 struct drm_device *dev = crtc->dev;
36 struct mga_device *mdev = to_mga_device(dev);
37 struct drm_framebuffer *fb;
38 u16 *r_ptr, *g_ptr, *b_ptr;
44 if (!mdev->display_pipe.plane.state)
47 fb = mdev->display_pipe.plane.state->fb;
49 r_ptr = crtc->gamma_store;
50 g_ptr = r_ptr + crtc->gamma_size;
51 b_ptr = g_ptr + crtc->gamma_size;
53 WREG8(DAC_INDEX + MGA1064_INDEX, 0);
55 if (fb && fb->format->cpp[0] * 8 == 16) {
56 int inc = (fb->format->depth == 15) ? 8 : 4;
58 for (i = 0; i < MGAG200_LUT_SIZE; i += inc) {
59 if (fb->format->depth == 16) {
60 if (i > (MGAG200_LUT_SIZE >> 1)) {
73 WREG8(DAC_INDEX + MGA1064_COL_PAL, r);
74 WREG8(DAC_INDEX + MGA1064_COL_PAL, *g_ptr++ >> 8);
75 WREG8(DAC_INDEX + MGA1064_COL_PAL, b);
79 for (i = 0; i < MGAG200_LUT_SIZE; i++) {
81 WREG8(DAC_INDEX + MGA1064_COL_PAL, *r_ptr++ >> 8);
82 WREG8(DAC_INDEX + MGA1064_COL_PAL, *g_ptr++ >> 8);
83 WREG8(DAC_INDEX + MGA1064_COL_PAL, *b_ptr++ >> 8);
87 static inline void mga_wait_vsync(struct mga_device *mdev)
89 unsigned long timeout = jiffies + HZ/10;
90 unsigned int status = 0;
93 status = RREG32(MGAREG_Status);
94 } while ((status & 0x08) && time_before(jiffies, timeout));
95 timeout = jiffies + HZ/10;
98 status = RREG32(MGAREG_Status);
99 } while (!(status & 0x08) && time_before(jiffies, timeout));
102 static inline void mga_wait_busy(struct mga_device *mdev)
104 unsigned long timeout = jiffies + HZ;
105 unsigned int status = 0;
107 status = RREG8(MGAREG_Status + 2);
108 } while ((status & 0x01) && time_before(jiffies, timeout));
115 static int mgag200_g200_set_plls(struct mga_device *mdev, long clock)
117 struct drm_device *dev = &mdev->base;
118 const int post_div_max = 7;
119 const int in_div_min = 1;
120 const int in_div_max = 6;
121 const int feed_div_min = 7;
122 const int feed_div_max = 127;
124 u8 n = 0, m = 0, p, s;
127 long delta, tmp_delta;
128 long ref_clk = mdev->model.g200.ref_clk;
129 long p_clk_min = mdev->model.g200.pclk_min;
130 long p_clk_max = mdev->model.g200.pclk_max;
132 if (clock > p_clk_max) {
133 drm_err(dev, "Pixel Clock %ld too high\n", clock);
137 if (clock < p_clk_min >> 3)
138 clock = p_clk_min >> 3;
142 p <= post_div_max && f_vco < p_clk_min;
143 p = (p << 1) + 1, f_vco <<= 1)
148 for (testm = in_div_min; testm <= in_div_max; testm++) {
149 for (testn = feed_div_min; testn <= feed_div_max; testn++) {
150 computed = ref_clk * (testn + 1) / (testm + 1);
151 if (computed < f_vco)
152 tmp_delta = f_vco - computed;
154 tmp_delta = computed - f_vco;
155 if (tmp_delta < delta) {
162 f_vco = ref_clk * (n + 1) / (m + 1);
165 else if (f_vco < 140000)
167 else if (f_vco < 180000)
172 drm_dbg_kms(dev, "clock: %ld vco: %ld m: %d n: %d p: %d s: %d\n",
173 clock, f_vco, m, n, p, s);
175 WREG_MISC_MASKED(MGAREG_MISC_CLKSEL_MGA, MGAREG_MISC_CLKSEL_MASK);
177 WREG_DAC(MGA1064_PIX_PLLC_M, m);
178 WREG_DAC(MGA1064_PIX_PLLC_N, n);
179 WREG_DAC(MGA1064_PIX_PLLC_P, (p | (s << 3)));
184 #define P_ARRAY_SIZE 9
186 static int mga_g200se_set_plls(struct mga_device *mdev, long clock)
188 u32 unique_rev_id = mdev->model.g200se.unique_rev_id;
189 unsigned int vcomax, vcomin, pllreffreq;
190 unsigned int delta, tmpdelta, permitteddelta;
191 unsigned int testp, testm, testn;
192 unsigned int p, m, n;
193 unsigned int computed;
194 unsigned int pvalues_e4[P_ARRAY_SIZE] = {16, 14, 12, 10, 8, 6, 4, 2, 1};
198 if (unique_rev_id <= 0x03) {
206 permitteddelta = clock * 5 / 1000;
208 for (testp = 8; testp > 0; testp /= 2) {
209 if (clock * testp > vcomax)
211 if (clock * testp < vcomin)
214 for (testn = 17; testn < 256; testn++) {
215 for (testm = 1; testm < 32; testm++) {
216 computed = (pllreffreq * testn) /
218 if (computed > clock)
219 tmpdelta = computed - clock;
221 tmpdelta = clock - computed;
222 if (tmpdelta < delta) {
245 /* Permited delta is 0.5% as VESA Specification */
246 permitteddelta = clock * 5 / 1000;
248 for (i = 0 ; i < P_ARRAY_SIZE ; i++) {
249 testp = pvalues_e4[i];
251 if ((clock * testp) > vcomax)
253 if ((clock * testp) < vcomin)
256 for (testn = 50; testn <= 256; testn++) {
257 for (testm = 1; testm <= 32; testm++) {
258 computed = (pllreffreq * testn) /
260 if (computed > clock)
261 tmpdelta = computed - clock;
263 tmpdelta = clock - computed;
265 if (tmpdelta < delta) {
275 fvv = pllreffreq * (n + 1) / (m + 1);
276 fvv = (fvv - 800000) / 50000;
287 if (delta > permitteddelta) {
288 pr_warn("PLL delta too large\n");
292 WREG_MISC_MASKED(MGAREG_MISC_CLKSEL_MGA, MGAREG_MISC_CLKSEL_MASK);
294 WREG_DAC(MGA1064_PIX_PLLC_M, m);
295 WREG_DAC(MGA1064_PIX_PLLC_N, n);
296 WREG_DAC(MGA1064_PIX_PLLC_P, p);
298 if (unique_rev_id >= 0x04) {
299 WREG_DAC(0x1a, 0x09);
301 WREG_DAC(0x1a, 0x01);
308 static int mga_g200wb_set_plls(struct mga_device *mdev, long clock)
310 unsigned int vcomax, vcomin, pllreffreq;
311 unsigned int delta, tmpdelta;
312 unsigned int testp, testm, testn, testp2;
313 unsigned int p, m, n;
314 unsigned int computed;
315 int i, j, tmpcount, vcount;
316 bool pll_locked = false;
323 if (mdev->type == G200_EW3) {
329 for (testp = 1; testp < 8; testp++) {
330 for (testp2 = 1; testp2 < 8; testp2++) {
333 if ((clock * testp * testp2) > vcomax)
335 if ((clock * testp * testp2) < vcomin)
337 for (testm = 1; testm < 26; testm++) {
338 for (testn = 32; testn < 2048 ; testn++) {
339 computed = (pllreffreq * testn) /
340 (testm * testp * testp2);
341 if (computed > clock)
342 tmpdelta = computed - clock;
344 tmpdelta = clock - computed;
345 if (tmpdelta < delta) {
347 m = ((testn & 0x100) >> 1) |
350 p = ((testn & 0x600) >> 3) |
364 for (testp = 1; testp < 9; testp++) {
365 if (clock * testp > vcomax)
367 if (clock * testp < vcomin)
370 for (testm = 1; testm < 17; testm++) {
371 for (testn = 1; testn < 151; testn++) {
372 computed = (pllreffreq * testn) /
374 if (computed > clock)
375 tmpdelta = computed - clock;
377 tmpdelta = clock - computed;
378 if (tmpdelta < delta) {
390 WREG_MISC_MASKED(MGAREG_MISC_CLKSEL_MGA, MGAREG_MISC_CLKSEL_MASK);
392 for (i = 0; i <= 32 && pll_locked == false; i++) {
394 WREG8(MGAREG_CRTC_INDEX, 0x1e);
395 tmp = RREG8(MGAREG_CRTC_DATA);
397 WREG8(MGAREG_CRTC_DATA, tmp+1);
400 /* set pixclkdis to 1 */
401 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
402 tmp = RREG8(DAC_DATA);
403 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
404 WREG8(DAC_DATA, tmp);
406 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
407 tmp = RREG8(DAC_DATA);
408 tmp |= MGA1064_REMHEADCTL_CLKDIS;
409 WREG8(DAC_DATA, tmp);
411 /* select PLL Set C */
412 tmp = RREG8(MGAREG_MEM_MISC_READ);
414 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
416 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
417 tmp = RREG8(DAC_DATA);
418 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN | 0x80;
419 WREG8(DAC_DATA, tmp);
424 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
425 tmp = RREG8(DAC_DATA);
427 WREG8(DAC_DATA, tmp);
431 /* program pixel pll register */
432 WREG_DAC(MGA1064_WB_PIX_PLLC_N, n);
433 WREG_DAC(MGA1064_WB_PIX_PLLC_M, m);
434 WREG_DAC(MGA1064_WB_PIX_PLLC_P, p);
439 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
440 tmp = RREG8(DAC_DATA);
442 WREG_DAC(MGA1064_VREF_CTL, tmp);
446 /* select the pixel pll */
447 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
448 tmp = RREG8(DAC_DATA);
449 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
450 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
451 WREG8(DAC_DATA, tmp);
453 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
454 tmp = RREG8(DAC_DATA);
455 tmp &= ~MGA1064_REMHEADCTL_CLKSL_MSK;
456 tmp |= MGA1064_REMHEADCTL_CLKSL_PLL;
457 WREG8(DAC_DATA, tmp);
459 /* reset dotclock rate bit */
460 WREG8(MGAREG_SEQ_INDEX, 1);
461 tmp = RREG8(MGAREG_SEQ_DATA);
463 WREG8(MGAREG_SEQ_DATA, tmp);
465 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
466 tmp = RREG8(DAC_DATA);
467 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
468 WREG8(DAC_DATA, tmp);
470 vcount = RREG8(MGAREG_VCOUNT);
472 for (j = 0; j < 30 && pll_locked == false; j++) {
473 tmpcount = RREG8(MGAREG_VCOUNT);
474 if (tmpcount < vcount)
476 if ((tmpcount - vcount) > 2)
482 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
483 tmp = RREG8(DAC_DATA);
484 tmp &= ~MGA1064_REMHEADCTL_CLKDIS;
485 WREG_DAC(MGA1064_REMHEADCTL, tmp);
489 static int mga_g200ev_set_plls(struct mga_device *mdev, long clock)
491 unsigned int vcomax, vcomin, pllreffreq;
492 unsigned int delta, tmpdelta;
493 unsigned int testp, testm, testn;
494 unsigned int p, m, n;
495 unsigned int computed;
505 for (testp = 16; testp > 0; testp--) {
506 if (clock * testp > vcomax)
508 if (clock * testp < vcomin)
511 for (testn = 1; testn < 257; testn++) {
512 for (testm = 1; testm < 17; testm++) {
513 computed = (pllreffreq * testn) /
515 if (computed > clock)
516 tmpdelta = computed - clock;
518 tmpdelta = clock - computed;
519 if (tmpdelta < delta) {
529 WREG_MISC_MASKED(MGAREG_MISC_CLKSEL_MGA, MGAREG_MISC_CLKSEL_MASK);
531 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
532 tmp = RREG8(DAC_DATA);
533 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
534 WREG8(DAC_DATA, tmp);
536 tmp = RREG8(MGAREG_MEM_MISC_READ);
538 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
540 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
541 tmp = RREG8(DAC_DATA);
542 WREG8(DAC_DATA, tmp & ~0x40);
544 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
545 tmp = RREG8(DAC_DATA);
546 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
547 WREG8(DAC_DATA, tmp);
549 WREG_DAC(MGA1064_EV_PIX_PLLC_M, m);
550 WREG_DAC(MGA1064_EV_PIX_PLLC_N, n);
551 WREG_DAC(MGA1064_EV_PIX_PLLC_P, p);
555 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
556 tmp = RREG8(DAC_DATA);
557 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
558 WREG8(DAC_DATA, tmp);
562 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
563 tmp = RREG8(DAC_DATA);
564 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
565 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
566 WREG8(DAC_DATA, tmp);
568 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
569 tmp = RREG8(DAC_DATA);
570 WREG8(DAC_DATA, tmp | 0x40);
572 tmp = RREG8(MGAREG_MEM_MISC_READ);
574 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
576 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
577 tmp = RREG8(DAC_DATA);
578 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
579 WREG8(DAC_DATA, tmp);
584 static int mga_g200eh_set_plls(struct mga_device *mdev, long clock)
586 unsigned int vcomax, vcomin, pllreffreq;
587 unsigned int delta, tmpdelta;
588 unsigned int testp, testm, testn;
589 unsigned int p, m, n;
590 unsigned int computed;
591 int i, j, tmpcount, vcount;
593 bool pll_locked = false;
597 if (mdev->type == G200_EH3) {
606 for (testm = 150; testm >= 6; testm--) {
607 if (clock * testm > vcomax)
609 if (clock * testm < vcomin)
611 for (testn = 120; testn >= 60; testn--) {
612 computed = (pllreffreq * testn) / testm;
613 if (computed > clock)
614 tmpdelta = computed - clock;
616 tmpdelta = clock - computed;
617 if (tmpdelta < delta) {
637 for (testp = 16; testp > 0; testp >>= 1) {
638 if (clock * testp > vcomax)
640 if (clock * testp < vcomin)
643 for (testm = 1; testm < 33; testm++) {
644 for (testn = 17; testn < 257; testn++) {
645 computed = (pllreffreq * testn) /
647 if (computed > clock)
648 tmpdelta = computed - clock;
650 tmpdelta = clock - computed;
651 if (tmpdelta < delta) {
657 if ((clock * testp) >= 600000)
664 WREG_MISC_MASKED(MGAREG_MISC_CLKSEL_MGA, MGAREG_MISC_CLKSEL_MASK);
666 for (i = 0; i <= 32 && pll_locked == false; i++) {
667 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
668 tmp = RREG8(DAC_DATA);
669 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
670 WREG8(DAC_DATA, tmp);
672 tmp = RREG8(MGAREG_MEM_MISC_READ);
674 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
676 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
677 tmp = RREG8(DAC_DATA);
678 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
679 WREG8(DAC_DATA, tmp);
683 WREG_DAC(MGA1064_EH_PIX_PLLC_M, m);
684 WREG_DAC(MGA1064_EH_PIX_PLLC_N, n);
685 WREG_DAC(MGA1064_EH_PIX_PLLC_P, p);
689 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
690 tmp = RREG8(DAC_DATA);
691 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
692 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
693 WREG8(DAC_DATA, tmp);
695 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
696 tmp = RREG8(DAC_DATA);
697 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
698 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
699 WREG8(DAC_DATA, tmp);
701 vcount = RREG8(MGAREG_VCOUNT);
703 for (j = 0; j < 30 && pll_locked == false; j++) {
704 tmpcount = RREG8(MGAREG_VCOUNT);
705 if (tmpcount < vcount)
707 if ((tmpcount - vcount) > 2)
717 static int mga_g200er_set_plls(struct mga_device *mdev, long clock)
719 unsigned int vcomax, vcomin, pllreffreq;
720 unsigned int delta, tmpdelta;
721 int testr, testn, testm, testo;
722 unsigned int p, m, n;
723 unsigned int computed, vco;
725 const unsigned int m_div_val[] = { 1, 2, 4, 8 };
734 for (testr = 0; testr < 4; testr++) {
737 for (testn = 5; testn < 129; testn++) {
740 for (testm = 3; testm >= 0; testm--) {
743 for (testo = 5; testo < 33; testo++) {
744 vco = pllreffreq * (testn + 1) /
750 computed = vco / (m_div_val[testm] * (testo + 1));
751 if (computed > clock)
752 tmpdelta = computed - clock;
754 tmpdelta = clock - computed;
755 if (tmpdelta < delta) {
757 m = testm | (testo << 3);
759 p = testr | (testr << 3);
766 WREG_MISC_MASKED(MGAREG_MISC_CLKSEL_MGA, MGAREG_MISC_CLKSEL_MASK);
768 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
769 tmp = RREG8(DAC_DATA);
770 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
771 WREG8(DAC_DATA, tmp);
773 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
774 tmp = RREG8(DAC_DATA);
775 tmp |= MGA1064_REMHEADCTL_CLKDIS;
776 WREG8(DAC_DATA, tmp);
778 tmp = RREG8(MGAREG_MEM_MISC_READ);
779 tmp |= (0x3<<2) | 0xc0;
780 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
782 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
783 tmp = RREG8(DAC_DATA);
784 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
785 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
786 WREG8(DAC_DATA, tmp);
790 WREG_DAC(MGA1064_ER_PIX_PLLC_N, n);
791 WREG_DAC(MGA1064_ER_PIX_PLLC_M, m);
792 WREG_DAC(MGA1064_ER_PIX_PLLC_P, p);
799 static int mgag200_crtc_set_plls(struct mga_device *mdev, long clock)
804 return mgag200_g200_set_plls(mdev, clock);
807 return mga_g200se_set_plls(mdev, clock);
811 return mga_g200wb_set_plls(mdev, clock);
814 return mga_g200ev_set_plls(mdev, clock);
818 return mga_g200eh_set_plls(mdev, clock);
821 return mga_g200er_set_plls(mdev, clock);
828 static void mgag200_g200wb_hold_bmc(struct mga_device *mdev)
833 /* 1- The first step is to warn the BMC of an upcoming mode change.
834 * We are putting the misc<0> to output.*/
836 WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL);
837 tmp = RREG8(DAC_DATA);
839 WREG_DAC(MGA1064_GEN_IO_CTL, tmp);
841 /* we are putting a 1 on the misc<0> line */
842 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
843 tmp = RREG8(DAC_DATA);
845 WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
847 /* 2- Second step to mask and further scan request
848 * This will be done by asserting the remfreqmsk bit (XSPAREREG<7>)
850 WREG8(DAC_INDEX, MGA1064_SPAREREG);
851 tmp = RREG8(DAC_DATA);
853 WREG_DAC(MGA1064_SPAREREG, tmp);
855 /* 3a- the third step is to verifu if there is an active scan
856 * We are searching for a 0 on remhsyncsts <XSPAREREG<0>)
859 while (!(tmp & 0x1) && iter_max) {
860 WREG8(DAC_INDEX, MGA1064_SPAREREG);
861 tmp = RREG8(DAC_DATA);
866 /* 3b- this step occurs only if the remove is actually scanning
867 * we are waiting for the end of the frame which is a 1 on
868 * remvsyncsts (XSPAREREG<1>)
872 while ((tmp & 0x2) && iter_max) {
873 WREG8(DAC_INDEX, MGA1064_SPAREREG);
874 tmp = RREG8(DAC_DATA);
881 static void mgag200_g200wb_release_bmc(struct mga_device *mdev)
885 /* 1- The first step is to ensure that the vrsten and hrsten are set */
886 WREG8(MGAREG_CRTCEXT_INDEX, 1);
887 tmp = RREG8(MGAREG_CRTCEXT_DATA);
888 WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88);
890 /* 2- second step is to assert the rstlvl2 */
891 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
892 tmp = RREG8(DAC_DATA);
894 WREG8(DAC_DATA, tmp);
899 /* 3- deassert rstlvl2 */
901 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
902 WREG8(DAC_DATA, tmp);
904 /* 4- remove mask of scan request */
905 WREG8(DAC_INDEX, MGA1064_SPAREREG);
906 tmp = RREG8(DAC_DATA);
908 WREG8(DAC_DATA, tmp);
910 /* 5- put back a 0 on the misc<0> line */
911 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
912 tmp = RREG8(DAC_DATA);
914 WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
918 * This is how the framebuffer base address is stored in g200 cards:
919 * * Assume @offset is the gpu_addr variable of the framebuffer object
920 * * Then addr is the number of _pixels_ (not bytes) from the start of
921 * VRAM to the first pixel we want to display. (divided by 2 for 32bit
923 * * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers
924 * addr<20> -> CRTCEXT0<6>
925 * addr<19-16> -> CRTCEXT0<3-0>
926 * addr<15-8> -> CRTCC<7-0>
927 * addr<7-0> -> CRTCD<7-0>
929 * CRTCEXT0 has to be programmed last to trigger an update and make the
930 * new addr variable take effect.
932 static void mgag200_set_startadd(struct mga_device *mdev,
933 unsigned long offset)
935 struct drm_device *dev = &mdev->base;
937 u8 crtcc, crtcd, crtcext0;
939 startadd = offset / 8;
942 * Can't store addresses any higher than that, but we also
943 * don't have more than 16 MiB of memory, so it should be fine.
945 drm_WARN_ON(dev, startadd > 0x1fffff);
947 RREG_ECRT(0x00, crtcext0);
949 crtcc = (startadd >> 8) & 0xff;
950 crtcd = startadd & 0xff;
952 crtcext0 |= ((startadd >> 14) & BIT(6)) |
953 ((startadd >> 16) & 0x0f);
955 WREG_CRT(0x0c, crtcc);
956 WREG_CRT(0x0d, crtcd);
957 WREG_ECRT(0x00, crtcext0);
960 static void mgag200_set_dac_regs(struct mga_device *mdev)
964 /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0,
965 /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0,
966 /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0,
967 /* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20,
968 /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
969 /* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40,
970 /* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83,
971 /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A,
972 /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0,
973 /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0
976 switch (mdev->type) {
979 dacvalue[MGA1064_SYS_PLL_M] = 0x04;
980 dacvalue[MGA1064_SYS_PLL_N] = 0x2D;
981 dacvalue[MGA1064_SYS_PLL_P] = 0x19;
985 dacvalue[MGA1064_VREF_CTL] = 0x03;
986 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
987 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN |
988 MGA1064_MISC_CTL_VGA8 |
989 MGA1064_MISC_CTL_DAC_RAM_CS;
993 dacvalue[MGA1064_VREF_CTL] = 0x07;
996 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
997 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
998 MGA1064_MISC_CTL_DAC_RAM_CS;
1002 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
1003 MGA1064_MISC_CTL_DAC_RAM_CS;
1009 for (i = 0; i < ARRAY_SIZE(dacvalue); i++) {
1013 ((i >= 0x1f) && (i <= 0x29)) ||
1014 ((i >= 0x30) && (i <= 0x37)))
1016 if (IS_G200_SE(mdev) &&
1017 ((i == 0x2c) || (i == 0x2d) || (i == 0x2e)))
1019 if ((mdev->type == G200_EV ||
1020 mdev->type == G200_WB ||
1021 mdev->type == G200_EH ||
1022 mdev->type == G200_EW3 ||
1023 mdev->type == G200_EH3) &&
1024 (i >= 0x44) && (i <= 0x4e))
1027 WREG_DAC(i, dacvalue[i]);
1030 if (mdev->type == G200_ER)
1034 static void mgag200_init_regs(struct mga_device *mdev)
1038 mgag200_set_dac_regs(mdev);
1051 RREG_CRT(0x11, crtc11);
1052 crtc11 &= ~(MGAREG_CRTC11_CRTCPROTECT |
1053 MGAREG_CRTC11_VINTEN |
1054 MGAREG_CRTC11_VINTCLR);
1055 WREG_CRT(0x11, crtc11);
1057 if (mdev->type == G200_ER)
1058 WREG_ECRT(0x24, 0x5);
1060 if (mdev->type == G200_EW3)
1061 WREG_ECRT(0x34, 0x5);
1063 misc = RREG8(MGA_MISC_IN);
1064 misc |= MGAREG_MISC_IOADSEL;
1065 WREG8(MGA_MISC_OUT, misc);
1068 static void mgag200_set_mode_regs(struct mga_device *mdev,
1069 const struct drm_display_mode *mode)
1071 unsigned int hdisplay, hsyncstart, hsyncend, htotal;
1072 unsigned int vdisplay, vsyncstart, vsyncend, vtotal;
1073 u8 misc, crtcext1, crtcext2, crtcext5;
1075 hdisplay = mode->hdisplay / 8 - 1;
1076 hsyncstart = mode->hsync_start / 8 - 1;
1077 hsyncend = mode->hsync_end / 8 - 1;
1078 htotal = mode->htotal / 8 - 1;
1080 /* Work around hardware quirk */
1081 if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04)
1084 vdisplay = mode->vdisplay - 1;
1085 vsyncstart = mode->vsync_start - 1;
1086 vsyncend = mode->vsync_end - 1;
1087 vtotal = mode->vtotal - 2;
1089 misc = RREG8(MGA_MISC_IN);
1091 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1092 misc |= MGAREG_MISC_HSYNCPOL;
1094 misc &= ~MGAREG_MISC_HSYNCPOL;
1096 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1097 misc |= MGAREG_MISC_VSYNCPOL;
1099 misc &= ~MGAREG_MISC_VSYNCPOL;
1101 crtcext1 = (((htotal - 4) & 0x100) >> 8) |
1102 ((hdisplay & 0x100) >> 7) |
1103 ((hsyncstart & 0x100) >> 6) |
1105 if (mdev->type == G200_WB || mdev->type == G200_EW3)
1106 crtcext1 |= BIT(7) | /* vrsten */
1107 BIT(3); /* hrsten */
1109 crtcext2 = ((vtotal & 0xc00) >> 10) |
1110 ((vdisplay & 0x400) >> 8) |
1111 ((vdisplay & 0xc00) >> 7) |
1112 ((vsyncstart & 0xc00) >> 5) |
1113 ((vdisplay & 0x400) >> 3);
1116 WREG_CRT(0, htotal - 4);
1117 WREG_CRT(1, hdisplay);
1118 WREG_CRT(2, hdisplay);
1119 WREG_CRT(3, (htotal & 0x1F) | 0x80);
1120 WREG_CRT(4, hsyncstart);
1121 WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F));
1122 WREG_CRT(6, vtotal & 0xFF);
1123 WREG_CRT(7, ((vtotal & 0x100) >> 8) |
1124 ((vdisplay & 0x100) >> 7) |
1125 ((vsyncstart & 0x100) >> 6) |
1126 ((vdisplay & 0x100) >> 5) |
1127 ((vdisplay & 0x100) >> 4) | /* linecomp */
1128 ((vtotal & 0x200) >> 4) |
1129 ((vdisplay & 0x200) >> 3) |
1130 ((vsyncstart & 0x200) >> 2));
1131 WREG_CRT(9, ((vdisplay & 0x200) >> 4) |
1132 ((vdisplay & 0x200) >> 3));
1133 WREG_CRT(16, vsyncstart & 0xFF);
1134 WREG_CRT(17, (vsyncend & 0x0F) | 0x20);
1135 WREG_CRT(18, vdisplay & 0xFF);
1137 WREG_CRT(21, vdisplay & 0xFF);
1138 WREG_CRT(22, (vtotal + 1) & 0xFF);
1140 WREG_CRT(24, vdisplay & 0xFF);
1142 WREG_ECRT(0x01, crtcext1);
1143 WREG_ECRT(0x02, crtcext2);
1144 WREG_ECRT(0x05, crtcext5);
1146 WREG8(MGA_MISC_OUT, misc);
1149 static u8 mgag200_get_bpp_shift(struct mga_device *mdev,
1150 const struct drm_format_info *format)
1152 return mdev->bpp_shifts[format->cpp[0] - 1];
1156 * Calculates the HW offset value from the framebuffer's pitch. The
1157 * offset is a multiple of the pixel size and depends on the display
1160 static u32 mgag200_calculate_offset(struct mga_device *mdev,
1161 const struct drm_framebuffer *fb)
1163 u32 offset = fb->pitches[0] / fb->format->cpp[0];
1164 u8 bppshift = mgag200_get_bpp_shift(mdev, fb->format);
1166 if (fb->format->cpp[0] * 8 == 24)
1167 offset = (offset * 3) >> (4 - bppshift);
1169 offset = offset >> (4 - bppshift);
1174 static void mgag200_set_offset(struct mga_device *mdev,
1175 const struct drm_framebuffer *fb)
1177 u8 crtc13, crtcext0;
1178 u32 offset = mgag200_calculate_offset(mdev, fb);
1180 RREG_ECRT(0, crtcext0);
1182 crtc13 = offset & 0xff;
1184 crtcext0 &= ~MGAREG_CRTCEXT0_OFFSET_MASK;
1185 crtcext0 |= (offset >> 4) & MGAREG_CRTCEXT0_OFFSET_MASK;
1187 WREG_CRT(0x13, crtc13);
1188 WREG_ECRT(0x00, crtcext0);
1191 static void mgag200_set_format_regs(struct mga_device *mdev,
1192 const struct drm_framebuffer *fb)
1194 struct drm_device *dev = &mdev->base;
1195 const struct drm_format_info *format = fb->format;
1196 unsigned int bpp, bppshift, scale;
1197 u8 crtcext3, xmulctrl;
1199 bpp = format->cpp[0] * 8;
1201 bppshift = mgag200_get_bpp_shift(mdev, format);
1204 scale = ((1 << bppshift) * 3) - 1;
1207 scale = (1 << bppshift) - 1;
1211 RREG_ECRT(3, crtcext3);
1215 xmulctrl = MGA1064_MUL_CTL_8bits;
1218 if (format->depth == 15)
1219 xmulctrl = MGA1064_MUL_CTL_15bits;
1221 xmulctrl = MGA1064_MUL_CTL_16bits;
1224 xmulctrl = MGA1064_MUL_CTL_24bits;
1227 xmulctrl = MGA1064_MUL_CTL_32_24bits;
1230 /* BUG: We should have caught this problem already. */
1231 drm_WARN_ON(dev, "invalid format depth\n");
1235 crtcext3 &= ~GENMASK(2, 0);
1238 WREG_DAC(MGA1064_MUL_CTL, xmulctrl);
1246 /* GCTL6 should be 0x05, but we configure memmapsl to 0xb8000 (text mode),
1247 * so that it doesn't hang when running kexec/kdump on G200_SE rev42.
1253 WREG_ECRT(3, crtcext3);
1256 static void mgag200_g200er_reset_tagfifo(struct mga_device *mdev)
1258 static uint32_t RESET_FLAG = 0x00200000; /* undocumented magic value */
1261 memctl = RREG32(MGAREG_MEMCTL);
1263 memctl |= RESET_FLAG;
1264 WREG32(MGAREG_MEMCTL, memctl);
1268 memctl &= ~RESET_FLAG;
1269 WREG32(MGAREG_MEMCTL, memctl);
1272 static void mgag200_g200se_set_hiprilvl(struct mga_device *mdev,
1273 const struct drm_display_mode *mode,
1274 const struct drm_framebuffer *fb)
1276 u32 unique_rev_id = mdev->model.g200se.unique_rev_id;
1277 unsigned int hiprilvl;
1280 if (unique_rev_id >= 0x04) {
1282 } else if (unique_rev_id >= 0x02) {
1286 if (fb->format->cpp[0] * 8 > 16)
1288 else if (fb->format->cpp[0] * 8 > 8)
1293 mb = (mode->clock * bpp) / 1000;
1307 } else if (unique_rev_id >= 0x01) {
1313 crtcext6 = hiprilvl; /* implicitly sets maxhipri to 0 */
1315 WREG_ECRT(0x06, crtcext6);
1318 static void mgag200_g200ev_set_hiprilvl(struct mga_device *mdev)
1320 WREG_ECRT(0x06, 0x00);
1323 static void mgag200_enable_display(struct mga_device *mdev)
1325 u8 seq0, seq1, crtcext1;
1327 RREG_SEQ(0x00, seq0);
1328 seq0 |= MGAREG_SEQ0_SYNCRST |
1329 MGAREG_SEQ0_ASYNCRST;
1330 WREG_SEQ(0x00, seq0);
1333 * TODO: replace busy waiting with vblank IRQ; put
1334 * msleep(50) before changing SCROFF
1336 mga_wait_vsync(mdev);
1337 mga_wait_busy(mdev);
1339 RREG_SEQ(0x01, seq1);
1340 seq1 &= ~MGAREG_SEQ1_SCROFF;
1341 WREG_SEQ(0x01, seq1);
1345 RREG_ECRT(0x01, crtcext1);
1346 crtcext1 &= ~MGAREG_CRTCEXT1_VSYNCOFF;
1347 crtcext1 &= ~MGAREG_CRTCEXT1_HSYNCOFF;
1348 WREG_ECRT(0x01, crtcext1);
1351 static void mgag200_disable_display(struct mga_device *mdev)
1353 u8 seq0, seq1, crtcext1;
1355 RREG_SEQ(0x00, seq0);
1356 seq0 &= ~MGAREG_SEQ0_SYNCRST;
1357 WREG_SEQ(0x00, seq0);
1360 * TODO: replace busy waiting with vblank IRQ; put
1361 * msleep(50) before changing SCROFF
1363 mga_wait_vsync(mdev);
1364 mga_wait_busy(mdev);
1366 RREG_SEQ(0x01, seq1);
1367 seq1 |= MGAREG_SEQ1_SCROFF;
1368 WREG_SEQ(0x01, seq1);
1372 RREG_ECRT(0x01, crtcext1);
1373 crtcext1 |= MGAREG_CRTCEXT1_VSYNCOFF |
1374 MGAREG_CRTCEXT1_HSYNCOFF;
1375 WREG_ECRT(0x01, crtcext1);
1382 static int mga_vga_get_modes(struct drm_connector *connector)
1384 struct mga_connector *mga_connector = to_mga_connector(connector);
1388 edid = drm_get_edid(connector, &mga_connector->i2c->adapter);
1390 drm_connector_update_edid_property(connector, edid);
1391 ret = drm_add_edid_modes(connector, edid);
1397 static uint32_t mga_vga_calculate_mode_bandwidth(struct drm_display_mode *mode,
1400 uint32_t total_area, divisor;
1401 uint64_t active_area, pixels_per_second, bandwidth;
1402 uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8;
1406 if (!mode->htotal || !mode->vtotal || !mode->clock)
1409 active_area = mode->hdisplay * mode->vdisplay;
1410 total_area = mode->htotal * mode->vtotal;
1412 pixels_per_second = active_area * mode->clock * 1000;
1413 do_div(pixels_per_second, total_area);
1415 bandwidth = pixels_per_second * bytes_per_pixel * 100;
1416 do_div(bandwidth, divisor);
1418 return (uint32_t)(bandwidth);
1421 #define MODE_BANDWIDTH MODE_BAD
1423 static enum drm_mode_status mga_vga_mode_valid(struct drm_connector *connector,
1424 struct drm_display_mode *mode)
1426 struct drm_device *dev = connector->dev;
1427 struct mga_device *mdev = to_mga_device(dev);
1430 if (IS_G200_SE(mdev)) {
1431 u32 unique_rev_id = mdev->model.g200se.unique_rev_id;
1433 if (unique_rev_id == 0x01) {
1434 if (mode->hdisplay > 1600)
1435 return MODE_VIRTUAL_X;
1436 if (mode->vdisplay > 1200)
1437 return MODE_VIRTUAL_Y;
1438 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1440 return MODE_BANDWIDTH;
1441 } else if (unique_rev_id == 0x02) {
1442 if (mode->hdisplay > 1920)
1443 return MODE_VIRTUAL_X;
1444 if (mode->vdisplay > 1200)
1445 return MODE_VIRTUAL_Y;
1446 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1448 return MODE_BANDWIDTH;
1450 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1452 return MODE_BANDWIDTH;
1454 } else if (mdev->type == G200_WB) {
1455 if (mode->hdisplay > 1280)
1456 return MODE_VIRTUAL_X;
1457 if (mode->vdisplay > 1024)
1458 return MODE_VIRTUAL_Y;
1459 if (mga_vga_calculate_mode_bandwidth(mode, bpp) >
1461 return MODE_BANDWIDTH;
1462 } else if (mdev->type == G200_EV &&
1463 (mga_vga_calculate_mode_bandwidth(mode, bpp)
1464 > (32700 * 1024))) {
1465 return MODE_BANDWIDTH;
1466 } else if (mdev->type == G200_EH &&
1467 (mga_vga_calculate_mode_bandwidth(mode, bpp)
1468 > (37500 * 1024))) {
1469 return MODE_BANDWIDTH;
1470 } else if (mdev->type == G200_ER &&
1471 (mga_vga_calculate_mode_bandwidth(mode,
1472 bpp) > (55000 * 1024))) {
1473 return MODE_BANDWIDTH;
1476 if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 ||
1477 (mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) {
1478 return MODE_H_ILLEGAL;
1481 if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 ||
1482 mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 ||
1483 mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 ||
1484 mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) {
1488 /* Validate the mode input by the user */
1489 if (connector->cmdline_mode.specified) {
1490 if (connector->cmdline_mode.bpp_specified)
1491 bpp = connector->cmdline_mode.bpp;
1494 if ((mode->hdisplay * mode->vdisplay * (bpp/8)) > mdev->vram_fb_available) {
1495 if (connector->cmdline_mode.specified)
1496 connector->cmdline_mode.specified = false;
1503 static void mga_connector_destroy(struct drm_connector *connector)
1505 struct mga_connector *mga_connector = to_mga_connector(connector);
1506 mgag200_i2c_destroy(mga_connector->i2c);
1507 drm_connector_cleanup(connector);
1510 static const struct drm_connector_helper_funcs mga_vga_connector_helper_funcs = {
1511 .get_modes = mga_vga_get_modes,
1512 .mode_valid = mga_vga_mode_valid,
1515 static const struct drm_connector_funcs mga_vga_connector_funcs = {
1516 .reset = drm_atomic_helper_connector_reset,
1517 .fill_modes = drm_helper_probe_single_connector_modes,
1518 .destroy = mga_connector_destroy,
1519 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1520 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1523 static int mgag200_vga_connector_init(struct mga_device *mdev)
1525 struct drm_device *dev = &mdev->base;
1526 struct mga_connector *mconnector = &mdev->connector;
1527 struct drm_connector *connector = &mconnector->base;
1528 struct mga_i2c_chan *i2c;
1531 i2c = mgag200_i2c_create(dev);
1533 drm_warn(dev, "failed to add DDC bus\n");
1535 ret = drm_connector_init_with_ddc(dev, connector,
1536 &mga_vga_connector_funcs,
1537 DRM_MODE_CONNECTOR_VGA,
1540 goto err_mgag200_i2c_destroy;
1541 drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs);
1543 mconnector->i2c = i2c;
1547 err_mgag200_i2c_destroy:
1548 mgag200_i2c_destroy(i2c);
1553 * Simple Display Pipe
1556 static enum drm_mode_status
1557 mgag200_simple_display_pipe_mode_valid(struct drm_simple_display_pipe *pipe,
1558 const struct drm_display_mode *mode)
1564 mgag200_handle_damage(struct mga_device *mdev, struct drm_framebuffer *fb,
1565 struct drm_rect *clip)
1567 struct drm_device *dev = &mdev->base;
1570 vmap = drm_gem_shmem_vmap(fb->obj[0]);
1571 if (drm_WARN_ON(dev, !vmap))
1572 return; /* BUG: SHMEM BO should always be vmapped */
1574 drm_fb_memcpy_dstclip(mdev->vram, vmap, fb, clip);
1576 drm_gem_shmem_vunmap(fb->obj[0], vmap);
1578 /* Always scanout image at VRAM offset 0 */
1579 mgag200_set_startadd(mdev, (u32)0);
1580 mgag200_set_offset(mdev, fb);
1584 mgag200_simple_display_pipe_enable(struct drm_simple_display_pipe *pipe,
1585 struct drm_crtc_state *crtc_state,
1586 struct drm_plane_state *plane_state)
1588 struct drm_crtc *crtc = &pipe->crtc;
1589 struct drm_device *dev = crtc->dev;
1590 struct mga_device *mdev = to_mga_device(dev);
1591 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
1592 struct drm_framebuffer *fb = plane_state->fb;
1593 struct drm_rect fullscreen = {
1600 if (mdev->type == G200_WB || mdev->type == G200_EW3)
1601 mgag200_g200wb_hold_bmc(mdev);
1603 mgag200_set_format_regs(mdev, fb);
1604 mgag200_set_mode_regs(mdev, adjusted_mode);
1605 mgag200_crtc_set_plls(mdev, adjusted_mode->clock);
1607 if (mdev->type == G200_ER)
1608 mgag200_g200er_reset_tagfifo(mdev);
1610 if (IS_G200_SE(mdev))
1611 mgag200_g200se_set_hiprilvl(mdev, adjusted_mode, fb);
1612 else if (mdev->type == G200_EV)
1613 mgag200_g200ev_set_hiprilvl(mdev);
1615 if (mdev->type == G200_WB || mdev->type == G200_EW3)
1616 mgag200_g200wb_release_bmc(mdev);
1618 mga_crtc_load_lut(crtc);
1619 mgag200_enable_display(mdev);
1621 mgag200_handle_damage(mdev, fb, &fullscreen);
1625 mgag200_simple_display_pipe_disable(struct drm_simple_display_pipe *pipe)
1627 struct drm_crtc *crtc = &pipe->crtc;
1628 struct mga_device *mdev = to_mga_device(crtc->dev);
1630 mgag200_disable_display(mdev);
1634 mgag200_simple_display_pipe_check(struct drm_simple_display_pipe *pipe,
1635 struct drm_plane_state *plane_state,
1636 struct drm_crtc_state *crtc_state)
1638 struct drm_plane *plane = plane_state->plane;
1639 struct drm_framebuffer *new_fb = plane_state->fb;
1640 struct drm_framebuffer *fb = NULL;
1646 fb = plane->state->fb;
1648 if (!fb || (fb->format != new_fb->format))
1649 crtc_state->mode_changed = true; /* update PLL settings */
1655 mgag200_simple_display_pipe_update(struct drm_simple_display_pipe *pipe,
1656 struct drm_plane_state *old_state)
1658 struct drm_plane *plane = &pipe->plane;
1659 struct drm_device *dev = plane->dev;
1660 struct mga_device *mdev = to_mga_device(dev);
1661 struct drm_plane_state *state = plane->state;
1662 struct drm_framebuffer *fb = state->fb;
1663 struct drm_rect damage;
1668 if (drm_atomic_helper_damage_merged(old_state, state, &damage))
1669 mgag200_handle_damage(mdev, fb, &damage);
1672 static const struct drm_simple_display_pipe_funcs
1673 mgag200_simple_display_pipe_funcs = {
1674 .mode_valid = mgag200_simple_display_pipe_mode_valid,
1675 .enable = mgag200_simple_display_pipe_enable,
1676 .disable = mgag200_simple_display_pipe_disable,
1677 .check = mgag200_simple_display_pipe_check,
1678 .update = mgag200_simple_display_pipe_update,
1679 .prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb,
1682 static const uint32_t mgag200_simple_display_pipe_formats[] = {
1683 DRM_FORMAT_XRGB8888,
1688 static const uint64_t mgag200_simple_display_pipe_fmtmods[] = {
1689 DRM_FORMAT_MOD_LINEAR,
1690 DRM_FORMAT_MOD_INVALID
1697 static const struct drm_mode_config_funcs mgag200_mode_config_funcs = {
1698 .fb_create = drm_gem_fb_create_with_dirty,
1699 .atomic_check = drm_atomic_helper_check,
1700 .atomic_commit = drm_atomic_helper_commit,
1703 static unsigned int mgag200_preferred_depth(struct mga_device *mdev)
1705 if (IS_G200_SE(mdev) && mdev->vram_fb_available < (2048*1024))
1711 int mgag200_modeset_init(struct mga_device *mdev)
1713 struct drm_device *dev = &mdev->base;
1714 struct drm_connector *connector = &mdev->connector.base;
1715 struct drm_simple_display_pipe *pipe = &mdev->display_pipe;
1716 size_t format_count = ARRAY_SIZE(mgag200_simple_display_pipe_formats);
1719 mdev->bpp_shifts[0] = 0;
1720 mdev->bpp_shifts[1] = 1;
1721 mdev->bpp_shifts[2] = 0;
1722 mdev->bpp_shifts[3] = 2;
1724 mgag200_init_regs(mdev);
1726 ret = drmm_mode_config_init(dev);
1728 drm_err(dev, "drmm_mode_config_init() failed, error %d\n",
1733 dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH;
1734 dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT;
1736 dev->mode_config.preferred_depth = mgag200_preferred_depth(mdev);
1738 dev->mode_config.fb_base = mdev->mc.vram_base;
1740 dev->mode_config.funcs = &mgag200_mode_config_funcs;
1742 ret = mgag200_vga_connector_init(mdev);
1745 "mgag200_vga_connector_init() failed, error %d\n",
1750 ret = drm_simple_display_pipe_init(dev, pipe,
1751 &mgag200_simple_display_pipe_funcs,
1752 mgag200_simple_display_pipe_formats,
1754 mgag200_simple_display_pipe_fmtmods,
1758 "drm_simple_display_pipe_init() failed, error %d\n",
1763 /* FIXME: legacy gamma tables; convert to CRTC state */
1764 drm_mode_crtc_set_gamma_size(&pipe->crtc, MGAG200_LUT_SIZE);
1766 drm_mode_config_reset(dev);