drivers/gpu/drm/meson/meson_venc.c

   1 /*
   2  * Copyright (C) 2016 BayLibre, SAS
   3  * Author: Neil Armstrong <narmstrong@baylibre.com>
   4  * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of the
   9  * License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <drm/drmP.h>
  23 #include "meson_drv.h"
  24 #include "meson_venc.h"
  25 #include "meson_vpp.h"
  26 #include "meson_vclk.h"
  27 #include "meson_registers.h"
  28
  29 /**
  30  * DOC: Video Encoder
  31  *
  32  * VENC Handle the pixels encoding to the output formats.
  33  * We handle the following encodings :
  34  *
  35  * - CVBS Encoding via the ENCI encoder and VDAC digital to analog converter
  36  * - TMDS/HDMI Encoding via ENCI_DIV and ENCP
  37  * - Setup of more clock rates for HDMI modes
  38  *
  39  * What is missing :
  40  *
  41  * - LCD Panel encoding via ENCL
  42  * - TV Panel encoding via ENCT
  43  *
  44  * VENC paths :
  45  *
  46  * .. code::
  47  *
  48  *          _____   _____   ____________________
  49  *   vd1---|     |-|     | | VENC     /---------|----VDAC
  50  *   vd2---| VIU |-| VPP |-|-----ENCI/-ENCI_DVI-|-|
  51  *   osd1--|     |-|     | | \                  | X--HDMI-TX
  52  *   osd2--|_____|-|_____| |  |\-ENCP--ENCP_DVI-|-|
  53  *                         |  |                 |
  54  *                         |  \--ENCL-----------|----LVDS
  55  *                         |____________________|
  56  *
  57  * The ENCI is designed for PAl or NTSC encoding and can go through the VDAC
  58  * directly for CVBS encoding or through the ENCI_DVI encoder for HDMI.
  59  * The ENCP is designed for Progressive encoding but can also generate
  60  * 1080i interlaced pixels, and was initialy desined to encode pixels for
  61  * VDAC to output RGB ou YUV analog outputs.
  62  * It's output is only used through the ENCP_DVI encoder for HDMI.
  63  * The ENCL LVDS encoder is not implemented.
  64  *
  65  * The ENCI and ENCP encoders needs specially defined parameters for each
  66  * supported mode and thus cannot be determined from standard video timings.
  67  *
  68  * The ENCI end ENCP DVI encoders are more generic and can generate any timings
  69  * from the pixel data generated by ENCI or ENCP, so can use the standard video
  70  * timings are source for HW parameters.
  71  */
  72
  73 /* HHI Registers */
  74 #define HHI_VDAC_CNTL0          0x2F4 /* 0xbd offset in data sheet */
  75 #define HHI_VDAC_CNTL1          0x2F8 /* 0xbe offset in data sheet */
  76 #define HHI_HDMI_PHY_CNTL0      0x3a0 /* 0xe8 offset in data sheet */
  77
  78 struct meson_cvbs_enci_mode meson_cvbs_enci_pal = {
  79         .mode_tag = MESON_VENC_MODE_CVBS_PAL,
  80         .hso_begin = 3,
  81         .hso_end = 129,
  82         .vso_even = 3,
  83         .vso_odd = 260,
  84         .macv_max_amp = 7,
  85         .video_prog_mode = 0xff,
  86         .video_mode = 0x13,
  87         .sch_adjust = 0x28,
  88         .yc_delay = 0x343,
  89         .pixel_start = 251,
  90         .pixel_end = 1691,
  91         .top_field_line_start = 22,
  92         .top_field_line_end = 310,
  93         .bottom_field_line_start = 23,
  94         .bottom_field_line_end = 311,
  95         .video_saturation = 9,
  96         .video_contrast = 0,
  97         .video_brightness = 0,
  98         .video_hue = 0,
  99         .analog_sync_adj = 0x8080,
 100 };
 101
 102 struct meson_cvbs_enci_mode meson_cvbs_enci_ntsc = {
 103         .mode_tag = MESON_VENC_MODE_CVBS_NTSC,
 104         .hso_begin = 5,
 105         .hso_end = 129,
 106         .vso_even = 3,
 107         .vso_odd = 260,
 108         .macv_max_amp = 0xb,
 109         .video_prog_mode = 0xf0,
 110         .video_mode = 0x8,
 111         .sch_adjust = 0x20,
 112         .yc_delay = 0x333,
 113         .pixel_start = 227,
 114         .pixel_end = 1667,
 115         .top_field_line_start = 18,
 116         .top_field_line_end = 258,
 117         .bottom_field_line_start = 19,
 118         .bottom_field_line_end = 259,
 119         .video_saturation = 18,
 120         .video_contrast = 3,
 121         .video_brightness = 0,
 122         .video_hue = 0,
 123         .analog_sync_adj = 0x9c00,
 124 };
 125
 126 union meson_hdmi_venc_mode {
 127         struct {
 128                 unsigned int mode_tag;
 129                 unsigned int hso_begin;
 130                 unsigned int hso_end;
 131                 unsigned int vso_even;
 132                 unsigned int vso_odd;
 133                 unsigned int macv_max_amp;
 134                 unsigned int video_prog_mode;
 135                 unsigned int video_mode;
 136                 unsigned int sch_adjust;
 137                 unsigned int yc_delay;
 138                 unsigned int pixel_start;
 139                 unsigned int pixel_end;
 140                 unsigned int top_field_line_start;
 141                 unsigned int top_field_line_end;
 142                 unsigned int bottom_field_line_start;
 143                 unsigned int bottom_field_line_end;
 144         } enci;
 145         struct {
 146                 unsigned int dvi_settings;
 147                 unsigned int video_mode;
 148                 unsigned int video_mode_adv;
 149                 unsigned int video_prog_mode;
 150                 bool video_prog_mode_present;
 151                 unsigned int video_sync_mode;
 152                 bool video_sync_mode_present;
 153                 unsigned int video_yc_dly;
 154                 bool video_yc_dly_present;
 155                 unsigned int video_rgb_ctrl;
 156                 bool video_rgb_ctrl_present;
 157                 unsigned int video_filt_ctrl;
 158                 bool video_filt_ctrl_present;
 159                 unsigned int video_ofld_voav_ofst;
 160                 bool video_ofld_voav_ofst_present;
 161                 unsigned int yfp1_htime;
 162                 unsigned int yfp2_htime;
 163                 unsigned int max_pxcnt;
 164                 unsigned int hspuls_begin;
 165                 unsigned int hspuls_end;
 166                 unsigned int hspuls_switch;
 167                 unsigned int vspuls_begin;
 168                 unsigned int vspuls_end;
 169                 unsigned int vspuls_bline;
 170                 unsigned int vspuls_eline;
 171                 unsigned int eqpuls_begin;
 172                 bool eqpuls_begin_present;
 173                 unsigned int eqpuls_end;
 174                 bool eqpuls_end_present;
 175                 unsigned int eqpuls_bline;
 176                 bool eqpuls_bline_present;
 177                 unsigned int eqpuls_eline;
 178                 bool eqpuls_eline_present;
 179                 unsigned int havon_begin;
 180                 unsigned int havon_end;
 181                 unsigned int vavon_bline;
 182                 unsigned int vavon_eline;
 183                 unsigned int hso_begin;
 184                 unsigned int hso_end;
 185                 unsigned int vso_begin;
 186                 unsigned int vso_end;
 187                 unsigned int vso_bline;
 188                 unsigned int vso_eline;
 189                 bool vso_eline_present;
 190                 unsigned int sy_val;
 191                 bool sy_val_present;
 192                 unsigned int sy2_val;
 193                 bool sy2_val_present;
 194                 unsigned int max_lncnt;
 195         } encp;
 196 };
 197
 198 union meson_hdmi_venc_mode meson_hdmi_enci_mode_480i = {
 199         .enci = {
 200                 .hso_begin = 5,
 201                 .hso_end = 129,
 202                 .vso_even = 3,
 203                 .vso_odd = 260,
 204                 .macv_max_amp = 0x810b,
 205                 .video_prog_mode = 0xf0,
 206                 .video_mode = 0x8,
 207                 .sch_adjust = 0x20,
 208                 .yc_delay = 0,
 209                 .pixel_start = 227,
 210                 .pixel_end = 1667,
 211                 .top_field_line_start = 18,
 212                 .top_field_line_end = 258,
 213                 .bottom_field_line_start = 19,
 214                 .bottom_field_line_end = 259,
 215         },
 216 };
 217
 218 union meson_hdmi_venc_mode meson_hdmi_enci_mode_576i = {
 219         .enci = {
 220                 .hso_begin = 3,
 221                 .hso_end = 129,
 222                 .vso_even = 3,
 223                 .vso_odd = 260,
 224                 .macv_max_amp = 8107,
 225                 .video_prog_mode = 0xff,
 226                 .video_mode = 0x13,
 227                 .sch_adjust = 0x28,
 228                 .yc_delay = 0x333,
 229                 .pixel_start = 251,
 230                 .pixel_end = 1691,
 231                 .top_field_line_start = 22,
 232                 .top_field_line_end = 310,
 233                 .bottom_field_line_start = 23,
 234                 .bottom_field_line_end = 311,
 235         },
 236 };
 237
 238 union meson_hdmi_venc_mode meson_hdmi_encp_mode_480p = {
 239         .encp = {
 240                 .dvi_settings = 0x21,
 241                 .video_mode = 0x4000,
 242                 .video_mode_adv = 0x9,
 243                 .video_prog_mode = 0,
 244                 .video_prog_mode_present = true,
 245                 .video_sync_mode = 7,
 246                 .video_sync_mode_present = true,
 247                 /* video_yc_dly */
 248                 /* video_rgb_ctrl */
 249                 .video_filt_ctrl = 0x2052,
 250                 .video_filt_ctrl_present = true,
 251                 /* video_ofld_voav_ofst */
 252                 .yfp1_htime = 244,
 253                 .yfp2_htime = 1630,
 254                 .max_pxcnt = 1715,
 255                 .hspuls_begin = 0x22,
 256                 .hspuls_end = 0xa0,
 257                 .hspuls_switch = 88,
 258                 .vspuls_begin = 0,
 259                 .vspuls_end = 1589,
 260                 .vspuls_bline = 0,
 261                 .vspuls_eline = 5,
 262                 .havon_begin = 249,
 263                 .havon_end = 1689,
 264                 .vavon_bline = 42,
 265                 .vavon_eline = 521,
 266                 /* eqpuls_begin */
 267                 /* eqpuls_end */
 268                 /* eqpuls_bline */
 269                 /* eqpuls_eline */
 270                 .hso_begin = 3,
 271                 .hso_end = 5,
 272                 .vso_begin = 3,
 273                 .vso_end = 5,
 274                 .vso_bline = 0,
 275                 /* vso_eline */
 276                 .sy_val = 8,
 277                 .sy_val_present = true,
 278                 .sy2_val = 0x1d8,
 279                 .sy2_val_present = true,
 280                 .max_lncnt = 524,
 281         },
 282 };
 283
 284 union meson_hdmi_venc_mode meson_hdmi_encp_mode_576p = {
 285         .encp = {
 286                 .dvi_settings = 0x21,
 287                 .video_mode = 0x4000,
 288                 .video_mode_adv = 0x9,
 289                 .video_prog_mode = 0,
 290                 .video_prog_mode_present = true,
 291                 .video_sync_mode = 7,
 292                 .video_sync_mode_present = true,
 293                 /* video_yc_dly */
 294                 /* video_rgb_ctrl */
 295                 .video_filt_ctrl = 0x52,
 296                 .video_filt_ctrl_present = true,
 297                 /* video_ofld_voav_ofst */
 298                 .yfp1_htime = 235,
 299                 .yfp2_htime = 1674,
 300                 .max_pxcnt = 1727,
 301                 .hspuls_begin = 0,
 302                 .hspuls_end = 0x80,
 303                 .hspuls_switch = 88,
 304                 .vspuls_begin = 0,
 305                 .vspuls_end = 1599,
 306                 .vspuls_bline = 0,
 307                 .vspuls_eline = 4,
 308                 .havon_begin = 235,
 309                 .havon_end = 1674,
 310                 .vavon_bline = 44,
 311                 .vavon_eline = 619,
 312                 /* eqpuls_begin */
 313                 /* eqpuls_end */
 314                 /* eqpuls_bline */
 315                 /* eqpuls_eline */
 316                 .hso_begin = 0x80,
 317                 .hso_end = 0,
 318                 .vso_begin = 0,
 319                 .vso_end = 5,
 320                 .vso_bline = 0,
 321                 /* vso_eline */
 322                 .sy_val = 8,
 323                 .sy_val_present = true,
 324                 .sy2_val = 0x1d8,
 325                 .sy2_val_present = true,
 326                 .max_lncnt = 624,
 327         },
 328 };
 329
 330 union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p60 = {
 331         .encp = {
 332                 .dvi_settings = 0x2029,
 333                 .video_mode = 0x4040,
 334                 .video_mode_adv = 0x19,
 335                 /* video_prog_mode */
 336                 /* video_sync_mode */
 337                 /* video_yc_dly */
 338                 /* video_rgb_ctrl */
 339                 /* video_filt_ctrl */
 340                 /* video_ofld_voav_ofst */
 341                 .yfp1_htime = 648,
 342                 .yfp2_htime = 3207,
 343                 .max_pxcnt = 3299,
 344                 .hspuls_begin = 80,
 345                 .hspuls_end = 240,
 346                 .hspuls_switch = 80,
 347                 .vspuls_begin = 688,
 348                 .vspuls_end = 3248,
 349                 .vspuls_bline = 4,
 350                 .vspuls_eline = 8,
 351                 .havon_begin = 648,
 352                 .havon_end = 3207,
 353                 .vavon_bline = 29,
 354                 .vavon_eline = 748,
 355                 /* eqpuls_begin */
 356                 /* eqpuls_end */
 357                 /* eqpuls_bline */
 358                 /* eqpuls_eline */
 359                 .hso_begin = 256,
 360                 .hso_end = 168,
 361                 .vso_begin = 168,
 362                 .vso_end = 256,
 363                 .vso_bline = 0,
 364                 .vso_eline = 5,
 365                 .vso_eline_present = true,
 366                 /* sy_val */
 367                 /* sy2_val */
 368                 .max_lncnt = 749,
 369         },
 370 };
 371
 372 union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p50 = {
 373         .encp = {
 374                 .dvi_settings = 0x202d,
 375                 .video_mode = 0x4040,
 376                 .video_mode_adv = 0x19,
 377                 .video_prog_mode = 0x100,
 378                 .video_prog_mode_present = true,
 379                 .video_sync_mode = 0x407,
 380                 .video_sync_mode_present = true,
 381                 .video_yc_dly = 0,
 382                 .video_yc_dly_present = true,
 383                 /* video_rgb_ctrl */
 384                 /* video_filt_ctrl */
 385                 /* video_ofld_voav_ofst */
 386                 .yfp1_htime = 648,
 387                 .yfp2_htime = 3207,
 388                 .max_pxcnt = 3959,
 389                 .hspuls_begin = 80,
 390                 .hspuls_end = 240,
 391                 .hspuls_switch = 80,
 392                 .vspuls_begin = 688,
 393                 .vspuls_end = 3248,
 394                 .vspuls_bline = 4,
 395                 .vspuls_eline = 8,
 396                 .havon_begin = 648,
 397                 .havon_end = 3207,
 398                 .vavon_bline = 29,
 399                 .vavon_eline = 748,
 400                 /* eqpuls_begin */
 401                 /* eqpuls_end */
 402                 /* eqpuls_bline */
 403                 /* eqpuls_eline */
 404                 .hso_begin = 128,
 405                 .hso_end = 208,
 406                 .vso_begin = 128,
 407                 .vso_end = 128,
 408                 .vso_bline = 0,
 409                 .vso_eline = 5,
 410                 .vso_eline_present = true,
 411                 /* sy_val */
 412                 /* sy2_val */
 413                 .max_lncnt = 749,
 414         },
 415 };
 416
 417 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i60 = {
 418         .encp = {
 419                 .dvi_settings = 0x2029,
 420                 .video_mode = 0x5ffc,
 421                 .video_mode_adv = 0x19,
 422                 .video_prog_mode = 0x100,
 423                 .video_prog_mode_present = true,
 424                 .video_sync_mode = 0x207,
 425                 .video_sync_mode_present = true,
 426                 /* video_yc_dly */
 427                 /* video_rgb_ctrl */
 428                 /* video_filt_ctrl */
 429                 .video_ofld_voav_ofst = 0x11,
 430                 .video_ofld_voav_ofst_present = true,
 431                 .yfp1_htime = 516,
 432                 .yfp2_htime = 4355,
 433                 .max_pxcnt = 4399,
 434                 .hspuls_begin = 88,
 435                 .hspuls_end = 264,
 436                 .hspuls_switch = 88,
 437                 .vspuls_begin = 440,
 438                 .vspuls_end = 2200,
 439                 .vspuls_bline = 0,
 440                 .vspuls_eline = 4,
 441                 .havon_begin = 516,
 442                 .havon_end = 4355,
 443                 .vavon_bline = 20,
 444                 .vavon_eline = 559,
 445                 .eqpuls_begin = 2288,
 446                 .eqpuls_begin_present = true,
 447                 .eqpuls_end = 2464,
 448                 .eqpuls_end_present = true,
 449                 .eqpuls_bline = 0,
 450                 .eqpuls_bline_present = true,
 451                 .eqpuls_eline = 4,
 452                 .eqpuls_eline_present = true,
 453                 .hso_begin = 264,
 454                 .hso_end = 176,
 455                 .vso_begin = 88,
 456                 .vso_end = 88,
 457                 .vso_bline = 0,
 458                 .vso_eline = 5,
 459                 .vso_eline_present = true,
 460                 /* sy_val */
 461                 /* sy2_val */
 462                 .max_lncnt = 1124,
 463         },
 464 };
 465
 466 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i50 = {
 467         .encp = {
 468                 .dvi_settings = 0x202d,
 469                 .video_mode = 0x5ffc,
 470                 .video_mode_adv = 0x19,
 471                 .video_prog_mode = 0x100,
 472                 .video_prog_mode_present = true,
 473                 .video_sync_mode = 0x7,
 474                 .video_sync_mode_present = true,
 475                 /* video_yc_dly */
 476                 /* video_rgb_ctrl */
 477                 /* video_filt_ctrl */
 478                 .video_ofld_voav_ofst = 0x11,
 479                 .video_ofld_voav_ofst_present = true,
 480                 .yfp1_htime = 526,
 481                 .yfp2_htime = 4365,
 482                 .max_pxcnt = 5279,
 483                 .hspuls_begin = 88,
 484                 .hspuls_end = 264,
 485                 .hspuls_switch = 88,
 486                 .vspuls_begin = 440,
 487                 .vspuls_end = 2200,
 488                 .vspuls_bline = 0,
 489                 .vspuls_eline = 4,
 490                 .havon_begin = 526,
 491                 .havon_end = 4365,
 492                 .vavon_bline = 20,
 493                 .vavon_eline = 559,
 494                 .eqpuls_begin = 2288,
 495                 .eqpuls_begin_present = true,
 496                 .eqpuls_end = 2464,
 497                 .eqpuls_end_present = true,
 498                 .eqpuls_bline = 0,
 499                 .eqpuls_bline_present = true,
 500                 .eqpuls_eline = 4,
 501                 .eqpuls_eline_present = true,
 502                 .hso_begin = 142,
 503                 .hso_end = 230,
 504                 .vso_begin = 142,
 505                 .vso_end = 142,
 506                 .vso_bline = 0,
 507                 .vso_eline = 5,
 508                 .vso_eline_present = true,
 509                 /* sy_val */
 510                 /* sy2_val */
 511                 .max_lncnt = 1124,
 512         },
 513 };
 514
 515 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p24 = {
 516         .encp = {
 517                 .dvi_settings = 0xd,
 518                 .video_mode = 0x4040,
 519                 .video_mode_adv = 0x18,
 520                 .video_prog_mode = 0x100,
 521                 .video_prog_mode_present = true,
 522                 .video_sync_mode = 0x7,
 523                 .video_sync_mode_present = true,
 524                 .video_yc_dly = 0,
 525                 .video_yc_dly_present = true,
 526                 .video_rgb_ctrl = 2,
 527                 .video_rgb_ctrl_present = true,
 528                 .video_filt_ctrl = 0x1052,
 529                 .video_filt_ctrl_present = true,
 530                 /* video_ofld_voav_ofst */
 531                 .yfp1_htime = 271,
 532                 .yfp2_htime = 2190,
 533                 .max_pxcnt = 2749,
 534                 .hspuls_begin = 44,
 535                 .hspuls_end = 132,
 536                 .hspuls_switch = 44,
 537                 .vspuls_begin = 220,
 538                 .vspuls_end = 2140,
 539                 .vspuls_bline = 0,
 540                 .vspuls_eline = 4,
 541                 .havon_begin = 271,
 542                 .havon_end = 2190,
 543                 .vavon_bline = 41,
 544                 .vavon_eline = 1120,
 545                 /* eqpuls_begin */
 546                 /* eqpuls_end */
 547                 .eqpuls_bline = 0,
 548                 .eqpuls_bline_present = true,
 549                 .eqpuls_eline = 4,
 550                 .eqpuls_eline_present = true,
 551                 .hso_begin = 79,
 552                 .hso_end = 123,
 553                 .vso_begin = 79,
 554                 .vso_end = 79,
 555                 .vso_bline = 0,
 556                 .vso_eline = 5,
 557                 .vso_eline_present = true,
 558                 /* sy_val */
 559                 /* sy2_val */
 560                 .max_lncnt = 1124,
 561         },
 562 };
 563
 564 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p30 = {
 565         .encp = {
 566                 .dvi_settings = 0x1,
 567                 .video_mode = 0x4040,
 568                 .video_mode_adv = 0x18,
 569                 .video_prog_mode = 0x100,
 570                 .video_prog_mode_present = true,
 571                 /* video_sync_mode */
 572                 /* video_yc_dly */
 573                 /* video_rgb_ctrl */
 574                 .video_filt_ctrl = 0x1052,
 575                 .video_filt_ctrl_present = true,
 576                 /* video_ofld_voav_ofst */
 577                 .yfp1_htime = 140,
 578                 .yfp2_htime = 2060,
 579                 .max_pxcnt = 2199,
 580                 .hspuls_begin = 2156,
 581                 .hspuls_end = 44,
 582                 .hspuls_switch = 44,
 583                 .vspuls_begin = 140,
 584                 .vspuls_end = 2059,
 585                 .vspuls_bline = 0,
 586                 .vspuls_eline = 4,
 587                 .havon_begin = 148,
 588                 .havon_end = 2067,
 589                 .vavon_bline = 41,
 590                 .vavon_eline = 1120,
 591                 /* eqpuls_begin */
 592                 /* eqpuls_end */
 593                 /* eqpuls_bline */
 594                 /* eqpuls_eline */
 595                 .hso_begin = 44,
 596                 .hso_end = 2156,
 597                 .vso_begin = 2100,
 598                 .vso_end = 2164,
 599                 .vso_bline = 0,
 600                 .vso_eline = 5,
 601                 .vso_eline_present = true,
 602                 /* sy_val */
 603                 /* sy2_val */
 604                 .max_lncnt = 1124,
 605         },
 606 };
 607
 608 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p50 = {
 609         .encp = {
 610                 .dvi_settings = 0xd,
 611                 .video_mode = 0x4040,
 612                 .video_mode_adv = 0x18,
 613                 .video_prog_mode = 0x100,
 614                 .video_prog_mode_present = true,
 615                 .video_sync_mode = 0x7,
 616                 .video_sync_mode_present = true,
 617                 .video_yc_dly = 0,
 618                 .video_yc_dly_present = true,
 619                 .video_rgb_ctrl = 2,
 620                 .video_rgb_ctrl_present = true,
 621                 /* video_filt_ctrl */
 622                 /* video_ofld_voav_ofst */
 623                 .yfp1_htime = 271,
 624                 .yfp2_htime = 2190,
 625                 .max_pxcnt = 2639,
 626                 .hspuls_begin = 44,
 627                 .hspuls_end = 132,
 628                 .hspuls_switch = 44,
 629                 .vspuls_begin = 220,
 630                 .vspuls_end = 2140,
 631                 .vspuls_bline = 0,
 632                 .vspuls_eline = 4,
 633                 .havon_begin = 271,
 634                 .havon_end = 2190,
 635                 .vavon_bline = 41,
 636                 .vavon_eline = 1120,
 637                 /* eqpuls_begin */
 638                 /* eqpuls_end */
 639                 .eqpuls_bline = 0,
 640                 .eqpuls_bline_present = true,
 641                 .eqpuls_eline = 4,
 642                 .eqpuls_eline_present = true,
 643                 .hso_begin = 79,
 644                 .hso_end = 123,
 645                 .vso_begin = 79,
 646                 .vso_end = 79,
 647                 .vso_bline = 0,
 648                 .vso_eline = 5,
 649                 .vso_eline_present = true,
 650                 /* sy_val */
 651                 /* sy2_val */
 652                 .max_lncnt = 1124,
 653         },
 654 };
 655
 656 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p60 = {
 657         .encp = {
 658                 .dvi_settings = 0x1,
 659                 .video_mode = 0x4040,
 660                 .video_mode_adv = 0x18,
 661                 .video_prog_mode = 0x100,
 662                 .video_prog_mode_present = true,
 663                 /* video_sync_mode */
 664                 /* video_yc_dly */
 665                 /* video_rgb_ctrl */
 666                 .video_filt_ctrl = 0x1052,
 667                 .video_filt_ctrl_present = true,
 668                 /* video_ofld_voav_ofst */
 669                 .yfp1_htime = 140,
 670                 .yfp2_htime = 2060,
 671                 .max_pxcnt = 2199,
 672                 .hspuls_begin = 2156,
 673                 .hspuls_end = 44,
 674                 .hspuls_switch = 44,
 675                 .vspuls_begin = 140,
 676                 .vspuls_end = 2059,
 677                 .vspuls_bline = 0,
 678                 .vspuls_eline = 4,
 679                 .havon_begin = 148,
 680                 .havon_end = 2067,
 681                 .vavon_bline = 41,
 682                 .vavon_eline = 1120,
 683                 /* eqpuls_begin */
 684                 /* eqpuls_end */
 685                 /* eqpuls_bline */
 686                 /* eqpuls_eline */
 687                 .hso_begin = 44,
 688                 .hso_end = 2156,
 689                 .vso_begin = 2100,
 690                 .vso_end = 2164,
 691                 .vso_bline = 0,
 692                 .vso_eline = 5,
 693                 .vso_eline_present = true,
 694                 /* sy_val */
 695                 /* sy2_val */
 696                 .max_lncnt = 1124,
 697         },
 698 };
 699
 700 struct meson_hdmi_venc_vic_mode {
 701         unsigned int vic;
 702         union meson_hdmi_venc_mode *mode;
 703 } meson_hdmi_venc_vic_modes[] = {
 704         { 6, &meson_hdmi_enci_mode_480i },
 705         { 7, &meson_hdmi_enci_mode_480i },
 706         { 21, &meson_hdmi_enci_mode_576i },
 707         { 22, &meson_hdmi_enci_mode_576i },
 708         { 2, &meson_hdmi_encp_mode_480p },
 709         { 3, &meson_hdmi_encp_mode_480p },
 710         { 17, &meson_hdmi_encp_mode_576p },
 711         { 18, &meson_hdmi_encp_mode_576p },
 712         { 4, &meson_hdmi_encp_mode_720p60 },
 713         { 19, &meson_hdmi_encp_mode_720p50 },
 714         { 5, &meson_hdmi_encp_mode_1080i60 },
 715         { 20, &meson_hdmi_encp_mode_1080i50 },
 716         { 32, &meson_hdmi_encp_mode_1080p24 },
 717         { 33, &meson_hdmi_encp_mode_1080p50 },
 718         { 34, &meson_hdmi_encp_mode_1080p30 },
 719         { 31, &meson_hdmi_encp_mode_1080p50 },
 720         { 16, &meson_hdmi_encp_mode_1080p60 },
 721         { 0, NULL}, /* sentinel */
 722 };
 723
 724 static signed int to_signed(unsigned int a)
 725 {
 726         if (a <= 7)
 727                 return a;
 728         else
 729                 return a - 16;
 730 }
 731
 732 static unsigned long modulo(unsigned long a, unsigned long b)
 733 {
 734         if (a >= b)
 735                 return a - b;
 736         else
 737                 return a;
 738 }
 739
 740 bool meson_venc_hdmi_supported_vic(int vic)
 741 {
 742         struct meson_hdmi_venc_vic_mode *vmode = meson_hdmi_venc_vic_modes;
 743
 744         while (vmode->vic && vmode->mode) {
 745                 if (vmode->vic == vic)
 746                         return true;
 747                 vmode++;
 748         }
 749
 750         return false;
 751 }
 752 EXPORT_SYMBOL_GPL(meson_venc_hdmi_supported_vic);
 753
 754 static union meson_hdmi_venc_mode *meson_venc_hdmi_get_vic_vmode(int vic)
 755 {
 756         struct meson_hdmi_venc_vic_mode *vmode = meson_hdmi_venc_vic_modes;
 757
 758         while (vmode->vic && vmode->mode) {
 759                 if (vmode->vic == vic)
 760                         return vmode->mode;
 761                 vmode++;
 762         }
 763
 764         return NULL;
 765 }
 766
 767 bool meson_venc_hdmi_venc_repeat(int vic)
 768 {
 769         /* Repeat VENC pixels for 480/576i/p, 720p50/60 and 1080p50/60 */
 770         if (vic == 6 || vic == 7 || /* 480i */
 771             vic == 21 || vic == 22 || /* 576i */
 772             vic == 17 || vic == 18 || /* 576p */
 773             vic == 2 || vic == 3 || /* 480p */
 774             vic == 4 || /* 720p60 */
 775             vic == 19 || /* 720p50 */
 776             vic == 5 || /* 1080i60 */
 777             vic == 20)  /* 1080i50 */
 778                 return true;
 779
 780         return false;
 781 }
 782 EXPORT_SYMBOL_GPL(meson_venc_hdmi_venc_repeat);
 783
 784 void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
 785                               struct drm_display_mode *mode)
 786 {
 787         union meson_hdmi_venc_mode *vmode = NULL;
 788         bool use_enci = false;
 789         bool venc_repeat = false;
 790         bool hdmi_repeat = false;
 791         unsigned int venc_hdmi_latency = 2;
 792         unsigned long total_pixels_venc = 0;
 793         unsigned long active_pixels_venc = 0;
 794         unsigned long front_porch_venc = 0;
 795         unsigned long hsync_pixels_venc = 0;
 796         unsigned long de_h_begin = 0;
 797         unsigned long de_h_end = 0;
 798         unsigned long de_v_begin_even = 0;
 799         unsigned long de_v_end_even = 0;
 800         unsigned long de_v_begin_odd = 0;
 801         unsigned long de_v_end_odd = 0;
 802         unsigned long hs_begin = 0;
 803         unsigned long hs_end = 0;
 804         unsigned long vs_adjust = 0;
 805         unsigned long vs_bline_evn = 0;
 806         unsigned long vs_eline_evn = 0;
 807         unsigned long vs_bline_odd = 0;
 808         unsigned long vs_eline_odd = 0;
 809         unsigned long vso_begin_evn = 0;
 810         unsigned long vso_begin_odd = 0;
 811         unsigned int eof_lines;
 812         unsigned int sof_lines;
 813         unsigned int vsync_lines;
 814
 815         vmode = meson_venc_hdmi_get_vic_vmode(vic);
 816         if (!vmode) {
 817                 dev_err(priv->dev, "%s: Fatal Error, unsupported vic %d\n",
 818                         __func__, vic);
 819                 return;
 820         }
 821
 822         /* Use VENCI for 480i and 576i and double HDMI pixels */
 823         if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
 824                 hdmi_repeat = true;
 825                 use_enci = true;
 826                 venc_hdmi_latency = 1;
 827         }
 828
 829         /* Repeat VENC pixels for 480/576i/p, 720p50/60 and 1080p50/60 */
 830         if (meson_venc_hdmi_venc_repeat(vic))
 831                 venc_repeat = true;
 832
 833         eof_lines = mode->vsync_start - mode->vdisplay;
 834         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 835                 eof_lines /= 2;
 836         sof_lines = mode->vtotal - mode->vsync_end;
 837         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 838                 sof_lines /= 2;
 839         vsync_lines = mode->vsync_end - mode->vsync_start;
 840         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 841                 vsync_lines /= 2;
 842
 843         total_pixels_venc = mode->htotal;
 844         if (hdmi_repeat)
 845                 total_pixels_venc /= 2;
 846         if (venc_repeat)
 847                 total_pixels_venc *= 2;
 848
 849         active_pixels_venc = mode->hdisplay;
 850         if (hdmi_repeat)
 851                 active_pixels_venc /= 2;
 852         if (venc_repeat)
 853                 active_pixels_venc *= 2;
 854
 855         front_porch_venc = (mode->hsync_start - mode->hdisplay);
 856         if (hdmi_repeat)
 857                 front_porch_venc /= 2;
 858         if (venc_repeat)
 859                 front_porch_venc *= 2;
 860
 861         hsync_pixels_venc = (mode->hsync_end - mode->hsync_start);
 862         if (hdmi_repeat)
 863                 hsync_pixels_venc /= 2;
 864         if (venc_repeat)
 865                 hsync_pixels_venc *= 2;
 866
 867         /* Disable VDACs */
 868         writel_bits_relaxed(0x1f, 0x1f,
 869                         priv->io_base + _REG(VENC_VDAC_SETTING));
 870
 871         writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
 872         writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
 873
 874         if (use_enci) {
 875                 unsigned int lines_f0;
 876                 unsigned int lines_f1;
 877
 878                 /* CVBS Filter settings */
 879                 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL));
 880                 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL2));
 881
 882                 /* Digital Video Select : Interlace, clk27 clk, external */
 883                 writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING));
 884
 885                 /* Reset Video Mode */
 886                 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE));
 887                 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
 888
 889                 /* Horizontal sync signal output */
 890                 writel_relaxed(vmode->enci.hso_begin,
 891                                 priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN));
 892                 writel_relaxed(vmode->enci.hso_end,
 893                                 priv->io_base + _REG(ENCI_SYNC_HSO_END));
 894
 895                 /* Vertical Sync lines */
 896                 writel_relaxed(vmode->enci.vso_even,
 897                                 priv->io_base + _REG(ENCI_SYNC_VSO_EVNLN));
 898                 writel_relaxed(vmode->enci.vso_odd,
 899                                 priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN));
 900
 901                 /* Macrovision max amplitude change */
 902                 writel_relaxed(vmode->enci.macv_max_amp,
 903                                 priv->io_base + _REG(ENCI_MACV_MAX_AMP));
 904
 905                 /* Video mode */
 906                 writel_relaxed(vmode->enci.video_prog_mode,
 907                                 priv->io_base + _REG(VENC_VIDEO_PROG_MODE));
 908                 writel_relaxed(vmode->enci.video_mode,
 909                                 priv->io_base + _REG(ENCI_VIDEO_MODE));
 910
 911                 /* Advanced Video Mode :
 912                  * Demux shifting 0x2
 913                  * Blank line end at line17/22
 914                  * High bandwidth Luma Filter
 915                  * Low bandwidth Chroma Filter
 916                  * Bypass luma low pass filter
 917                  * No macrovision on CSYNC
 918                  */
 919                 writel_relaxed(0x26, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
 920
 921                 writel(vmode->enci.sch_adjust,
 922                                 priv->io_base + _REG(ENCI_VIDEO_SCH));
 923
 924                 /* Sync mode : MASTER Master mode, free run, send HSO/VSO out */
 925                 writel_relaxed(0x07, priv->io_base + _REG(ENCI_SYNC_MODE));
 926
 927                 if (vmode->enci.yc_delay)
 928                         writel_relaxed(vmode->enci.yc_delay,
 929                                         priv->io_base + _REG(ENCI_YC_DELAY));
 930
 931
 932                 /* UNreset Interlaced TV Encoder */
 933                 writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST));
 934
 935                 /* Enable Vfifo2vd, Y_Cb_Y_Cr select */
 936                 writel_relaxed(0x4e01, priv->io_base + _REG(ENCI_VFIFO2VD_CTL));
 937
 938                 /* Timings */
 939                 writel_relaxed(vmode->enci.pixel_start,
 940                         priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_START));
 941                 writel_relaxed(vmode->enci.pixel_end,
 942                         priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_END));
 943
 944                 writel_relaxed(vmode->enci.top_field_line_start,
 945                         priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_START));
 946                 writel_relaxed(vmode->enci.top_field_line_end,
 947                         priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_END));
 948
 949                 writel_relaxed(vmode->enci.bottom_field_line_start,
 950                         priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_START));
 951                 writel_relaxed(vmode->enci.bottom_field_line_end,
 952                         priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_END));
 953
 954                 /* Select ENCI for VIU */
 955                 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCI);
 956
 957                 /* Interlace video enable */
 958                 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN));
 959
 960                 lines_f0 = mode->vtotal >> 1;
 961                 lines_f1 = lines_f0 + 1;
 962
 963                 de_h_begin = modulo(readl_relaxed(priv->io_base +
 964                                         _REG(ENCI_VFIFO2VD_PIXEL_START))
 965                                         + venc_hdmi_latency,
 966                                     total_pixels_venc);
 967                 de_h_end  = modulo(de_h_begin + active_pixels_venc,
 968                                    total_pixels_venc);
 969
 970                 writel_relaxed(de_h_begin,
 971                                 priv->io_base + _REG(ENCI_DE_H_BEGIN));
 972                 writel_relaxed(de_h_end,
 973                                 priv->io_base + _REG(ENCI_DE_H_END));
 974
 975                 de_v_begin_even = readl_relaxed(priv->io_base +
 976                                         _REG(ENCI_VFIFO2VD_LINE_TOP_START));
 977                 de_v_end_even  = de_v_begin_even + mode->vdisplay;
 978                 de_v_begin_odd = readl_relaxed(priv->io_base +
 979                                         _REG(ENCI_VFIFO2VD_LINE_BOT_START));
 980                 de_v_end_odd = de_v_begin_odd + mode->vdisplay;
 981
 982                 writel_relaxed(de_v_begin_even,
 983                                 priv->io_base + _REG(ENCI_DE_V_BEGIN_EVEN));
 984                 writel_relaxed(de_v_end_even,
 985                                 priv->io_base + _REG(ENCI_DE_V_END_EVEN));
 986                 writel_relaxed(de_v_begin_odd,
 987                                 priv->io_base + _REG(ENCI_DE_V_BEGIN_ODD));
 988                 writel_relaxed(de_v_end_odd,
 989                                 priv->io_base + _REG(ENCI_DE_V_END_ODD));
 990
 991                 /* Program Hsync timing */
 992                 hs_begin = de_h_end + front_porch_venc;
 993                 if (de_h_end + front_porch_venc >= total_pixels_venc) {
 994                         hs_begin -= total_pixels_venc;
 995                         vs_adjust  = 1;
 996                 } else {
 997                         hs_begin = de_h_end + front_porch_venc;
 998                         vs_adjust  = 0;
 999                 }
1000
1001                 hs_end = modulo(hs_begin + hsync_pixels_venc,
1002                                 total_pixels_venc);
1003                 writel_relaxed(hs_begin,
1004                                 priv->io_base + _REG(ENCI_DVI_HSO_BEGIN));
1005                 writel_relaxed(hs_end,
1006                                 priv->io_base + _REG(ENCI_DVI_HSO_END));
1007
1008                 /* Program Vsync timing for even field */
1009                 if (((de_v_end_odd - 1) + eof_lines + vs_adjust) >= lines_f1) {
1010                         vs_bline_evn = (de_v_end_odd - 1)
1011                                         + eof_lines
1012                                         + vs_adjust
1013                                         - lines_f1;
1014                         vs_eline_evn = vs_bline_evn + vsync_lines;
1015
1016                         writel_relaxed(vs_bline_evn,
1017                                 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_EVN));
1018
1019                         writel_relaxed(vs_eline_evn,
1020                                 priv->io_base + _REG(ENCI_DVI_VSO_ELINE_EVN));
1021
1022                         writel_relaxed(hs_begin,
1023                                 priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_EVN));
1024                         writel_relaxed(hs_begin,
1025                                 priv->io_base + _REG(ENCI_DVI_VSO_END_EVN));
1026                 } else {
1027                         vs_bline_odd = (de_v_end_odd - 1)
1028                                         + eof_lines
1029                                         + vs_adjust;
1030
1031                         writel_relaxed(vs_bline_odd,
1032                                 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_ODD));
1033
1034                         writel_relaxed(hs_begin,
1035                                 priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_ODD));
1036
1037                         if ((vs_bline_odd + vsync_lines) >= lines_f1) {
1038                                 vs_eline_evn = vs_bline_odd
1039                                                 + vsync_lines
1040                                                 - lines_f1;
1041
1042                                 writel_relaxed(vs_eline_evn, priv->io_base
1043                                                 + _REG(ENCI_DVI_VSO_ELINE_EVN));
1044
1045                                 writel_relaxed(hs_begin, priv->io_base
1046                                                 + _REG(ENCI_DVI_VSO_END_EVN));
1047                         } else {
1048                                 vs_eline_odd = vs_bline_odd
1049                                                 + vsync_lines;
1050
1051                                 writel_relaxed(vs_eline_odd, priv->io_base
1052                                                 + _REG(ENCI_DVI_VSO_ELINE_ODD));
1053
1054                                 writel_relaxed(hs_begin, priv->io_base
1055                                                 + _REG(ENCI_DVI_VSO_END_ODD));
1056                         }
1057                 }
1058
1059                 /* Program Vsync timing for odd field */
1060                 if (((de_v_end_even - 1) + (eof_lines + 1)) >= lines_f0) {
1061                         vs_bline_odd = (de_v_end_even - 1)
1062                                         + (eof_lines + 1)
1063                                         - lines_f0;
1064                         vs_eline_odd = vs_bline_odd + vsync_lines;
1065
1066                         writel_relaxed(vs_bline_odd,
1067                                 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_ODD));
1068
1069                         writel_relaxed(vs_eline_odd,
1070                                 priv->io_base + _REG(ENCI_DVI_VSO_ELINE_ODD));
1071
1072                         vso_begin_odd  = modulo(hs_begin
1073                                                 + (total_pixels_venc >> 1),
1074                                                 total_pixels_venc);
1075
1076                         writel_relaxed(vso_begin_odd,
1077                                 priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_ODD));
1078                         writel_relaxed(vso_begin_odd,
1079                                 priv->io_base + _REG(ENCI_DVI_VSO_END_ODD));
1080                 } else {
1081                         vs_bline_evn = (de_v_end_even - 1)
1082                                         + (eof_lines + 1);
1083
1084                         writel_relaxed(vs_bline_evn,
1085                                 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_EVN));
1086
1087                         vso_begin_evn  = modulo(hs_begin
1088                                                 + (total_pixels_venc >> 1),
1089                                                 total_pixels_venc);
1090
1091                         writel_relaxed(vso_begin_evn, priv->io_base
1092                                         + _REG(ENCI_DVI_VSO_BEGIN_EVN));
1093
1094                         if (vs_bline_evn + vsync_lines >= lines_f0) {
1095                                 vs_eline_odd = vs_bline_evn
1096                                                 + vsync_lines
1097                                                 - lines_f0;
1098
1099                                 writel_relaxed(vs_eline_odd, priv->io_base
1100                                                 + _REG(ENCI_DVI_VSO_ELINE_ODD));
1101
1102                                 writel_relaxed(vso_begin_evn, priv->io_base
1103                                                 + _REG(ENCI_DVI_VSO_END_ODD));
1104                         } else {
1105                                 vs_eline_evn = vs_bline_evn + vsync_lines;
1106
1107                                 writel_relaxed(vs_eline_evn, priv->io_base
1108                                                 + _REG(ENCI_DVI_VSO_ELINE_EVN));
1109
1110                                 writel_relaxed(vso_begin_evn, priv->io_base
1111                                                 + _REG(ENCI_DVI_VSO_END_EVN));
1112                         }
1113                 }
1114         } else {
1115                 writel_relaxed(vmode->encp.dvi_settings,
1116                                 priv->io_base + _REG(VENC_DVI_SETTING));
1117                 writel_relaxed(vmode->encp.video_mode,
1118                                 priv->io_base + _REG(ENCP_VIDEO_MODE));
1119                 writel_relaxed(vmode->encp.video_mode_adv,
1120                                 priv->io_base + _REG(ENCP_VIDEO_MODE_ADV));
1121                 if (vmode->encp.video_prog_mode_present)
1122                         writel_relaxed(vmode->encp.video_prog_mode,
1123                                 priv->io_base + _REG(VENC_VIDEO_PROG_MODE));
1124                 if (vmode->encp.video_sync_mode_present)
1125                         writel_relaxed(vmode->encp.video_sync_mode,
1126                                 priv->io_base + _REG(ENCP_VIDEO_SYNC_MODE));
1127                 if (vmode->encp.video_yc_dly_present)
1128                         writel_relaxed(vmode->encp.video_yc_dly,
1129                                 priv->io_base + _REG(ENCP_VIDEO_YC_DLY));
1130                 if (vmode->encp.video_rgb_ctrl_present)
1131                         writel_relaxed(vmode->encp.video_rgb_ctrl,
1132                                 priv->io_base + _REG(ENCP_VIDEO_RGB_CTRL));
1133                 if (vmode->encp.video_filt_ctrl_present)
1134                         writel_relaxed(vmode->encp.video_filt_ctrl,
1135                                 priv->io_base + _REG(ENCP_VIDEO_FILT_CTRL));
1136                 if (vmode->encp.video_ofld_voav_ofst_present)
1137                         writel_relaxed(vmode->encp.video_ofld_voav_ofst,
1138                                 priv->io_base
1139                                 + _REG(ENCP_VIDEO_OFLD_VOAV_OFST));
1140                 writel_relaxed(vmode->encp.yfp1_htime,
1141                                 priv->io_base + _REG(ENCP_VIDEO_YFP1_HTIME));
1142                 writel_relaxed(vmode->encp.yfp2_htime,
1143                                 priv->io_base + _REG(ENCP_VIDEO_YFP2_HTIME));
1144                 writel_relaxed(vmode->encp.max_pxcnt,
1145                                 priv->io_base + _REG(ENCP_VIDEO_MAX_PXCNT));
1146                 writel_relaxed(vmode->encp.hspuls_begin,
1147                                 priv->io_base + _REG(ENCP_VIDEO_HSPULS_BEGIN));
1148                 writel_relaxed(vmode->encp.hspuls_end,
1149                                 priv->io_base + _REG(ENCP_VIDEO_HSPULS_END));
1150                 writel_relaxed(vmode->encp.hspuls_switch,
1151                                 priv->io_base + _REG(ENCP_VIDEO_HSPULS_SWITCH));
1152                 writel_relaxed(vmode->encp.vspuls_begin,
1153                                 priv->io_base + _REG(ENCP_VIDEO_VSPULS_BEGIN));
1154                 writel_relaxed(vmode->encp.vspuls_end,
1155                                 priv->io_base + _REG(ENCP_VIDEO_VSPULS_END));
1156                 writel_relaxed(vmode->encp.vspuls_bline,
1157                                 priv->io_base + _REG(ENCP_VIDEO_VSPULS_BLINE));
1158                 writel_relaxed(vmode->encp.vspuls_eline,
1159                                 priv->io_base + _REG(ENCP_VIDEO_VSPULS_ELINE));
1160                 if (vmode->encp.eqpuls_begin_present)
1161                         writel_relaxed(vmode->encp.eqpuls_begin,
1162                                 priv->io_base + _REG(ENCP_VIDEO_EQPULS_BEGIN));
1163                 if (vmode->encp.eqpuls_end_present)
1164                         writel_relaxed(vmode->encp.eqpuls_end,
1165                                 priv->io_base + _REG(ENCP_VIDEO_EQPULS_END));
1166                 if (vmode->encp.eqpuls_bline_present)
1167                         writel_relaxed(vmode->encp.eqpuls_bline,
1168                                 priv->io_base + _REG(ENCP_VIDEO_EQPULS_BLINE));
1169                 if (vmode->encp.eqpuls_eline_present)
1170                         writel_relaxed(vmode->encp.eqpuls_eline,
1171                                 priv->io_base + _REG(ENCP_VIDEO_EQPULS_ELINE));
1172                 writel_relaxed(vmode->encp.havon_begin,
1173                                 priv->io_base + _REG(ENCP_VIDEO_HAVON_BEGIN));
1174                 writel_relaxed(vmode->encp.havon_end,
1175                                 priv->io_base + _REG(ENCP_VIDEO_HAVON_END));
1176                 writel_relaxed(vmode->encp.vavon_bline,
1177                                 priv->io_base + _REG(ENCP_VIDEO_VAVON_BLINE));
1178                 writel_relaxed(vmode->encp.vavon_eline,
1179                                 priv->io_base + _REG(ENCP_VIDEO_VAVON_ELINE));
1180                 writel_relaxed(vmode->encp.hso_begin,
1181                                 priv->io_base + _REG(ENCP_VIDEO_HSO_BEGIN));
1182                 writel_relaxed(vmode->encp.hso_end,
1183                                 priv->io_base + _REG(ENCP_VIDEO_HSO_END));
1184                 writel_relaxed(vmode->encp.vso_begin,
1185                                 priv->io_base + _REG(ENCP_VIDEO_VSO_BEGIN));
1186                 writel_relaxed(vmode->encp.vso_end,
1187                                 priv->io_base + _REG(ENCP_VIDEO_VSO_END));
1188                 writel_relaxed(vmode->encp.vso_bline,
1189                                 priv->io_base + _REG(ENCP_VIDEO_VSO_BLINE));
1190                 if (vmode->encp.vso_eline_present)
1191                         writel_relaxed(vmode->encp.vso_eline,
1192                                 priv->io_base + _REG(ENCP_VIDEO_VSO_ELINE));
1193                 if (vmode->encp.sy_val_present)
1194                         writel_relaxed(vmode->encp.sy_val,
1195                                 priv->io_base + _REG(ENCP_VIDEO_SY_VAL));
1196                 if (vmode->encp.sy2_val_present)
1197                         writel_relaxed(vmode->encp.sy2_val,
1198                                 priv->io_base + _REG(ENCP_VIDEO_SY2_VAL));
1199                 writel_relaxed(vmode->encp.max_lncnt,
1200                                 priv->io_base + _REG(ENCP_VIDEO_MAX_LNCNT));
1201
1202                 writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN));
1203
1204                 /* Set DE signal’s polarity is active high */
1205                 writel_bits_relaxed(BIT(14), BIT(14),
1206                                     priv->io_base + _REG(ENCP_VIDEO_MODE));
1207
1208                 /* Program DE timing */
1209                 de_h_begin = modulo(readl_relaxed(priv->io_base +
1210                                         _REG(ENCP_VIDEO_HAVON_BEGIN))
1211                                         + venc_hdmi_latency,
1212                                     total_pixels_venc);
1213                 de_h_end = modulo(de_h_begin + active_pixels_venc,
1214                                   total_pixels_venc);
1215
1216                 writel_relaxed(de_h_begin,
1217                                 priv->io_base + _REG(ENCP_DE_H_BEGIN));
1218                 writel_relaxed(de_h_end,
1219                                 priv->io_base + _REG(ENCP_DE_H_END));
1220
1221                 /* Program DE timing for even field */
1222                 de_v_begin_even = readl_relaxed(priv->io_base
1223                                                 + _REG(ENCP_VIDEO_VAVON_BLINE));
1224                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1225                         de_v_end_even = de_v_begin_even +
1226                                         (mode->vdisplay / 2);
1227                 else
1228                         de_v_end_even = de_v_begin_even + mode->vdisplay;
1229
1230                 writel_relaxed(de_v_begin_even,
1231                                 priv->io_base + _REG(ENCP_DE_V_BEGIN_EVEN));
1232                 writel_relaxed(de_v_end_even,
1233                                 priv->io_base + _REG(ENCP_DE_V_END_EVEN));
1234
1235                 /* Program DE timing for odd field if needed */
1236                 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1237                         unsigned int ofld_voav_ofst =
1238                                 readl_relaxed(priv->io_base +
1239                                         _REG(ENCP_VIDEO_OFLD_VOAV_OFST));
1240                         de_v_begin_odd = to_signed((ofld_voav_ofst & 0xf0) >> 4)
1241                                                 + de_v_begin_even
1242                                                 + ((mode->vtotal - 1) / 2);
1243                         de_v_end_odd = de_v_begin_odd + (mode->vdisplay / 2);
1244
1245                         writel_relaxed(de_v_begin_odd,
1246                                 priv->io_base + _REG(ENCP_DE_V_BEGIN_ODD));
1247                         writel_relaxed(de_v_end_odd,
1248                                 priv->io_base + _REG(ENCP_DE_V_END_ODD));
1249                 }
1250
1251                 /* Program Hsync timing */
1252                 if ((de_h_end + front_porch_venc) >= total_pixels_venc) {
1253                         hs_begin = de_h_end
1254                                    + front_porch_venc
1255                                    - total_pixels_venc;
1256                         vs_adjust  = 1;
1257                 } else {
1258                         hs_begin = de_h_end
1259                                    + front_porch_venc;
1260                         vs_adjust  = 0;
1261                 }
1262
1263                 hs_end = modulo(hs_begin + hsync_pixels_venc,
1264                                 total_pixels_venc);
1265
1266                 writel_relaxed(hs_begin,
1267                                 priv->io_base + _REG(ENCP_DVI_HSO_BEGIN));
1268                 writel_relaxed(hs_end,
1269                                 priv->io_base + _REG(ENCP_DVI_HSO_END));
1270
1271                 /* Program Vsync timing for even field */
1272                 if (de_v_begin_even >=
1273                                 (sof_lines + vsync_lines + (1 - vs_adjust)))
1274                         vs_bline_evn = de_v_begin_even
1275                                         - sof_lines
1276                                         - vsync_lines
1277                                         - (1 - vs_adjust);
1278                 else
1279                         vs_bline_evn = mode->vtotal
1280                                         + de_v_begin_even
1281                                         - sof_lines
1282                                         - vsync_lines
1283                                         - (1 - vs_adjust);
1284
1285                 vs_eline_evn = modulo(vs_bline_evn + vsync_lines,
1286                                         mode->vtotal);
1287
1288                 writel_relaxed(vs_bline_evn,
1289                                 priv->io_base + _REG(ENCP_DVI_VSO_BLINE_EVN));
1290                 writel_relaxed(vs_eline_evn,
1291                                 priv->io_base + _REG(ENCP_DVI_VSO_ELINE_EVN));
1292
1293                 vso_begin_evn = hs_begin;
1294                 writel_relaxed(vso_begin_evn,
1295                                 priv->io_base + _REG(ENCP_DVI_VSO_BEGIN_EVN));
1296                 writel_relaxed(vso_begin_evn,
1297                                 priv->io_base + _REG(ENCP_DVI_VSO_END_EVN));
1298
1299                 /* Program Vsync timing for odd field if needed */
1300                 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1301                         vs_bline_odd = (de_v_begin_odd - 1)
1302                                         - sof_lines
1303                                         - vsync_lines;
1304                         vs_eline_odd = (de_v_begin_odd - 1)
1305                                         - vsync_lines;
1306                         vso_begin_odd  = modulo(hs_begin
1307                                                 + (total_pixels_venc >> 1),
1308                                                 total_pixels_venc);
1309
1310                         writel_relaxed(vs_bline_odd,
1311                                 priv->io_base + _REG(ENCP_DVI_VSO_BLINE_ODD));
1312                         writel_relaxed(vs_eline_odd,
1313                                 priv->io_base + _REG(ENCP_DVI_VSO_ELINE_ODD));
1314                         writel_relaxed(vso_begin_odd,
1315                                 priv->io_base + _REG(ENCP_DVI_VSO_BEGIN_ODD));
1316                         writel_relaxed(vso_begin_odd,
1317                                 priv->io_base + _REG(ENCP_DVI_VSO_END_ODD));
1318                 }
1319
1320                 /* Select ENCP for VIU */
1321                 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCP);
1322         }
1323
1324         writel_relaxed((use_enci ? 1 : 2) |
1325                        (mode->flags & DRM_MODE_FLAG_PHSYNC ? 1 << 2 : 0) |
1326                        (mode->flags & DRM_MODE_FLAG_PVSYNC ? 1 << 3 : 0) |
1327                        4 << 5 |
1328                        (venc_repeat ? 1 << 8 : 0) |
1329                        (hdmi_repeat ? 1 << 12 : 0),
1330                        priv->io_base + _REG(VPU_HDMI_SETTING));
1331
1332         priv->venc.hdmi_repeat = hdmi_repeat;
1333         priv->venc.venc_repeat = venc_repeat;
1334         priv->venc.hdmi_use_enci = use_enci;
1335
1336         priv->venc.current_mode = MESON_VENC_MODE_HDMI;
1337 }
1338 EXPORT_SYMBOL_GPL(meson_venc_hdmi_mode_set);
1339
1340 void meson_venci_cvbs_mode_set(struct meson_drm *priv,
1341                                struct meson_cvbs_enci_mode *mode)
1342 {
1343         if (mode->mode_tag == priv->venc.current_mode)
1344                 return;
1345
1346         /* CVBS Filter settings */
1347         writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL));
1348         writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL2));
1349
1350         /* Digital Video Select : Interlace, clk27 clk, external */
1351         writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING));
1352
1353         /* Reset Video Mode */
1354         writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE));
1355         writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
1356
1357         /* Horizontal sync signal output */
1358         writel_relaxed(mode->hso_begin,
1359                         priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN));
1360         writel_relaxed(mode->hso_end,
1361                         priv->io_base + _REG(ENCI_SYNC_HSO_END));
1362
1363         /* Vertical Sync lines */
1364         writel_relaxed(mode->vso_even,
1365                         priv->io_base + _REG(ENCI_SYNC_VSO_EVNLN));
1366         writel_relaxed(mode->vso_odd,
1367                         priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN));
1368
1369         /* Macrovision max amplitude change */
1370         writel_relaxed(0x8100 + mode->macv_max_amp,
1371                         priv->io_base + _REG(ENCI_MACV_MAX_AMP));
1372
1373         /* Video mode */
1374         writel_relaxed(mode->video_prog_mode,
1375                         priv->io_base + _REG(VENC_VIDEO_PROG_MODE));
1376         writel_relaxed(mode->video_mode,
1377                         priv->io_base + _REG(ENCI_VIDEO_MODE));
1378
1379         /* Advanced Video Mode :
1380          * Demux shifting 0x2
1381          * Blank line end at line17/22
1382          * High bandwidth Luma Filter
1383          * Low bandwidth Chroma Filter
1384          * Bypass luma low pass filter
1385          * No macrovision on CSYNC
1386          */
1387         writel_relaxed(0x26, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
1388
1389         writel(mode->sch_adjust, priv->io_base + _REG(ENCI_VIDEO_SCH));
1390
1391         /* Sync mode : MASTER Master mode, free run, send HSO/VSO out */
1392         writel_relaxed(0x07, priv->io_base + _REG(ENCI_SYNC_MODE));
1393
1394         /* 0x3 Y, C, and Component Y delay */
1395         writel_relaxed(mode->yc_delay, priv->io_base + _REG(ENCI_YC_DELAY));
1396
1397         /* Timings */
1398         writel_relaxed(mode->pixel_start,
1399                         priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_START));
1400         writel_relaxed(mode->pixel_end,
1401                         priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_END));
1402
1403         writel_relaxed(mode->top_field_line_start,
1404                         priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_START));
1405         writel_relaxed(mode->top_field_line_end,
1406                         priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_END));
1407
1408         writel_relaxed(mode->bottom_field_line_start,
1409                         priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_START));
1410         writel_relaxed(mode->bottom_field_line_end,
1411                         priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_END));
1412
1413         /* Internal Venc, Internal VIU Sync, Internal Vencoder */
1414         writel_relaxed(0, priv->io_base + _REG(VENC_SYNC_ROUTE));
1415
1416         /* UNreset Interlaced TV Encoder */
1417         writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST));
1418
1419         /* Enable Vfifo2vd, Y_Cb_Y_Cr select */
1420         writel_relaxed(0x4e01, priv->io_base + _REG(ENCI_VFIFO2VD_CTL));
1421
1422         /* Power UP Dacs */
1423         writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_SETTING));
1424
1425         /* Video Upsampling */
1426         writel_relaxed(0x0061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL0));
1427         writel_relaxed(0x4061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL1));
1428         writel_relaxed(0x5061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL2));
1429
1430         /* Select Interlace Y DACs */
1431         writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL0));
1432         writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL1));
1433         writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL2));
1434         writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL3));
1435         writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL4));
1436         writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL5));
1437
1438         /* Select ENCI for VIU */
1439         meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCI);
1440
1441         /* Enable ENCI FIFO */
1442         writel_relaxed(0x2000, priv->io_base + _REG(VENC_VDAC_FIFO_CTRL));
1443
1444         /* Select ENCI DACs 0, 1, 4, and 5 */
1445         writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_0));
1446         writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_1));
1447
1448         /* Interlace video enable */
1449         writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN));
1450
1451         /* Configure Video Saturation / Contrast / Brightness / Hue */
1452         writel_relaxed(mode->video_saturation,
1453                         priv->io_base + _REG(ENCI_VIDEO_SAT));
1454         writel_relaxed(mode->video_contrast,
1455                         priv->io_base + _REG(ENCI_VIDEO_CONT));
1456         writel_relaxed(mode->video_brightness,
1457                         priv->io_base + _REG(ENCI_VIDEO_BRIGHT));
1458         writel_relaxed(mode->video_hue,
1459                         priv->io_base + _REG(ENCI_VIDEO_HUE));
1460
1461         /* Enable DAC0 Filter */
1462         writel_relaxed(0x1, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL0));
1463         writel_relaxed(0xfc48, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL1));
1464
1465         /* 0 in Macrovision register 0 */
1466         writel_relaxed(0, priv->io_base + _REG(ENCI_MACV_N0));
1467
1468         /* Analog Synchronization and color burst value adjust */
1469         writel_relaxed(mode->analog_sync_adj,
1470                         priv->io_base + _REG(ENCI_SYNC_ADJ));
1471
1472         priv->venc.current_mode = mode->mode_tag;
1473 }
1474
1475 /* Returns the current ENCI field polarity */
1476 unsigned int meson_venci_get_field(struct meson_drm *priv)
1477 {
1478         return readl_relaxed(priv->io_base + _REG(ENCI_INFO_READ)) & BIT(29);
1479 }
1480
1481 void meson_venc_enable_vsync(struct meson_drm *priv)
1482 {
1483         writel_relaxed(2, priv->io_base + _REG(VENC_INTCTRL));
1484 }
1485
1486 void meson_venc_disable_vsync(struct meson_drm *priv)
1487 {
1488         writel_relaxed(0, priv->io_base + _REG(VENC_INTCTRL));
1489 }
1490
1491 void meson_venc_init(struct meson_drm *priv)
1492 {
1493         /* Disable CVBS VDAC */
1494         regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0);
1495         regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8);
1496
1497         /* Power Down Dacs */
1498         writel_relaxed(0xff, priv->io_base + _REG(VENC_VDAC_SETTING));
1499
1500         /* Disable HDMI PHY */
1501         regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0);
1502
1503         /* Disable HDMI */
1504         writel_bits_relaxed(0x3, 0,
1505                             priv->io_base + _REG(VPU_HDMI_SETTING));
1506
1507         /* Disable all encoders */
1508         writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
1509         writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
1510         writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
1511
1512         /* Disable VSync IRQ */
1513         meson_venc_disable_vsync(priv);
1514
1515         priv->venc.current_mode = MESON_VENC_MODE_NONE;
1516 }