drivers/gpu/drm/meson/meson_plane.c

   1 /*
   2  * Copyright (C) 2016 BayLibre, SAS
   3  * Author: Neil Armstrong <narmstrong@baylibre.com>
   4  * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
   5  * Copyright (C) 2014 Endless Mobile
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of the
  10  * License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  19  *
  20  * Written by:
  21  *     Jasper St. Pierre <jstpierre@mecheye.net>
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/mutex.h>
  27 #include <linux/platform_device.h>
  28 #include <drm/drmP.h>
  29 #include <drm/drm_atomic.h>
  30 #include <drm/drm_atomic_helper.h>
  31 #include <drm/drm_plane_helper.h>
  32 #include <drm/drm_gem_cma_helper.h>
  33 #include <drm/drm_fb_cma_helper.h>
  34 #include <drm/drm_rect.h>
  35
  36 #include "meson_plane.h"
  37 #include "meson_vpp.h"
  38 #include "meson_viu.h"
  39 #include "meson_canvas.h"
  40 #include "meson_registers.h"
  41
  42 struct meson_plane {
  43         struct drm_plane base;
  44         struct meson_drm *priv;
  45 };
  46 #define to_meson_plane(x) container_of(x, struct meson_plane, base)
  47
  48 static int meson_plane_atomic_check(struct drm_plane *plane,
  49                                     struct drm_plane_state *state)
  50 {
  51         struct drm_crtc_state *crtc_state;
  52         struct drm_rect clip = { 0, };
  53
  54         if (!state->crtc)
  55                 return 0;
  56
  57         crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
  58         if (IS_ERR(crtc_state))
  59                 return PTR_ERR(crtc_state);
  60
  61         clip.x2 = crtc_state->mode.hdisplay;
  62         clip.y2 = crtc_state->mode.vdisplay;
  63
  64         return drm_plane_helper_check_state(state, &clip,
  65                                             DRM_PLANE_HELPER_NO_SCALING,
  66                                             DRM_PLANE_HELPER_NO_SCALING,
  67                                             true, true);
  68 }
  69
  70 /* Takes a fixed 16.16 number and converts it to integer. */
  71 static inline int64_t fixed16_to_int(int64_t value)
  72 {
  73         return value >> 16;
  74 }
  75
  76 static void meson_plane_atomic_update(struct drm_plane *plane,
  77                                       struct drm_plane_state *old_state)
  78 {
  79         struct meson_plane *meson_plane = to_meson_plane(plane);
  80         struct drm_plane_state *state = plane->state;
  81         struct drm_framebuffer *fb = state->fb;
  82         struct meson_drm *priv = meson_plane->priv;
  83         struct drm_gem_cma_object *gem;
  84         struct drm_rect src = {
  85                 .x1 = (state->src_x),
  86                 .y1 = (state->src_y),
  87                 .x2 = (state->src_x + state->src_w),
  88                 .y2 = (state->src_y + state->src_h),
  89         };
  90         struct drm_rect dest = {
  91                 .x1 = state->crtc_x,
  92                 .y1 = state->crtc_y,
  93                 .x2 = state->crtc_x + state->crtc_w,
  94                 .y2 = state->crtc_y + state->crtc_h,
  95         };
  96         unsigned long flags;
  97
  98         /*
  99          * Update Coordinates
 100          * Update Formats
 101          * Update Buffer
 102          * Enable Plane
 103          */
 104         spin_lock_irqsave(&priv->drm->event_lock, flags);
 105
 106         /* Enable OSD and BLK0, set max global alpha */
 107         priv->viu.osd1_ctrl_stat = OSD_ENABLE |
 108                                    (0xFF << OSD_GLOBAL_ALPHA_SHIFT) |
 109                                    OSD_BLK0_ENABLE;
 110
 111         /* Set up BLK0 to point to the right canvas */
 112         priv->viu.osd1_blk0_cfg[0] = ((MESON_CANVAS_ID_OSD1 << OSD_CANVAS_SEL) |
 113                                       OSD_ENDIANNESS_LE);
 114
 115         /* On GXBB, Use the old non-HDR RGB2YUV converter */
 116         if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu"))
 117                 priv->viu.osd1_blk0_cfg[0] |= OSD_OUTPUT_COLOR_RGB;
 118
 119         switch (fb->format->format) {
 120         case DRM_FORMAT_XRGB8888:
 121                 /* For XRGB, replace the pixel's alpha by 0xFF */
 122                 writel_bits_relaxed(OSD_REPLACE_EN, OSD_REPLACE_EN,
 123                                     priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
 124                 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 |
 125                                               OSD_COLOR_MATRIX_32_ARGB;
 126                 break;
 127         case DRM_FORMAT_XBGR8888:
 128                 /* For XRGB, replace the pixel's alpha by 0xFF */
 129                 writel_bits_relaxed(OSD_REPLACE_EN, OSD_REPLACE_EN,
 130                                     priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
 131                 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 |
 132                                               OSD_COLOR_MATRIX_32_ABGR;
 133                 break;
 134         case DRM_FORMAT_ARGB8888:
 135                 /* For ARGB, use the pixel's alpha */
 136                 writel_bits_relaxed(OSD_REPLACE_EN, 0,
 137                                     priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
 138                 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 |
 139                                               OSD_COLOR_MATRIX_32_ARGB;
 140                 break;
 141         case DRM_FORMAT_ABGR8888:
 142                 /* For ARGB, use the pixel's alpha */
 143                 writel_bits_relaxed(OSD_REPLACE_EN, 0,
 144                                     priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
 145                 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 |
 146                                               OSD_COLOR_MATRIX_32_ABGR;
 147                 break;
 148         case DRM_FORMAT_RGB888:
 149                 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_24 |
 150                                               OSD_COLOR_MATRIX_24_RGB;
 151                 break;
 152         case DRM_FORMAT_RGB565:
 153                 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_16 |
 154                                               OSD_COLOR_MATRIX_16_RGB565;
 155                 break;
 156         };
 157
 158         if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) {
 159                 priv->viu.osd1_interlace = true;
 160
 161                 dest.y1 /= 2;
 162                 dest.y2 /= 2;
 163         } else
 164                 priv->viu.osd1_interlace = false;
 165
 166         /*
 167          * The format of these registers is (x2 << 16 | x1),
 168          * where x2 is exclusive.
 169          * e.g. +30x1920 would be (1919 << 16) | 30
 170          */
 171         priv->viu.osd1_blk0_cfg[1] = ((fixed16_to_int(src.x2) - 1) << 16) |
 172                                         fixed16_to_int(src.x1);
 173         priv->viu.osd1_blk0_cfg[2] = ((fixed16_to_int(src.y2) - 1) << 16) |
 174                                         fixed16_to_int(src.y1);
 175         priv->viu.osd1_blk0_cfg[3] = ((dest.x2 - 1) << 16) | dest.x1;
 176         priv->viu.osd1_blk0_cfg[4] = ((dest.y2 - 1) << 16) | dest.y1;
 177
 178         /* Update Canvas with buffer address */
 179         gem = drm_fb_cma_get_gem_obj(fb, 0);
 180
 181         priv->viu.osd1_addr = gem->paddr;
 182         priv->viu.osd1_stride = fb->pitches[0];
 183         priv->viu.osd1_height = fb->height;
 184
 185         spin_unlock_irqrestore(&priv->drm->event_lock, flags);
 186 }
 187
 188 static void meson_plane_atomic_disable(struct drm_plane *plane,
 189                                        struct drm_plane_state *old_state)
 190 {
 191         struct meson_plane *meson_plane = to_meson_plane(plane);
 192         struct meson_drm *priv = meson_plane->priv;
 193
 194         /* Disable OSD1 */
 195         writel_bits_relaxed(VPP_OSD1_POSTBLEND, 0,
 196                             priv->io_base + _REG(VPP_MISC));
 197
 198 }
 199
 200 static const struct drm_plane_helper_funcs meson_plane_helper_funcs = {
 201         .atomic_check   = meson_plane_atomic_check,
 202         .atomic_disable = meson_plane_atomic_disable,
 203         .atomic_update  = meson_plane_atomic_update,
 204 };
 205
 206 static const struct drm_plane_funcs meson_plane_funcs = {
 207         .update_plane           = drm_atomic_helper_update_plane,
 208         .disable_plane          = drm_atomic_helper_disable_plane,
 209         .destroy                = drm_plane_cleanup,
 210         .reset                  = drm_atomic_helper_plane_reset,
 211         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 212         .atomic_destroy_state   = drm_atomic_helper_plane_destroy_state,
 213 };
 214
 215 static const uint32_t supported_drm_formats[] = {
 216         DRM_FORMAT_ARGB8888,
 217         DRM_FORMAT_ABGR8888,
 218         DRM_FORMAT_XRGB8888,
 219         DRM_FORMAT_XBGR8888,
 220         DRM_FORMAT_RGB888,
 221         DRM_FORMAT_RGB565,
 222 };
 223
 224 int meson_plane_create(struct meson_drm *priv)
 225 {
 226         struct meson_plane *meson_plane;
 227         struct drm_plane *plane;
 228
 229         meson_plane = devm_kzalloc(priv->drm->dev, sizeof(*meson_plane),
 230                                    GFP_KERNEL);
 231         if (!meson_plane)
 232                 return -ENOMEM;
 233
 234         meson_plane->priv = priv;
 235         plane = &meson_plane->base;
 236
 237         drm_universal_plane_init(priv->drm, plane, 0xFF,
 238                                  &meson_plane_funcs,
 239                                  supported_drm_formats,
 240                                  ARRAY_SIZE(supported_drm_formats),
 241                                  NULL,
 242                                  DRM_PLANE_TYPE_PRIMARY, "meson_primary_plane");
 243
 244         drm_plane_helper_add(plane, &meson_plane_helper_funcs);
 245
 246         priv->primary_plane = plane;
 247
 248         return 0;
 249 }