drivers/gpu/drm/mediatek/mtk_hdmi.c

   1 /*
   2  * Copyright (c) 2014 MediaTek Inc.
   3  * Author: Jie Qiu <jie.qiu@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14 #include <drm/drmP.h>
  15 #include <drm/drm_atomic_helper.h>
  16 #include <drm/drm_crtc.h>
  17 #include <drm/drm_crtc_helper.h>
  18 #include <drm/drm_edid.h>
  19 #include <linux/arm-smccc.h>
  20 #include <linux/clk.h>
  21 #include <linux/delay.h>
  22 #include <linux/hdmi.h>
  23 #include <linux/i2c.h>
  24 #include <linux/io.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mfd/syscon.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/of.h>
  29 #include <linux/of_gpio.h>
  30 #include <linux/of_graph.h>
  31 #include <linux/phy/phy.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/regmap.h>
  34 #include <sound/hdmi-codec.h>
  35 #include "mtk_cec.h"
  36 #include "mtk_hdmi.h"
  37 #include "mtk_hdmi_regs.h"
  38
  39 #define NCTS_BYTES      7
  40
  41 enum mtk_hdmi_clk_id {
  42         MTK_HDMI_CLK_HDMI_PIXEL,
  43         MTK_HDMI_CLK_HDMI_PLL,
  44         MTK_HDMI_CLK_AUD_BCLK,
  45         MTK_HDMI_CLK_AUD_SPDIF,
  46         MTK_HDMI_CLK_COUNT
  47 };
  48
  49 enum hdmi_aud_input_type {
  50         HDMI_AUD_INPUT_I2S = 0,
  51         HDMI_AUD_INPUT_SPDIF,
  52 };
  53
  54 enum hdmi_aud_i2s_fmt {
  55         HDMI_I2S_MODE_RJT_24BIT = 0,
  56         HDMI_I2S_MODE_RJT_16BIT,
  57         HDMI_I2S_MODE_LJT_24BIT,
  58         HDMI_I2S_MODE_LJT_16BIT,
  59         HDMI_I2S_MODE_I2S_24BIT,
  60         HDMI_I2S_MODE_I2S_16BIT
  61 };
  62
  63 enum hdmi_aud_mclk {
  64         HDMI_AUD_MCLK_128FS,
  65         HDMI_AUD_MCLK_192FS,
  66         HDMI_AUD_MCLK_256FS,
  67         HDMI_AUD_MCLK_384FS,
  68         HDMI_AUD_MCLK_512FS,
  69         HDMI_AUD_MCLK_768FS,
  70         HDMI_AUD_MCLK_1152FS,
  71 };
  72
  73 enum hdmi_aud_channel_type {
  74         HDMI_AUD_CHAN_TYPE_1_0 = 0,
  75         HDMI_AUD_CHAN_TYPE_1_1,
  76         HDMI_AUD_CHAN_TYPE_2_0,
  77         HDMI_AUD_CHAN_TYPE_2_1,
  78         HDMI_AUD_CHAN_TYPE_3_0,
  79         HDMI_AUD_CHAN_TYPE_3_1,
  80         HDMI_AUD_CHAN_TYPE_4_0,
  81         HDMI_AUD_CHAN_TYPE_4_1,
  82         HDMI_AUD_CHAN_TYPE_5_0,
  83         HDMI_AUD_CHAN_TYPE_5_1,
  84         HDMI_AUD_CHAN_TYPE_6_0,
  85         HDMI_AUD_CHAN_TYPE_6_1,
  86         HDMI_AUD_CHAN_TYPE_7_0,
  87         HDMI_AUD_CHAN_TYPE_7_1,
  88         HDMI_AUD_CHAN_TYPE_3_0_LRS,
  89         HDMI_AUD_CHAN_TYPE_3_1_LRS,
  90         HDMI_AUD_CHAN_TYPE_4_0_CLRS,
  91         HDMI_AUD_CHAN_TYPE_4_1_CLRS,
  92         HDMI_AUD_CHAN_TYPE_6_1_CS,
  93         HDMI_AUD_CHAN_TYPE_6_1_CH,
  94         HDMI_AUD_CHAN_TYPE_6_1_OH,
  95         HDMI_AUD_CHAN_TYPE_6_1_CHR,
  96         HDMI_AUD_CHAN_TYPE_7_1_LH_RH,
  97         HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR,
  98         HDMI_AUD_CHAN_TYPE_7_1_LC_RC,
  99         HDMI_AUD_CHAN_TYPE_7_1_LW_RW,
 100         HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD,
 101         HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS,
 102         HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS,
 103         HDMI_AUD_CHAN_TYPE_7_1_CS_CH,
 104         HDMI_AUD_CHAN_TYPE_7_1_CS_OH,
 105         HDMI_AUD_CHAN_TYPE_7_1_CS_CHR,
 106         HDMI_AUD_CHAN_TYPE_7_1_CH_OH,
 107         HDMI_AUD_CHAN_TYPE_7_1_CH_CHR,
 108         HDMI_AUD_CHAN_TYPE_7_1_OH_CHR,
 109         HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR,
 110         HDMI_AUD_CHAN_TYPE_6_0_CS,
 111         HDMI_AUD_CHAN_TYPE_6_0_CH,
 112         HDMI_AUD_CHAN_TYPE_6_0_OH,
 113         HDMI_AUD_CHAN_TYPE_6_0_CHR,
 114         HDMI_AUD_CHAN_TYPE_7_0_LH_RH,
 115         HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR,
 116         HDMI_AUD_CHAN_TYPE_7_0_LC_RC,
 117         HDMI_AUD_CHAN_TYPE_7_0_LW_RW,
 118         HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD,
 119         HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS,
 120         HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS,
 121         HDMI_AUD_CHAN_TYPE_7_0_CS_CH,
 122         HDMI_AUD_CHAN_TYPE_7_0_CS_OH,
 123         HDMI_AUD_CHAN_TYPE_7_0_CS_CHR,
 124         HDMI_AUD_CHAN_TYPE_7_0_CH_OH,
 125         HDMI_AUD_CHAN_TYPE_7_0_CH_CHR,
 126         HDMI_AUD_CHAN_TYPE_7_0_OH_CHR,
 127         HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR,
 128         HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS,
 129         HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF
 130 };
 131
 132 enum hdmi_aud_channel_swap_type {
 133         HDMI_AUD_SWAP_LR,
 134         HDMI_AUD_SWAP_LFE_CC,
 135         HDMI_AUD_SWAP_LSRS,
 136         HDMI_AUD_SWAP_RLS_RRS,
 137         HDMI_AUD_SWAP_LR_STATUS,
 138 };
 139
 140 struct hdmi_audio_param {
 141         enum hdmi_audio_coding_type aud_codec;
 142         enum hdmi_audio_sample_size aud_sampe_size;
 143         enum hdmi_aud_input_type aud_input_type;
 144         enum hdmi_aud_i2s_fmt aud_i2s_fmt;
 145         enum hdmi_aud_mclk aud_mclk;
 146         enum hdmi_aud_channel_type aud_input_chan_type;
 147         struct hdmi_codec_params codec_params;
 148 };
 149
 150 struct mtk_hdmi {
 151         struct drm_bridge bridge;
 152         struct drm_connector conn;
 153         struct device *dev;
 154         struct phy *phy;
 155         struct device *cec_dev;
 156         struct i2c_adapter *ddc_adpt;
 157         struct clk *clk[MTK_HDMI_CLK_COUNT];
 158         struct drm_display_mode mode;
 159         bool dvi_mode;
 160         u32 min_clock;
 161         u32 max_clock;
 162         u32 max_hdisplay;
 163         u32 max_vdisplay;
 164         u32 ibias;
 165         u32 ibias_up;
 166         struct regmap *sys_regmap;
 167         unsigned int sys_offset;
 168         void __iomem *regs;
 169         enum hdmi_colorspace csp;
 170         struct hdmi_audio_param aud_param;
 171         bool audio_enable;
 172         bool powered;
 173         bool enabled;
 174 };
 175
 176 static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
 177 {
 178         return container_of(b, struct mtk_hdmi, bridge);
 179 }
 180
 181 static inline struct mtk_hdmi *hdmi_ctx_from_conn(struct drm_connector *c)
 182 {
 183         return container_of(c, struct mtk_hdmi, conn);
 184 }
 185
 186 static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset)
 187 {
 188         return readl(hdmi->regs + offset);
 189 }
 190
 191 static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val)
 192 {
 193         writel(val, hdmi->regs + offset);
 194 }
 195
 196 static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
 197 {
 198         void __iomem *reg = hdmi->regs + offset;
 199         u32 tmp;
 200
 201         tmp = readl(reg);
 202         tmp &= ~bits;
 203         writel(tmp, reg);
 204 }
 205
 206 static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
 207 {
 208         void __iomem *reg = hdmi->regs + offset;
 209         u32 tmp;
 210
 211         tmp = readl(reg);
 212         tmp |= bits;
 213         writel(tmp, reg);
 214 }
 215
 216 static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask)
 217 {
 218         void __iomem *reg = hdmi->regs + offset;
 219         u32 tmp;
 220
 221         tmp = readl(reg);
 222         tmp = (tmp & ~mask) | (val & mask);
 223         writel(tmp, reg);
 224 }
 225
 226 static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
 227 {
 228         mtk_hdmi_mask(hdmi, VIDEO_CFG_4, black ? GEN_RGB : NORMAL_PATH,
 229                       VIDEO_SOURCE_SEL);
 230 }
 231
 232 static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
 233 {
 234         struct arm_smccc_res res;
 235
 236         /*
 237          * MT8173 HDMI hardware has an output control bit to enable/disable HDMI
 238          * output. This bit can only be controlled in ARM supervisor mode.
 239          * The ARM trusted firmware provides an API for the HDMI driver to set
 240          * this control bit to enable HDMI output in supervisor mode.
 241          */
 242         arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904, 0x80000000,
 243                       0, 0, 0, 0, 0, &res);
 244
 245         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
 246                            HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0);
 247         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
 248                            HDMI_ON | ANLG_ON, enable ? (HDMI_ON | ANLG_ON) : 0);
 249 }
 250
 251 static void mtk_hdmi_hw_1p4_version_enable(struct mtk_hdmi *hdmi, bool enable)
 252 {
 253         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
 254                            HDMI2P0_EN, enable ? 0 : HDMI2P0_EN);
 255 }
 256
 257 static void mtk_hdmi_hw_aud_mute(struct mtk_hdmi *hdmi)
 258 {
 259         mtk_hdmi_set_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO);
 260 }
 261
 262 static void mtk_hdmi_hw_aud_unmute(struct mtk_hdmi *hdmi)
 263 {
 264         mtk_hdmi_clear_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO);
 265 }
 266
 267 static void mtk_hdmi_hw_reset(struct mtk_hdmi *hdmi)
 268 {
 269         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
 270                            HDMI_RST, HDMI_RST);
 271         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
 272                            HDMI_RST, 0);
 273         mtk_hdmi_clear_bits(hdmi, GRL_CFG3, CFG3_CONTROL_PACKET_DELAY);
 274         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
 275                            ANLG_ON, ANLG_ON);
 276 }
 277
 278 static void mtk_hdmi_hw_enable_notice(struct mtk_hdmi *hdmi, bool enable_notice)
 279 {
 280         mtk_hdmi_mask(hdmi, GRL_CFG2, enable_notice ? CFG2_NOTICE_EN : 0,
 281                       CFG2_NOTICE_EN);
 282 }
 283
 284 static void mtk_hdmi_hw_write_int_mask(struct mtk_hdmi *hdmi, u32 int_mask)
 285 {
 286         mtk_hdmi_write(hdmi, GRL_INT_MASK, int_mask);
 287 }
 288
 289 static void mtk_hdmi_hw_enable_dvi_mode(struct mtk_hdmi *hdmi, bool enable)
 290 {
 291         mtk_hdmi_mask(hdmi, GRL_CFG1, enable ? CFG1_DVI : 0, CFG1_DVI);
 292 }
 293
 294 static void mtk_hdmi_hw_send_info_frame(struct mtk_hdmi *hdmi, u8 *buffer,
 295                                         u8 len)
 296 {
 297         u32 ctrl_reg = GRL_CTRL;
 298         int i;
 299         u8 *frame_data;
 300         enum hdmi_infoframe_type frame_type;
 301         u8 frame_ver;
 302         u8 frame_len;
 303         u8 checksum;
 304         int ctrl_frame_en = 0;
 305
 306         frame_type = *buffer;
 307         buffer += 1;
 308         frame_ver = *buffer;
 309         buffer += 1;
 310         frame_len = *buffer;
 311         buffer += 1;
 312         checksum = *buffer;
 313         buffer += 1;
 314         frame_data = buffer;
 315
 316         dev_dbg(hdmi->dev,
 317                 "frame_type:0x%x,frame_ver:0x%x,frame_len:0x%x,checksum:0x%x\n",
 318                 frame_type, frame_ver, frame_len, checksum);
 319
 320         switch (frame_type) {
 321         case HDMI_INFOFRAME_TYPE_AVI:
 322                 ctrl_frame_en = CTRL_AVI_EN;
 323                 ctrl_reg = GRL_CTRL;
 324                 break;
 325         case HDMI_INFOFRAME_TYPE_SPD:
 326                 ctrl_frame_en = CTRL_SPD_EN;
 327                 ctrl_reg = GRL_CTRL;
 328                 break;
 329         case HDMI_INFOFRAME_TYPE_AUDIO:
 330                 ctrl_frame_en = CTRL_AUDIO_EN;
 331                 ctrl_reg = GRL_CTRL;
 332                 break;
 333         case HDMI_INFOFRAME_TYPE_VENDOR:
 334                 ctrl_frame_en = VS_EN;
 335                 ctrl_reg = GRL_ACP_ISRC_CTRL;
 336                 break;
 337         }
 338         mtk_hdmi_clear_bits(hdmi, ctrl_reg, ctrl_frame_en);
 339         mtk_hdmi_write(hdmi, GRL_INFOFRM_TYPE, frame_type);
 340         mtk_hdmi_write(hdmi, GRL_INFOFRM_VER, frame_ver);
 341         mtk_hdmi_write(hdmi, GRL_INFOFRM_LNG, frame_len);
 342
 343         mtk_hdmi_write(hdmi, GRL_IFM_PORT, checksum);
 344         for (i = 0; i < frame_len; i++)
 345                 mtk_hdmi_write(hdmi, GRL_IFM_PORT, frame_data[i]);
 346
 347         mtk_hdmi_set_bits(hdmi, ctrl_reg, ctrl_frame_en);
 348 }
 349
 350 static void mtk_hdmi_hw_send_aud_packet(struct mtk_hdmi *hdmi, bool enable)
 351 {
 352         mtk_hdmi_mask(hdmi, GRL_SHIFT_R2, enable ? 0 : AUDIO_PACKET_OFF,
 353                       AUDIO_PACKET_OFF);
 354 }
 355
 356 static void mtk_hdmi_hw_config_sys(struct mtk_hdmi *hdmi)
 357 {
 358         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
 359                            HDMI_OUT_FIFO_EN | MHL_MODE_ON, 0);
 360         usleep_range(2000, 4000);
 361         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
 362                            HDMI_OUT_FIFO_EN | MHL_MODE_ON, HDMI_OUT_FIFO_EN);
 363 }
 364
 365 static void mtk_hdmi_hw_set_deep_color_mode(struct mtk_hdmi *hdmi)
 366 {
 367         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
 368                            DEEP_COLOR_MODE_MASK | DEEP_COLOR_EN,
 369                            COLOR_8BIT_MODE);
 370 }
 371
 372 static void mtk_hdmi_hw_send_av_mute(struct mtk_hdmi *hdmi)
 373 {
 374         mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CTRL_AVMUTE);
 375         usleep_range(2000, 4000);
 376         mtk_hdmi_set_bits(hdmi, GRL_CFG4, CTRL_AVMUTE);
 377 }
 378
 379 static void mtk_hdmi_hw_send_av_unmute(struct mtk_hdmi *hdmi)
 380 {
 381         mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_EN,
 382                       CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET);
 383         usleep_range(2000, 4000);
 384         mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_SET,
 385                       CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET);
 386 }
 387
 388 static void mtk_hdmi_hw_ncts_enable(struct mtk_hdmi *hdmi, bool on)
 389 {
 390         mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, on ? 0 : CTS_CTRL_SOFT,
 391                       CTS_CTRL_SOFT);
 392 }
 393
 394 static void mtk_hdmi_hw_ncts_auto_write_enable(struct mtk_hdmi *hdmi,
 395                                                bool enable)
 396 {
 397         mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, enable ? NCTS_WRI_ANYTIME : 0,
 398                       NCTS_WRI_ANYTIME);
 399 }
 400
 401 static void mtk_hdmi_hw_msic_setting(struct mtk_hdmi *hdmi,
 402                                      struct drm_display_mode *mode)
 403 {
 404         mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CFG4_MHL_MODE);
 405
 406         if (mode->flags & DRM_MODE_FLAG_INTERLACE &&
 407             mode->clock == 74250 &&
 408             mode->vdisplay == 1080)
 409                 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL);
 410         else
 411                 mtk_hdmi_set_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL);
 412 }
 413
 414 static void mtk_hdmi_hw_aud_set_channel_swap(struct mtk_hdmi *hdmi,
 415                                         enum hdmi_aud_channel_swap_type swap)
 416 {
 417         u8 swap_bit;
 418
 419         switch (swap) {
 420         case HDMI_AUD_SWAP_LR:
 421                 swap_bit = LR_SWAP;
 422                 break;
 423         case HDMI_AUD_SWAP_LFE_CC:
 424                 swap_bit = LFE_CC_SWAP;
 425                 break;
 426         case HDMI_AUD_SWAP_LSRS:
 427                 swap_bit = LSRS_SWAP;
 428                 break;
 429         case HDMI_AUD_SWAP_RLS_RRS:
 430                 swap_bit = RLS_RRS_SWAP;
 431                 break;
 432         case HDMI_AUD_SWAP_LR_STATUS:
 433                 swap_bit = LR_STATUS_SWAP;
 434                 break;
 435         default:
 436                 swap_bit = LFE_CC_SWAP;
 437                 break;
 438         }
 439         mtk_hdmi_mask(hdmi, GRL_CH_SWAP, swap_bit, 0xff);
 440 }
 441
 442 static void mtk_hdmi_hw_aud_set_bit_num(struct mtk_hdmi *hdmi,
 443                                         enum hdmi_audio_sample_size bit_num)
 444 {
 445         u32 val;
 446
 447         switch (bit_num) {
 448         case HDMI_AUDIO_SAMPLE_SIZE_16:
 449                 val = AOUT_16BIT;
 450                 break;
 451         case HDMI_AUDIO_SAMPLE_SIZE_20:
 452                 val = AOUT_20BIT;
 453                 break;
 454         case HDMI_AUDIO_SAMPLE_SIZE_24:
 455         case HDMI_AUDIO_SAMPLE_SIZE_STREAM:
 456                 val = AOUT_24BIT;
 457                 break;
 458         }
 459
 460         mtk_hdmi_mask(hdmi, GRL_AOUT_CFG, val, AOUT_BNUM_SEL_MASK);
 461 }
 462
 463 static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi,
 464                                         enum hdmi_aud_i2s_fmt i2s_fmt)
 465 {
 466         u32 val;
 467
 468         val = mtk_hdmi_read(hdmi, GRL_CFG0);
 469         val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK);
 470
 471         switch (i2s_fmt) {
 472         case HDMI_I2S_MODE_RJT_24BIT:
 473                 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_24BIT;
 474                 break;
 475         case HDMI_I2S_MODE_RJT_16BIT:
 476                 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_16BIT;
 477                 break;
 478         case HDMI_I2S_MODE_LJT_24BIT:
 479         default:
 480                 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_24BIT;
 481                 break;
 482         case HDMI_I2S_MODE_LJT_16BIT:
 483                 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_16BIT;
 484                 break;
 485         case HDMI_I2S_MODE_I2S_24BIT:
 486                 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_24BIT;
 487                 break;
 488         case HDMI_I2S_MODE_I2S_16BIT:
 489                 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_16BIT;
 490                 break;
 491         }
 492         mtk_hdmi_write(hdmi, GRL_CFG0, val);
 493 }
 494
 495 static void mtk_hdmi_hw_audio_config(struct mtk_hdmi *hdmi, bool dst)
 496 {
 497         const u8 mask = HIGH_BIT_RATE | DST_NORMAL_DOUBLE | SACD_DST | DSD_SEL;
 498         u8 val;
 499
 500         /* Disable high bitrate, set DST packet normal/double */
 501         mtk_hdmi_clear_bits(hdmi, GRL_AOUT_CFG, HIGH_BIT_RATE_PACKET_ALIGN);
 502
 503         if (dst)
 504                 val = DST_NORMAL_DOUBLE | SACD_DST;
 505         else
 506                 val = 0;
 507
 508         mtk_hdmi_mask(hdmi, GRL_AUDIO_CFG, val, mask);
 509 }
 510
 511 static void mtk_hdmi_hw_aud_set_i2s_chan_num(struct mtk_hdmi *hdmi,
 512                                         enum hdmi_aud_channel_type channel_type,
 513                                         u8 channel_count)
 514 {
 515         unsigned int ch_switch;
 516         u8 i2s_uv;
 517
 518         ch_switch = CH_SWITCH(7, 7) | CH_SWITCH(6, 6) |
 519                     CH_SWITCH(5, 5) | CH_SWITCH(4, 4) |
 520                     CH_SWITCH(3, 3) | CH_SWITCH(1, 2) |
 521                     CH_SWITCH(2, 1) | CH_SWITCH(0, 0);
 522
 523         if (channel_count == 2) {
 524                 i2s_uv = I2S_UV_CH_EN(0);
 525         } else if (channel_count == 3 || channel_count == 4) {
 526                 if (channel_count == 4 &&
 527                     (channel_type == HDMI_AUD_CHAN_TYPE_3_0_LRS ||
 528                     channel_type == HDMI_AUD_CHAN_TYPE_4_0))
 529                         i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(0);
 530                 else
 531                         i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2);
 532         } else if (channel_count == 6 || channel_count == 5) {
 533                 if (channel_count == 6 &&
 534                     channel_type != HDMI_AUD_CHAN_TYPE_5_1 &&
 535                     channel_type != HDMI_AUD_CHAN_TYPE_4_1_CLRS) {
 536                         i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) |
 537                                  I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0);
 538                 } else {
 539                         i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(1) |
 540                                  I2S_UV_CH_EN(0);
 541                 }
 542         } else if (channel_count == 8 || channel_count == 7) {
 543                 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) |
 544                          I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0);
 545         } else {
 546                 i2s_uv = I2S_UV_CH_EN(0);
 547         }
 548
 549         mtk_hdmi_write(hdmi, GRL_CH_SW0, ch_switch & 0xff);
 550         mtk_hdmi_write(hdmi, GRL_CH_SW1, (ch_switch >> 8) & 0xff);
 551         mtk_hdmi_write(hdmi, GRL_CH_SW2, (ch_switch >> 16) & 0xff);
 552         mtk_hdmi_write(hdmi, GRL_I2S_UV, i2s_uv);
 553 }
 554
 555 static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi,
 556                                            enum hdmi_aud_input_type input_type)
 557 {
 558         u32 val;
 559
 560         val = mtk_hdmi_read(hdmi, GRL_CFG1);
 561         if (input_type == HDMI_AUD_INPUT_I2S &&
 562             (val & CFG1_SPDIF) == CFG1_SPDIF) {
 563                 val &= ~CFG1_SPDIF;
 564         } else if (input_type == HDMI_AUD_INPUT_SPDIF &&
 565                 (val & CFG1_SPDIF) == 0) {
 566                 val |= CFG1_SPDIF;
 567         }
 568         mtk_hdmi_write(hdmi, GRL_CFG1, val);
 569 }
 570
 571 static void mtk_hdmi_hw_aud_set_channel_status(struct mtk_hdmi *hdmi,
 572                                                u8 *channel_status)
 573 {
 574         int i;
 575
 576         for (i = 0; i < 5; i++) {
 577                 mtk_hdmi_write(hdmi, GRL_I2S_C_STA0 + i * 4, channel_status[i]);
 578                 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, channel_status[i]);
 579                 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, channel_status[i]);
 580         }
 581         for (; i < 24; i++) {
 582                 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, 0);
 583                 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, 0);
 584         }
 585 }
 586
 587 static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi)
 588 {
 589         u32 val;
 590
 591         val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
 592         if (val & MIX_CTRL_SRC_EN) {
 593                 val &= ~MIX_CTRL_SRC_EN;
 594                 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
 595                 usleep_range(255, 512);
 596                 val |= MIX_CTRL_SRC_EN;
 597                 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
 598         }
 599 }
 600
 601 static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi)
 602 {
 603         u32 val;
 604
 605         val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
 606         val &= ~MIX_CTRL_SRC_EN;
 607         mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
 608         mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00);
 609 }
 610
 611 static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
 612                                      enum hdmi_aud_mclk mclk)
 613 {
 614         u32 val;
 615
 616         val = mtk_hdmi_read(hdmi, GRL_CFG5);
 617         val &= CFG5_CD_RATIO_MASK;
 618
 619         switch (mclk) {
 620         case HDMI_AUD_MCLK_128FS:
 621                 val |= CFG5_FS128;
 622                 break;
 623         case HDMI_AUD_MCLK_256FS:
 624                 val |= CFG5_FS256;
 625                 break;
 626         case HDMI_AUD_MCLK_384FS:
 627                 val |= CFG5_FS384;
 628                 break;
 629         case HDMI_AUD_MCLK_512FS:
 630                 val |= CFG5_FS512;
 631                 break;
 632         case HDMI_AUD_MCLK_768FS:
 633                 val |= CFG5_FS768;
 634                 break;
 635         default:
 636                 val |= CFG5_FS256;
 637                 break;
 638         }
 639         mtk_hdmi_write(hdmi, GRL_CFG5, val);
 640 }
 641
 642 struct hdmi_acr_n {
 643         unsigned int clock;
 644         unsigned int n[3];
 645 };
 646
 647 /* Recommended N values from HDMI specification, tables 7-1 to 7-3 */
 648 static const struct hdmi_acr_n hdmi_rec_n_table[] = {
 649         /* Clock, N: 32kHz 44.1kHz 48kHz */
 650         {  25175, {  4576,  7007,  6864 } },
 651         {  74176, { 11648, 17836, 11648 } },
 652         { 148352, { 11648,  8918,  5824 } },
 653         { 296703, {  5824,  4459,  5824 } },
 654         { 297000, {  3072,  4704,  5120 } },
 655         {      0, {  4096,  6272,  6144 } }, /* all other TMDS clocks */
 656 };
 657
 658 /**
 659  * hdmi_recommended_n() - Return N value recommended by HDMI specification
 660  * @freq: audio sample rate in Hz
 661  * @clock: rounded TMDS clock in kHz
 662  */
 663 static unsigned int hdmi_recommended_n(unsigned int freq, unsigned int clock)
 664 {
 665         const struct hdmi_acr_n *recommended;
 666         unsigned int i;
 667
 668         for (i = 0; i < ARRAY_SIZE(hdmi_rec_n_table) - 1; i++) {
 669                 if (clock == hdmi_rec_n_table[i].clock)
 670                         break;
 671         }
 672         recommended = hdmi_rec_n_table + i;
 673
 674         switch (freq) {
 675         case 32000:
 676                 return recommended->n[0];
 677         case 44100:
 678                 return recommended->n[1];
 679         case 48000:
 680                 return recommended->n[2];
 681         case 88200:
 682                 return recommended->n[1] * 2;
 683         case 96000:
 684                 return recommended->n[2] * 2;
 685         case 176400:
 686                 return recommended->n[1] * 4;
 687         case 192000:
 688                 return recommended->n[2] * 4;
 689         default:
 690                 return (128 * freq) / 1000;
 691         }
 692 }
 693
 694 static unsigned int hdmi_mode_clock_to_hz(unsigned int clock)
 695 {
 696         switch (clock) {
 697         case 25175:
 698                 return 25174825;        /* 25.2/1.001 MHz */
 699         case 74176:
 700                 return 74175824;        /* 74.25/1.001 MHz */
 701         case 148352:
 702                 return 148351648;       /* 148.5/1.001 MHz */
 703         case 296703:
 704                 return 296703297;       /* 297/1.001 MHz */
 705         default:
 706                 return clock * 1000;
 707         }
 708 }
 709
 710 static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate,
 711                                       unsigned int tmds_clock, unsigned int n)
 712 {
 713         return DIV_ROUND_CLOSEST_ULL((u64)hdmi_mode_clock_to_hz(tmds_clock) * n,
 714                                      128 * audio_sample_rate);
 715 }
 716
 717 static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n,
 718                                     unsigned int cts)
 719 {
 720         unsigned char val[NCTS_BYTES];
 721         int i;
 722
 723         mtk_hdmi_write(hdmi, GRL_NCTS, 0);
 724         mtk_hdmi_write(hdmi, GRL_NCTS, 0);
 725         mtk_hdmi_write(hdmi, GRL_NCTS, 0);
 726         memset(val, 0, sizeof(val));
 727
 728         val[0] = (cts >> 24) & 0xff;
 729         val[1] = (cts >> 16) & 0xff;
 730         val[2] = (cts >> 8) & 0xff;
 731         val[3] = cts & 0xff;
 732
 733         val[4] = (n >> 16) & 0xff;
 734         val[5] = (n >> 8) & 0xff;
 735         val[6] = n & 0xff;
 736
 737         for (i = 0; i < NCTS_BYTES; i++)
 738                 mtk_hdmi_write(hdmi, GRL_NCTS, val[i]);
 739 }
 740
 741 static void mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi,
 742                                      unsigned int sample_rate,
 743                                      unsigned int clock)
 744 {
 745         unsigned int n, cts;
 746
 747         n = hdmi_recommended_n(sample_rate, clock);
 748         cts = hdmi_expected_cts(sample_rate, clock, n);
 749
 750         dev_dbg(hdmi->dev, "%s: sample_rate=%u, clock=%d, cts=%u, n=%u\n",
 751                 __func__, sample_rate, clock, n, cts);
 752
 753         mtk_hdmi_mask(hdmi, DUMMY_304, AUDIO_I2S_NCTS_SEL_64,
 754                       AUDIO_I2S_NCTS_SEL);
 755         do_hdmi_hw_aud_set_ncts(hdmi, n, cts);
 756 }
 757
 758 static u8 mtk_hdmi_aud_get_chnl_count(enum hdmi_aud_channel_type channel_type)
 759 {
 760         switch (channel_type) {
 761         case HDMI_AUD_CHAN_TYPE_1_0:
 762         case HDMI_AUD_CHAN_TYPE_1_1:
 763         case HDMI_AUD_CHAN_TYPE_2_0:
 764                 return 2;
 765         case HDMI_AUD_CHAN_TYPE_2_1:
 766         case HDMI_AUD_CHAN_TYPE_3_0:
 767                 return 3;
 768         case HDMI_AUD_CHAN_TYPE_3_1:
 769         case HDMI_AUD_CHAN_TYPE_4_0:
 770         case HDMI_AUD_CHAN_TYPE_3_0_LRS:
 771                 return 4;
 772         case HDMI_AUD_CHAN_TYPE_4_1:
 773         case HDMI_AUD_CHAN_TYPE_5_0:
 774         case HDMI_AUD_CHAN_TYPE_3_1_LRS:
 775         case HDMI_AUD_CHAN_TYPE_4_0_CLRS:
 776                 return 5;
 777         case HDMI_AUD_CHAN_TYPE_5_1:
 778         case HDMI_AUD_CHAN_TYPE_6_0:
 779         case HDMI_AUD_CHAN_TYPE_4_1_CLRS:
 780         case HDMI_AUD_CHAN_TYPE_6_0_CS:
 781         case HDMI_AUD_CHAN_TYPE_6_0_CH:
 782         case HDMI_AUD_CHAN_TYPE_6_0_OH:
 783         case HDMI_AUD_CHAN_TYPE_6_0_CHR:
 784                 return 6;
 785         case HDMI_AUD_CHAN_TYPE_6_1:
 786         case HDMI_AUD_CHAN_TYPE_6_1_CS:
 787         case HDMI_AUD_CHAN_TYPE_6_1_CH:
 788         case HDMI_AUD_CHAN_TYPE_6_1_OH:
 789         case HDMI_AUD_CHAN_TYPE_6_1_CHR:
 790         case HDMI_AUD_CHAN_TYPE_7_0:
 791         case HDMI_AUD_CHAN_TYPE_7_0_LH_RH:
 792         case HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR:
 793         case HDMI_AUD_CHAN_TYPE_7_0_LC_RC:
 794         case HDMI_AUD_CHAN_TYPE_7_0_LW_RW:
 795         case HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD:
 796         case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS:
 797         case HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS:
 798         case HDMI_AUD_CHAN_TYPE_7_0_CS_CH:
 799         case HDMI_AUD_CHAN_TYPE_7_0_CS_OH:
 800         case HDMI_AUD_CHAN_TYPE_7_0_CS_CHR:
 801         case HDMI_AUD_CHAN_TYPE_7_0_CH_OH:
 802         case HDMI_AUD_CHAN_TYPE_7_0_CH_CHR:
 803         case HDMI_AUD_CHAN_TYPE_7_0_OH_CHR:
 804         case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR:
 805         case HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS:
 806                 return 7;
 807         case HDMI_AUD_CHAN_TYPE_7_1:
 808         case HDMI_AUD_CHAN_TYPE_7_1_LH_RH:
 809         case HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR:
 810         case HDMI_AUD_CHAN_TYPE_7_1_LC_RC:
 811         case HDMI_AUD_CHAN_TYPE_7_1_LW_RW:
 812         case HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD:
 813         case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS:
 814         case HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS:
 815         case HDMI_AUD_CHAN_TYPE_7_1_CS_CH:
 816         case HDMI_AUD_CHAN_TYPE_7_1_CS_OH:
 817         case HDMI_AUD_CHAN_TYPE_7_1_CS_CHR:
 818         case HDMI_AUD_CHAN_TYPE_7_1_CH_OH:
 819         case HDMI_AUD_CHAN_TYPE_7_1_CH_CHR:
 820         case HDMI_AUD_CHAN_TYPE_7_1_OH_CHR:
 821         case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR:
 822                 return 8;
 823         default:
 824                 return 2;
 825         }
 826 }
 827
 828 static int mtk_hdmi_video_change_vpll(struct mtk_hdmi *hdmi, u32 clock)
 829 {
 830         unsigned long rate;
 831         int ret;
 832
 833         /* The DPI driver already should have set TVDPLL to the correct rate */
 834         ret = clk_set_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL], clock);
 835         if (ret) {
 836                 dev_err(hdmi->dev, "Failed to set PLL to %u Hz: %d\n", clock,
 837                         ret);
 838                 return ret;
 839         }
 840
 841         rate = clk_get_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
 842
 843         if (DIV_ROUND_CLOSEST(rate, 1000) != DIV_ROUND_CLOSEST(clock, 1000))
 844                 dev_warn(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock,
 845                          rate);
 846         else
 847                 dev_dbg(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock, rate);
 848
 849         mtk_hdmi_hw_config_sys(hdmi);
 850         mtk_hdmi_hw_set_deep_color_mode(hdmi);
 851         return 0;
 852 }
 853
 854 static void mtk_hdmi_video_set_display_mode(struct mtk_hdmi *hdmi,
 855                                             struct drm_display_mode *mode)
 856 {
 857         mtk_hdmi_hw_reset(hdmi);
 858         mtk_hdmi_hw_enable_notice(hdmi, true);
 859         mtk_hdmi_hw_write_int_mask(hdmi, 0xff);
 860         mtk_hdmi_hw_enable_dvi_mode(hdmi, hdmi->dvi_mode);
 861         mtk_hdmi_hw_ncts_auto_write_enable(hdmi, true);
 862
 863         mtk_hdmi_hw_msic_setting(hdmi, mode);
 864 }
 865
 866 static int mtk_hdmi_aud_enable_packet(struct mtk_hdmi *hdmi, bool enable)
 867 {
 868         mtk_hdmi_hw_send_aud_packet(hdmi, enable);
 869         return 0;
 870 }
 871
 872 static int mtk_hdmi_aud_on_off_hw_ncts(struct mtk_hdmi *hdmi, bool on)
 873 {
 874         mtk_hdmi_hw_ncts_enable(hdmi, on);
 875         return 0;
 876 }
 877
 878 static int mtk_hdmi_aud_set_input(struct mtk_hdmi *hdmi)
 879 {
 880         enum hdmi_aud_channel_type chan_type;
 881         u8 chan_count;
 882         bool dst;
 883
 884         mtk_hdmi_hw_aud_set_channel_swap(hdmi, HDMI_AUD_SWAP_LFE_CC);
 885         mtk_hdmi_set_bits(hdmi, GRL_MIX_CTRL, MIX_CTRL_FLAT);
 886
 887         if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF &&
 888             hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST) {
 889                 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24);
 890         } else if (hdmi->aud_param.aud_i2s_fmt == HDMI_I2S_MODE_LJT_24BIT) {
 891                 hdmi->aud_param.aud_i2s_fmt = HDMI_I2S_MODE_LJT_16BIT;
 892         }
 893
 894         mtk_hdmi_hw_aud_set_i2s_fmt(hdmi, hdmi->aud_param.aud_i2s_fmt);
 895         mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24);
 896
 897         dst = ((hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF) &&
 898                (hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST));
 899         mtk_hdmi_hw_audio_config(hdmi, dst);
 900
 901         if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF)
 902                 chan_type = HDMI_AUD_CHAN_TYPE_2_0;
 903         else
 904                 chan_type = hdmi->aud_param.aud_input_chan_type;
 905         chan_count = mtk_hdmi_aud_get_chnl_count(chan_type);
 906         mtk_hdmi_hw_aud_set_i2s_chan_num(hdmi, chan_type, chan_count);
 907         mtk_hdmi_hw_aud_set_input_type(hdmi, hdmi->aud_param.aud_input_type);
 908
 909         return 0;
 910 }
 911
 912 static int mtk_hdmi_aud_set_src(struct mtk_hdmi *hdmi,
 913                                 struct drm_display_mode *display_mode)
 914 {
 915         unsigned int sample_rate = hdmi->aud_param.codec_params.sample_rate;
 916
 917         mtk_hdmi_aud_on_off_hw_ncts(hdmi, false);
 918         mtk_hdmi_hw_aud_src_disable(hdmi);
 919         mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_ACLK_INV);
 920
 921         if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_I2S) {
 922                 switch (sample_rate) {
 923                 case 32000:
 924                 case 44100:
 925                 case 48000:
 926                 case 88200:
 927                 case 96000:
 928                         break;
 929                 default:
 930                         return -EINVAL;
 931                 }
 932                 mtk_hdmi_hw_aud_set_mclk(hdmi, hdmi->aud_param.aud_mclk);
 933         } else {
 934                 switch (sample_rate) {
 935                 case 32000:
 936                 case 44100:
 937                 case 48000:
 938                         break;
 939                 default:
 940                         return -EINVAL;
 941                 }
 942                 mtk_hdmi_hw_aud_set_mclk(hdmi, HDMI_AUD_MCLK_128FS);
 943         }
 944
 945         mtk_hdmi_hw_aud_set_ncts(hdmi, sample_rate, display_mode->clock);
 946
 947         mtk_hdmi_hw_aud_src_reenable(hdmi);
 948         return 0;
 949 }
 950
 951 static int mtk_hdmi_aud_output_config(struct mtk_hdmi *hdmi,
 952                                       struct drm_display_mode *display_mode)
 953 {
 954         mtk_hdmi_hw_aud_mute(hdmi);
 955         mtk_hdmi_aud_enable_packet(hdmi, false);
 956
 957         mtk_hdmi_aud_set_input(hdmi);
 958         mtk_hdmi_aud_set_src(hdmi, display_mode);
 959         mtk_hdmi_hw_aud_set_channel_status(hdmi,
 960                         hdmi->aud_param.codec_params.iec.status);
 961
 962         usleep_range(50, 100);
 963
 964         mtk_hdmi_aud_on_off_hw_ncts(hdmi, true);
 965         mtk_hdmi_aud_enable_packet(hdmi, true);
 966         mtk_hdmi_hw_aud_unmute(hdmi);
 967         return 0;
 968 }
 969
 970 static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi,
 971                                         struct drm_display_mode *mode)
 972 {
 973         struct hdmi_avi_infoframe frame;
 974         u8 buffer[17];
 975         ssize_t err;
 976
 977         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
 978         if (err < 0) {
 979                 dev_err(hdmi->dev,
 980                         "Failed to get AVI infoframe from mode: %zd\n", err);
 981                 return err;
 982         }
 983
 984         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
 985         if (err < 0) {
 986                 dev_err(hdmi->dev, "Failed to pack AVI infoframe: %zd\n", err);
 987                 return err;
 988         }
 989
 990         mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
 991         return 0;
 992 }
 993
 994 static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi,
 995                                         const char *vendor,
 996                                         const char *product)
 997 {
 998         struct hdmi_spd_infoframe frame;
 999         u8 buffer[29];
1000         ssize_t err;
1001
1002         err = hdmi_spd_infoframe_init(&frame, vendor, product);
1003         if (err < 0) {
1004                 dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n",
1005                         err);
1006                 return err;
1007         }
1008
1009         err = hdmi_spd_infoframe_pack(&frame, buffer, sizeof(buffer));
1010         if (err < 0) {
1011                 dev_err(hdmi->dev, "Failed to pack SDP infoframe: %zd\n", err);
1012                 return err;
1013         }
1014
1015         mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1016         return 0;
1017 }
1018
1019 static int mtk_hdmi_setup_audio_infoframe(struct mtk_hdmi *hdmi)
1020 {
1021         struct hdmi_audio_infoframe frame;
1022         u8 buffer[14];
1023         ssize_t err;
1024
1025         err = hdmi_audio_infoframe_init(&frame);
1026         if (err < 0) {
1027                 dev_err(hdmi->dev, "Failed to setup audio infoframe: %zd\n",
1028                         err);
1029                 return err;
1030         }
1031
1032         frame.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
1033         frame.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
1034         frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
1035         frame.channels = mtk_hdmi_aud_get_chnl_count(
1036                                         hdmi->aud_param.aud_input_chan_type);
1037
1038         err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
1039         if (err < 0) {
1040                 dev_err(hdmi->dev, "Failed to pack audio infoframe: %zd\n",
1041                         err);
1042                 return err;
1043         }
1044
1045         mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1046         return 0;
1047 }
1048
1049 static int mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi *hdmi,
1050                                                 struct drm_display_mode *mode)
1051 {
1052         struct hdmi_vendor_infoframe frame;
1053         u8 buffer[10];
1054         ssize_t err;
1055
1056         err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mode);
1057         if (err) {
1058                 dev_err(hdmi->dev,
1059                         "Failed to get vendor infoframe from mode: %zd\n", err);
1060                 return err;
1061         }
1062
1063         err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1064         if (err < 0) {
1065                 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1066                         err);
1067                 return err;
1068         }
1069
1070         mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1071         return 0;
1072 }
1073
1074 static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi)
1075 {
1076         struct hdmi_audio_param *aud_param = &hdmi->aud_param;
1077
1078         hdmi->csp = HDMI_COLORSPACE_RGB;
1079         aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1080         aud_param->aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1081         aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
1082         aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
1083         aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
1084         aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
1085
1086         return 0;
1087 }
1088
1089 static void mtk_hdmi_audio_enable(struct mtk_hdmi *hdmi)
1090 {
1091         mtk_hdmi_aud_enable_packet(hdmi, true);
1092         hdmi->audio_enable = true;
1093 }
1094
1095 static void mtk_hdmi_audio_disable(struct mtk_hdmi *hdmi)
1096 {
1097         mtk_hdmi_aud_enable_packet(hdmi, false);
1098         hdmi->audio_enable = false;
1099 }
1100
1101 static int mtk_hdmi_audio_set_param(struct mtk_hdmi *hdmi,
1102                                     struct hdmi_audio_param *param)
1103 {
1104         if (!hdmi->audio_enable) {
1105                 dev_err(hdmi->dev, "hdmi audio is in disable state!\n");
1106                 return -EINVAL;
1107         }
1108         dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n",
1109                 param->aud_codec, param->aud_input_type,
1110                 param->aud_input_chan_type, param->codec_params.sample_rate);
1111         memcpy(&hdmi->aud_param, param, sizeof(*param));
1112         return mtk_hdmi_aud_output_config(hdmi, &hdmi->mode);
1113 }
1114
1115 static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi,
1116                                             struct drm_display_mode *mode)
1117 {
1118         int ret;
1119
1120         mtk_hdmi_hw_vid_black(hdmi, true);
1121         mtk_hdmi_hw_aud_mute(hdmi);
1122         mtk_hdmi_hw_send_av_mute(hdmi);
1123         phy_power_off(hdmi->phy);
1124
1125         ret = mtk_hdmi_video_change_vpll(hdmi,
1126                                          mode->clock * 1000);
1127         if (ret) {
1128                 dev_err(hdmi->dev, "Failed to set vpll: %d\n", ret);
1129                 return ret;
1130         }
1131         mtk_hdmi_video_set_display_mode(hdmi, mode);
1132
1133         phy_power_on(hdmi->phy);
1134         mtk_hdmi_aud_output_config(hdmi, mode);
1135
1136         mtk_hdmi_hw_vid_black(hdmi, false);
1137         mtk_hdmi_hw_aud_unmute(hdmi);
1138         mtk_hdmi_hw_send_av_unmute(hdmi);
1139
1140         return 0;
1141 }
1142
1143 static const char * const mtk_hdmi_clk_names[MTK_HDMI_CLK_COUNT] = {
1144         [MTK_HDMI_CLK_HDMI_PIXEL] = "pixel",
1145         [MTK_HDMI_CLK_HDMI_PLL] = "pll",
1146         [MTK_HDMI_CLK_AUD_BCLK] = "bclk",
1147         [MTK_HDMI_CLK_AUD_SPDIF] = "spdif",
1148 };
1149
1150 static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi,
1151                                 struct device_node *np)
1152 {
1153         int i;
1154
1155         for (i = 0; i < ARRAY_SIZE(mtk_hdmi_clk_names); i++) {
1156                 hdmi->clk[i] = of_clk_get_by_name(np,
1157                                                   mtk_hdmi_clk_names[i]);
1158                 if (IS_ERR(hdmi->clk[i]))
1159                         return PTR_ERR(hdmi->clk[i]);
1160         }
1161         return 0;
1162 }
1163
1164 static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi)
1165 {
1166         int ret;
1167
1168         ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1169         if (ret)
1170                 return ret;
1171
1172         ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
1173         if (ret)
1174                 goto err;
1175
1176         return 0;
1177 err:
1178         clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1179         return ret;
1180 }
1181
1182 static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi)
1183 {
1184         clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1185         clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
1186 }
1187
1188 static enum drm_connector_status hdmi_conn_detect(struct drm_connector *conn,
1189                                                   bool force)
1190 {
1191         struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1192
1193         return mtk_cec_hpd_high(hdmi->cec_dev) ?
1194                connector_status_connected : connector_status_disconnected;
1195 }
1196
1197 static void hdmi_conn_destroy(struct drm_connector *conn)
1198 {
1199         struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1200
1201         mtk_cec_set_hpd_event(hdmi->cec_dev, NULL, NULL);
1202
1203         drm_connector_cleanup(conn);
1204 }
1205
1206 static int mtk_hdmi_conn_get_modes(struct drm_connector *conn)
1207 {
1208         struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1209         struct edid *edid;
1210         int ret;
1211
1212         if (!hdmi->ddc_adpt)
1213                 return -ENODEV;
1214
1215         edid = drm_get_edid(conn, hdmi->ddc_adpt);
1216         if (!edid)
1217                 return -ENODEV;
1218
1219         hdmi->dvi_mode = !drm_detect_monitor_audio(edid);
1220
1221         drm_mode_connector_update_edid_property(conn, edid);
1222
1223         ret = drm_add_edid_modes(conn, edid);
1224         drm_edid_to_eld(conn, edid);
1225         kfree(edid);
1226         return ret;
1227 }
1228
1229 static int mtk_hdmi_conn_mode_valid(struct drm_connector *conn,
1230                                     struct drm_display_mode *mode)
1231 {
1232         struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1233
1234         dev_dbg(hdmi->dev, "xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n",
1235                 mode->hdisplay, mode->vdisplay, mode->vrefresh,
1236                 !!(mode->flags & DRM_MODE_FLAG_INTERLACE), mode->clock * 1000);
1237
1238         if (hdmi->bridge.next) {
1239                 struct drm_display_mode adjusted_mode;
1240
1241                 drm_mode_copy(&adjusted_mode, mode);
1242                 if (!drm_bridge_mode_fixup(hdmi->bridge.next, mode,
1243                                            &adjusted_mode))
1244                         return MODE_BAD;
1245         }
1246
1247         if (mode->clock < 27000)
1248                 return MODE_CLOCK_LOW;
1249         if (mode->clock > 297000)
1250                 return MODE_CLOCK_HIGH;
1251
1252         return drm_mode_validate_size(mode, 0x1fff, 0x1fff);
1253 }
1254
1255 static struct drm_encoder *mtk_hdmi_conn_best_enc(struct drm_connector *conn)
1256 {
1257         struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1258
1259         return hdmi->bridge.encoder;
1260 }
1261
1262 static const struct drm_connector_funcs mtk_hdmi_connector_funcs = {
1263         .dpms = drm_atomic_helper_connector_dpms,
1264         .detect = hdmi_conn_detect,
1265         .fill_modes = drm_helper_probe_single_connector_modes,
1266         .destroy = hdmi_conn_destroy,
1267         .reset = drm_atomic_helper_connector_reset,
1268         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1269         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1270 };
1271
1272 static const struct drm_connector_helper_funcs
1273                 mtk_hdmi_connector_helper_funcs = {
1274         .get_modes = mtk_hdmi_conn_get_modes,
1275         .mode_valid = mtk_hdmi_conn_mode_valid,
1276         .best_encoder = mtk_hdmi_conn_best_enc,
1277 };
1278
1279 static void mtk_hdmi_hpd_event(bool hpd, struct device *dev)
1280 {
1281         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1282
1283         if (hdmi && hdmi->bridge.encoder && hdmi->bridge.encoder->dev)
1284                 drm_helper_hpd_irq_event(hdmi->bridge.encoder->dev);
1285 }
1286
1287 /*
1288  * Bridge callbacks
1289  */
1290
1291 static int mtk_hdmi_bridge_attach(struct drm_bridge *bridge)
1292 {
1293         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1294         int ret;
1295
1296         ret = drm_connector_init(bridge->encoder->dev, &hdmi->conn,
1297                                  &mtk_hdmi_connector_funcs,
1298                                  DRM_MODE_CONNECTOR_HDMIA);
1299         if (ret) {
1300                 dev_err(hdmi->dev, "Failed to initialize connector: %d\n", ret);
1301                 return ret;
1302         }
1303         drm_connector_helper_add(&hdmi->conn, &mtk_hdmi_connector_helper_funcs);
1304
1305         hdmi->conn.polled = DRM_CONNECTOR_POLL_HPD;
1306         hdmi->conn.interlace_allowed = true;
1307         hdmi->conn.doublescan_allowed = false;
1308
1309         ret = drm_mode_connector_attach_encoder(&hdmi->conn,
1310                                                 bridge->encoder);
1311         if (ret) {
1312                 dev_err(hdmi->dev,
1313                         "Failed to attach connector to encoder: %d\n", ret);
1314                 return ret;
1315         }
1316
1317         if (bridge->next) {
1318                 bridge->next->encoder = bridge->encoder;
1319                 ret = drm_bridge_attach(bridge->encoder->dev, bridge->next);
1320                 if (ret) {
1321                         dev_err(hdmi->dev,
1322                                 "Failed to attach external bridge: %d\n", ret);
1323                         return ret;
1324                 }
1325         }
1326
1327         mtk_cec_set_hpd_event(hdmi->cec_dev, mtk_hdmi_hpd_event, hdmi->dev);
1328
1329         return 0;
1330 }
1331
1332 static bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
1333                                        const struct drm_display_mode *mode,
1334                                        struct drm_display_mode *adjusted_mode)
1335 {
1336         return true;
1337 }
1338
1339 static void mtk_hdmi_bridge_disable(struct drm_bridge *bridge)
1340 {
1341         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1342
1343         if (!hdmi->enabled)
1344                 return;
1345
1346         phy_power_off(hdmi->phy);
1347         clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
1348         clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
1349
1350         hdmi->enabled = false;
1351 }
1352
1353 static void mtk_hdmi_bridge_post_disable(struct drm_bridge *bridge)
1354 {
1355         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1356
1357         if (!hdmi->powered)
1358                 return;
1359
1360         mtk_hdmi_hw_1p4_version_enable(hdmi, true);
1361         mtk_hdmi_hw_make_reg_writable(hdmi, false);
1362
1363         hdmi->powered = false;
1364 }
1365
1366 static void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1367                                      struct drm_display_mode *mode,
1368                                      struct drm_display_mode *adjusted_mode)
1369 {
1370         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1371
1372         dev_dbg(hdmi->dev, "cur info: name:%s, hdisplay:%d\n",
1373                 adjusted_mode->name, adjusted_mode->hdisplay);
1374         dev_dbg(hdmi->dev, "hsync_start:%d,hsync_end:%d, htotal:%d",
1375                 adjusted_mode->hsync_start, adjusted_mode->hsync_end,
1376                 adjusted_mode->htotal);
1377         dev_dbg(hdmi->dev, "hskew:%d, vdisplay:%d\n",
1378                 adjusted_mode->hskew, adjusted_mode->vdisplay);
1379         dev_dbg(hdmi->dev, "vsync_start:%d, vsync_end:%d, vtotal:%d",
1380                 adjusted_mode->vsync_start, adjusted_mode->vsync_end,
1381                 adjusted_mode->vtotal);
1382         dev_dbg(hdmi->dev, "vscan:%d, flag:%d\n",
1383                 adjusted_mode->vscan, adjusted_mode->flags);
1384
1385         drm_mode_copy(&hdmi->mode, adjusted_mode);
1386 }
1387
1388 static void mtk_hdmi_bridge_pre_enable(struct drm_bridge *bridge)
1389 {
1390         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1391
1392         mtk_hdmi_hw_make_reg_writable(hdmi, true);
1393         mtk_hdmi_hw_1p4_version_enable(hdmi, true);
1394
1395         hdmi->powered = true;
1396 }
1397
1398 static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi,
1399                                     struct drm_display_mode *mode)
1400 {
1401         mtk_hdmi_setup_audio_infoframe(hdmi);
1402         mtk_hdmi_setup_avi_infoframe(hdmi, mode);
1403         mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI");
1404         if (mode->flags & DRM_MODE_FLAG_3D_MASK)
1405                 mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode);
1406 }
1407
1408 static void mtk_hdmi_bridge_enable(struct drm_bridge *bridge)
1409 {
1410         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1411
1412         mtk_hdmi_output_set_display_mode(hdmi, &hdmi->mode);
1413         clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
1414         clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
1415         phy_power_on(hdmi->phy);
1416         mtk_hdmi_send_infoframe(hdmi, &hdmi->mode);
1417
1418         hdmi->enabled = true;
1419 }
1420
1421 static const struct drm_bridge_funcs mtk_hdmi_bridge_funcs = {
1422         .attach = mtk_hdmi_bridge_attach,
1423         .mode_fixup = mtk_hdmi_bridge_mode_fixup,
1424         .disable = mtk_hdmi_bridge_disable,
1425         .post_disable = mtk_hdmi_bridge_post_disable,
1426         .mode_set = mtk_hdmi_bridge_mode_set,
1427         .pre_enable = mtk_hdmi_bridge_pre_enable,
1428         .enable = mtk_hdmi_bridge_enable,
1429 };
1430
1431 static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
1432                                    struct platform_device *pdev)
1433 {
1434         struct device *dev = &pdev->dev;
1435         struct device_node *np = dev->of_node;
1436         struct device_node *cec_np, *port, *ep, *remote, *i2c_np;
1437         struct platform_device *cec_pdev;
1438         struct regmap *regmap;
1439         struct resource *mem;
1440         int ret;
1441
1442         ret = mtk_hdmi_get_all_clk(hdmi, np);
1443         if (ret) {
1444                 dev_err(dev, "Failed to get clocks: %d\n", ret);
1445                 return ret;
1446         }
1447
1448         /* The CEC module handles HDMI hotplug detection */
1449         cec_np = of_get_compatible_child(np->parent, "mediatek,mt8173-cec");
1450         if (!cec_np) {
1451                 dev_err(dev, "Failed to find CEC node\n");
1452                 return -EINVAL;
1453         }
1454
1455         cec_pdev = of_find_device_by_node(cec_np);
1456         if (!cec_pdev) {
1457                 dev_err(hdmi->dev, "Waiting for CEC device %s\n",
1458                         cec_np->full_name);
1459                 of_node_put(cec_np);
1460                 return -EPROBE_DEFER;
1461         }
1462         of_node_put(cec_np);
1463         hdmi->cec_dev = &cec_pdev->dev;
1464
1465         /*
1466          * The mediatek,syscon-hdmi property contains a phandle link to the
1467          * MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG
1468          * registers it contains.
1469          */
1470         regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,syscon-hdmi");
1471         ret = of_property_read_u32_index(np, "mediatek,syscon-hdmi", 1,
1472                                          &hdmi->sys_offset);
1473         if (IS_ERR(regmap))
1474                 ret = PTR_ERR(regmap);
1475         if (ret) {
1476                 dev_err(dev,
1477                         "Failed to get system configuration registers: %d\n",
1478                         ret);
1479                 return ret;
1480         }
1481         hdmi->sys_regmap = regmap;
1482
1483         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1484         hdmi->regs = devm_ioremap_resource(dev, mem);
1485         if (IS_ERR(hdmi->regs))
1486                 return PTR_ERR(hdmi->regs);
1487
1488         port = of_graph_get_port_by_id(np, 1);
1489         if (!port) {
1490                 dev_err(dev, "Missing output port node\n");
1491                 return -EINVAL;
1492         }
1493
1494         ep = of_get_child_by_name(port, "endpoint");
1495         if (!ep) {
1496                 dev_err(dev, "Missing endpoint node in port %s\n",
1497                         port->full_name);
1498                 of_node_put(port);
1499                 return -EINVAL;
1500         }
1501         of_node_put(port);
1502
1503         remote = of_graph_get_remote_port_parent(ep);
1504         if (!remote) {
1505                 dev_err(dev, "Missing connector/bridge node for endpoint %s\n",
1506                         ep->full_name);
1507                 of_node_put(ep);
1508                 return -EINVAL;
1509         }
1510         of_node_put(ep);
1511
1512         if (!of_device_is_compatible(remote, "hdmi-connector")) {
1513                 hdmi->bridge.next = of_drm_find_bridge(remote);
1514                 if (!hdmi->bridge.next) {
1515                         dev_err(dev, "Waiting for external bridge\n");
1516                         of_node_put(remote);
1517                         return -EPROBE_DEFER;
1518                 }
1519         }
1520
1521         i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0);
1522         if (!i2c_np) {
1523                 dev_err(dev, "Failed to find ddc-i2c-bus node in %s\n",
1524                         remote->full_name);
1525                 of_node_put(remote);
1526                 return -EINVAL;
1527         }
1528         of_node_put(remote);
1529
1530         hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np);
1531         of_node_put(i2c_np);
1532         if (!hdmi->ddc_adpt) {
1533                 dev_err(dev, "Failed to get ddc i2c adapter by node\n");
1534                 return -EINVAL;
1535         }
1536
1537         return 0;
1538 }
1539
1540 /*
1541  * HDMI audio codec callbacks
1542  */
1543
1544 static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
1545                                     struct hdmi_codec_daifmt *daifmt,
1546                                     struct hdmi_codec_params *params)
1547 {
1548         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1549         struct hdmi_audio_param hdmi_params;
1550         unsigned int chan = params->cea.channels;
1551
1552         dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1553                 params->sample_rate, params->sample_width, chan);
1554
1555         if (!hdmi->bridge.encoder)
1556                 return -ENODEV;
1557
1558         switch (chan) {
1559         case 2:
1560                 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
1561                 break;
1562         case 4:
1563                 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_4_0;
1564                 break;
1565         case 6:
1566                 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_5_1;
1567                 break;
1568         case 8:
1569                 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_7_1;
1570                 break;
1571         default:
1572                 dev_err(hdmi->dev, "channel[%d] not supported!\n", chan);
1573                 return -EINVAL;
1574         }
1575
1576         switch (params->sample_rate) {
1577         case 32000:
1578         case 44100:
1579         case 48000:
1580         case 88200:
1581         case 96000:
1582         case 176400:
1583         case 192000:
1584                 break;
1585         default:
1586                 dev_err(hdmi->dev, "rate[%d] not supported!\n",
1587                         params->sample_rate);
1588                 return -EINVAL;
1589         }
1590
1591         switch (daifmt->fmt) {
1592         case HDMI_I2S:
1593                 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1594                 hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1595                 hdmi_params.aud_input_type = HDMI_AUD_INPUT_I2S;
1596                 hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
1597                 hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS;
1598                 break;
1599         default:
1600                 dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__,
1601                         daifmt->fmt);
1602                 return -EINVAL;
1603         }
1604
1605         memcpy(&hdmi_params.codec_params, params,
1606                sizeof(hdmi_params.codec_params));
1607
1608         mtk_hdmi_audio_set_param(hdmi, &hdmi_params);
1609
1610         return 0;
1611 }
1612
1613 static int mtk_hdmi_audio_startup(struct device *dev, void *data)
1614 {
1615         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1616
1617         dev_dbg(dev, "%s\n", __func__);
1618
1619         mtk_hdmi_audio_enable(hdmi);
1620
1621         return 0;
1622 }
1623
1624 static void mtk_hdmi_audio_shutdown(struct device *dev, void *data)
1625 {
1626         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1627
1628         dev_dbg(dev, "%s\n", __func__);
1629
1630         mtk_hdmi_audio_disable(hdmi);
1631 }
1632
1633 static int
1634 mtk_hdmi_audio_digital_mute(struct device *dev, void *data, bool enable)
1635 {
1636         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1637
1638         dev_dbg(dev, "%s(%d)\n", __func__, enable);
1639
1640         if (enable)
1641                 mtk_hdmi_hw_aud_mute(hdmi);
1642         else
1643                 mtk_hdmi_hw_aud_unmute(hdmi);
1644
1645         return 0;
1646 }
1647
1648 static int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)
1649 {
1650         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1651
1652         dev_dbg(dev, "%s\n", __func__);
1653
1654         memcpy(buf, hdmi->conn.eld, min(sizeof(hdmi->conn.eld), len));
1655
1656         return 0;
1657 }
1658
1659 static const struct hdmi_codec_ops mtk_hdmi_audio_codec_ops = {
1660         .hw_params = mtk_hdmi_audio_hw_params,
1661         .audio_startup = mtk_hdmi_audio_startup,
1662         .audio_shutdown = mtk_hdmi_audio_shutdown,
1663         .digital_mute = mtk_hdmi_audio_digital_mute,
1664         .get_eld = mtk_hdmi_audio_get_eld,
1665 };
1666
1667 static void mtk_hdmi_register_audio_driver(struct device *dev)
1668 {
1669         struct hdmi_codec_pdata codec_data = {
1670                 .ops = &mtk_hdmi_audio_codec_ops,
1671                 .max_i2s_channels = 2,
1672                 .i2s = 1,
1673         };
1674         struct platform_device *pdev;
1675
1676         pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
1677                                              PLATFORM_DEVID_AUTO, &codec_data,
1678                                              sizeof(codec_data));
1679         if (IS_ERR(pdev))
1680                 return;
1681
1682         DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME);
1683 }
1684
1685 static int mtk_drm_hdmi_probe(struct platform_device *pdev)
1686 {
1687         struct mtk_hdmi *hdmi;
1688         struct device *dev = &pdev->dev;
1689         int ret;
1690
1691         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1692         if (!hdmi)
1693                 return -ENOMEM;
1694
1695         hdmi->dev = dev;
1696
1697         ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev);
1698         if (ret)
1699                 return ret;
1700
1701         hdmi->phy = devm_phy_get(dev, "hdmi");
1702         if (IS_ERR(hdmi->phy)) {
1703                 ret = PTR_ERR(hdmi->phy);
1704                 dev_err(dev, "Failed to get HDMI PHY: %d\n", ret);
1705                 return ret;
1706         }
1707
1708         platform_set_drvdata(pdev, hdmi);
1709
1710         ret = mtk_hdmi_output_init(hdmi);
1711         if (ret) {
1712                 dev_err(dev, "Failed to initialize hdmi output\n");
1713                 return ret;
1714         }
1715
1716         mtk_hdmi_register_audio_driver(dev);
1717
1718         hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs;
1719         hdmi->bridge.of_node = pdev->dev.of_node;
1720         ret = drm_bridge_add(&hdmi->bridge);
1721         if (ret) {
1722                 dev_err(dev, "failed to add bridge, ret = %d\n", ret);
1723                 return ret;
1724         }
1725
1726         ret = mtk_hdmi_clk_enable_audio(hdmi);
1727         if (ret) {
1728                 dev_err(dev, "Failed to enable audio clocks: %d\n", ret);
1729                 goto err_bridge_remove;
1730         }
1731
1732         dev_dbg(dev, "mediatek hdmi probe success\n");
1733         return 0;
1734
1735 err_bridge_remove:
1736         drm_bridge_remove(&hdmi->bridge);
1737         return ret;
1738 }
1739
1740 static int mtk_drm_hdmi_remove(struct platform_device *pdev)
1741 {
1742         struct mtk_hdmi *hdmi = platform_get_drvdata(pdev);
1743
1744         drm_bridge_remove(&hdmi->bridge);
1745         mtk_hdmi_clk_disable_audio(hdmi);
1746         return 0;
1747 }
1748
1749 #ifdef CONFIG_PM_SLEEP
1750 static int mtk_hdmi_suspend(struct device *dev)
1751 {
1752         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1753
1754         mtk_hdmi_clk_disable_audio(hdmi);
1755         dev_dbg(dev, "hdmi suspend success!\n");
1756         return 0;
1757 }
1758
1759 static int mtk_hdmi_resume(struct device *dev)
1760 {
1761         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1762         int ret = 0;
1763
1764         ret = mtk_hdmi_clk_enable_audio(hdmi);
1765         if (ret) {
1766                 dev_err(dev, "hdmi resume failed!\n");
1767                 return ret;
1768         }
1769
1770         dev_dbg(dev, "hdmi resume success!\n");
1771         return 0;
1772 }
1773 #endif
1774 static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops,
1775                          mtk_hdmi_suspend, mtk_hdmi_resume);
1776
1777 static const struct of_device_id mtk_drm_hdmi_of_ids[] = {
1778         { .compatible = "mediatek,mt8173-hdmi", },
1779         {}
1780 };
1781
1782 static struct platform_driver mtk_hdmi_driver = {
1783         .probe = mtk_drm_hdmi_probe,
1784         .remove = mtk_drm_hdmi_remove,
1785         .driver = {
1786                 .name = "mediatek-drm-hdmi",
1787                 .of_match_table = mtk_drm_hdmi_of_ids,
1788                 .pm = &mtk_hdmi_pm_ops,
1789         },
1790 };
1791
1792 static struct platform_driver * const mtk_hdmi_drivers[] = {
1793         &mtk_hdmi_phy_driver,
1794         &mtk_hdmi_ddc_driver,
1795         &mtk_cec_driver,
1796         &mtk_hdmi_driver,
1797 };
1798
1799 static int __init mtk_hdmitx_init(void)
1800 {
1801         int ret;
1802         int i;
1803
1804         for (i = 0; i < ARRAY_SIZE(mtk_hdmi_drivers); i++) {
1805                 ret = platform_driver_register(mtk_hdmi_drivers[i]);
1806                 if (ret < 0) {
1807                         pr_err("Failed to register %s driver: %d\n",
1808                                mtk_hdmi_drivers[i]->driver.name, ret);
1809                         goto err;
1810                 }
1811         }
1812
1813         return 0;
1814
1815 err:
1816         while (--i >= 0)
1817                 platform_driver_unregister(mtk_hdmi_drivers[i]);
1818
1819         return ret;
1820 }
1821
1822 static void __exit mtk_hdmitx_exit(void)
1823 {
1824         int i;
1825
1826         for (i = ARRAY_SIZE(mtk_hdmi_drivers) - 1; i >= 0; i--)
1827                 platform_driver_unregister(mtk_hdmi_drivers[i]);
1828 }
1829
1830 module_init(mtk_hdmitx_init);
1831 module_exit(mtk_hdmitx_exit);
1832
1833 MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
1834 MODULE_DESCRIPTION("MediaTek HDMI Driver");
1835 MODULE_LICENSE("GPL v2");