drivers/gpu/drm/mediatek/mtk_dsi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015 MediaTek Inc.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/component.h>
   8 #include <linux/iopoll.h>
   9 #include <linux/irq.h>
  10 #include <linux/of.h>
  11 #include <linux/of_platform.h>
  12 #include <linux/phy/phy.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/reset.h>
  15
  16 #include <video/mipi_display.h>
  17 #include <video/videomode.h>
  18
  19 #include <drm/drm_atomic_helper.h>
  20 #include <drm/drm_bridge.h>
  21 #include <drm/drm_bridge_connector.h>
  22 #include <drm/drm_mipi_dsi.h>
  23 #include <drm/drm_of.h>
  24 #include <drm/drm_panel.h>
  25 #include <drm/drm_print.h>
  26 #include <drm/drm_probe_helper.h>
  27 #include <drm/drm_simple_kms_helper.h>
  28
  29 #include "mtk_disp_drv.h"
  30 #include "mtk_drm_ddp_comp.h"
  31
  32 #define DSI_START               0x00
  33
  34 #define DSI_INTEN               0x08
  35
  36 #define DSI_INTSTA              0x0c
  37 #define LPRX_RD_RDY_INT_FLAG            BIT(0)
  38 #define CMD_DONE_INT_FLAG               BIT(1)
  39 #define TE_RDY_INT_FLAG                 BIT(2)
  40 #define VM_DONE_INT_FLAG                BIT(3)
  41 #define EXT_TE_RDY_INT_FLAG             BIT(4)
  42 #define DSI_BUSY                        BIT(31)
  43
  44 #define DSI_CON_CTRL            0x10
  45 #define DSI_RESET                       BIT(0)
  46 #define DSI_EN                          BIT(1)
  47 #define DPHY_RESET                      BIT(2)
  48
  49 #define DSI_MODE_CTRL           0x14
  50 #define MODE                            (3)
  51 #define CMD_MODE                        0
  52 #define SYNC_PULSE_MODE                 1
  53 #define SYNC_EVENT_MODE                 2
  54 #define BURST_MODE                      3
  55 #define FRM_MODE                        BIT(16)
  56 #define MIX_MODE                        BIT(17)
  57
  58 #define DSI_TXRX_CTRL           0x18
  59 #define VC_NUM                          BIT(1)
  60 #define LANE_NUM                        (0xf << 2)
  61 #define DIS_EOT                         BIT(6)
  62 #define NULL_EN                         BIT(7)
  63 #define TE_FREERUN                      BIT(8)
  64 #define EXT_TE_EN                       BIT(9)
  65 #define EXT_TE_EDGE                     BIT(10)
  66 #define MAX_RTN_SIZE                    (0xf << 12)
  67 #define HSTX_CKLP_EN                    BIT(16)
  68
  69 #define DSI_PSCTRL              0x1c
  70 #define DSI_PS_WC                       0x3fff
  71 #define DSI_PS_SEL                      (3 << 16)
  72 #define PACKED_PS_16BIT_RGB565          (0 << 16)
  73 #define LOOSELY_PS_18BIT_RGB666         (1 << 16)
  74 #define PACKED_PS_18BIT_RGB666          (2 << 16)
  75 #define PACKED_PS_24BIT_RGB888          (3 << 16)
  76
  77 #define DSI_VSA_NL              0x20
  78 #define DSI_VBP_NL              0x24
  79 #define DSI_VFP_NL              0x28
  80 #define DSI_VACT_NL             0x2C
  81 #define DSI_SIZE_CON            0x38
  82 #define DSI_HSA_WC              0x50
  83 #define DSI_HBP_WC              0x54
  84 #define DSI_HFP_WC              0x58
  85
  86 #define DSI_CMDQ_SIZE           0x60
  87 #define CMDQ_SIZE                       0x3f
  88
  89 #define DSI_HSTX_CKL_WC         0x64
  90
  91 #define DSI_RX_DATA0            0x74
  92 #define DSI_RX_DATA1            0x78
  93 #define DSI_RX_DATA2            0x7c
  94 #define DSI_RX_DATA3            0x80
  95
  96 #define DSI_RACK                0x84
  97 #define RACK                            BIT(0)
  98
  99 #define DSI_PHY_LCCON           0x104
 100 #define LC_HS_TX_EN                     BIT(0)
 101 #define LC_ULPM_EN                      BIT(1)
 102 #define LC_WAKEUP_EN                    BIT(2)
 103
 104 #define DSI_PHY_LD0CON          0x108
 105 #define LD0_HS_TX_EN                    BIT(0)
 106 #define LD0_ULPM_EN                     BIT(1)
 107 #define LD0_WAKEUP_EN                   BIT(2)
 108
 109 #define DSI_PHY_TIMECON0        0x110
 110 #define LPX                             (0xff << 0)
 111 #define HS_PREP                         (0xff << 8)
 112 #define HS_ZERO                         (0xff << 16)
 113 #define HS_TRAIL                        (0xff << 24)
 114
 115 #define DSI_PHY_TIMECON1        0x114
 116 #define TA_GO                           (0xff << 0)
 117 #define TA_SURE                         (0xff << 8)
 118 #define TA_GET                          (0xff << 16)
 119 #define DA_HS_EXIT                      (0xff << 24)
 120
 121 #define DSI_PHY_TIMECON2        0x118
 122 #define CONT_DET                        (0xff << 0)
 123 #define CLK_ZERO                        (0xff << 16)
 124 #define CLK_TRAIL                       (0xff << 24)
 125
 126 #define DSI_PHY_TIMECON3        0x11c
 127 #define CLK_HS_PREP                     (0xff << 0)
 128 #define CLK_HS_POST                     (0xff << 8)
 129 #define CLK_HS_EXIT                     (0xff << 16)
 130
 131 #define DSI_VM_CMD_CON          0x130
 132 #define VM_CMD_EN                       BIT(0)
 133 #define TS_VFP_EN                       BIT(5)
 134
 135 #define DSI_SHADOW_DEBUG        0x190U
 136 #define FORCE_COMMIT                    BIT(0)
 137 #define BYPASS_SHADOW                   BIT(1)
 138
 139 #define CONFIG                          (0xff << 0)
 140 #define SHORT_PACKET                    0
 141 #define LONG_PACKET                     2
 142 #define BTA                             BIT(2)
 143 #define DATA_ID                         (0xff << 8)
 144 #define DATA_0                          (0xff << 16)
 145 #define DATA_1                          (0xff << 24)
 146
 147 #define NS_TO_CYCLE(n, c)    ((n) / (c) + (((n) % (c)) ? 1 : 0))
 148
 149 #define MTK_DSI_HOST_IS_READ(type) \
 150         ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
 151         (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
 152         (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
 153         (type == MIPI_DSI_DCS_READ))
 154
 155 struct mtk_phy_timing {
 156         u32 lpx;
 157         u32 da_hs_prepare;
 158         u32 da_hs_zero;
 159         u32 da_hs_trail;
 160
 161         u32 ta_go;
 162         u32 ta_sure;
 163         u32 ta_get;
 164         u32 da_hs_exit;
 165
 166         u32 clk_hs_zero;
 167         u32 clk_hs_trail;
 168
 169         u32 clk_hs_prepare;
 170         u32 clk_hs_post;
 171         u32 clk_hs_exit;
 172 };
 173
 174 struct phy;
 175
 176 struct mtk_dsi_driver_data {
 177         const u32 reg_cmdq_off;
 178         bool has_shadow_ctl;
 179         bool has_size_ctl;
 180 };
 181
 182 struct mtk_dsi {
 183         struct device *dev;
 184         struct mipi_dsi_host host;
 185         struct drm_encoder encoder;
 186         struct drm_bridge bridge;
 187         struct drm_bridge *next_bridge;
 188         struct drm_connector *connector;
 189         struct phy *phy;
 190
 191         void __iomem *regs;
 192
 193         struct clk *engine_clk;
 194         struct clk *digital_clk;
 195         struct clk *hs_clk;
 196
 197         u32 data_rate;
 198
 199         unsigned long mode_flags;
 200         enum mipi_dsi_pixel_format format;
 201         unsigned int lanes;
 202         struct videomode vm;
 203         struct mtk_phy_timing phy_timing;
 204         int refcount;
 205         bool enabled;
 206         u32 irq_data;
 207         wait_queue_head_t irq_wait_queue;
 208         const struct mtk_dsi_driver_data *driver_data;
 209 };
 210
 211 static inline struct mtk_dsi *bridge_to_dsi(struct drm_bridge *b)
 212 {
 213         return container_of(b, struct mtk_dsi, bridge);
 214 }
 215
 216 static inline struct mtk_dsi *host_to_dsi(struct mipi_dsi_host *h)
 217 {
 218         return container_of(h, struct mtk_dsi, host);
 219 }
 220
 221 static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data)
 222 {
 223         u32 temp = readl(dsi->regs + offset);
 224
 225         writel((temp & ~mask) | (data & mask), dsi->regs + offset);
 226 }
 227
 228 static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
 229 {
 230         u32 timcon0, timcon1, timcon2, timcon3;
 231         u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, 1000000);
 232         struct mtk_phy_timing *timing = &dsi->phy_timing;
 233
 234         timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1;
 235         timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000;
 236         timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 -
 237                              timing->da_hs_prepare;
 238         timing->da_hs_trail = timing->da_hs_prepare + 1;
 239
 240         timing->ta_go = 4 * timing->lpx - 2;
 241         timing->ta_sure = timing->lpx + 2;
 242         timing->ta_get = 4 * timing->lpx;
 243         timing->da_hs_exit = 2 * timing->lpx + 1;
 244
 245         timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000);
 246         timing->clk_hs_post = timing->clk_hs_prepare + 8;
 247         timing->clk_hs_trail = timing->clk_hs_prepare;
 248         timing->clk_hs_zero = timing->clk_hs_trail * 4;
 249         timing->clk_hs_exit = 2 * timing->clk_hs_trail;
 250
 251         timcon0 = timing->lpx | timing->da_hs_prepare << 8 |
 252                   timing->da_hs_zero << 16 | timing->da_hs_trail << 24;
 253         timcon1 = timing->ta_go | timing->ta_sure << 8 |
 254                   timing->ta_get << 16 | timing->da_hs_exit << 24;
 255         timcon2 = 1 << 8 | timing->clk_hs_zero << 16 |
 256                   timing->clk_hs_trail << 24;
 257         timcon3 = timing->clk_hs_prepare | timing->clk_hs_post << 8 |
 258                   timing->clk_hs_exit << 16;
 259
 260         writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
 261         writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
 262         writel(timcon2, dsi->regs + DSI_PHY_TIMECON2);
 263         writel(timcon3, dsi->regs + DSI_PHY_TIMECON3);
 264 }
 265
 266 static void mtk_dsi_enable(struct mtk_dsi *dsi)
 267 {
 268         mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, DSI_EN);
 269 }
 270
 271 static void mtk_dsi_disable(struct mtk_dsi *dsi)
 272 {
 273         mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0);
 274 }
 275
 276 static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
 277 {
 278         mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET);
 279         mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
 280 }
 281
 282 static void mtk_dsi_reset_dphy(struct mtk_dsi *dsi)
 283 {
 284         mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, DPHY_RESET);
 285         mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, 0);
 286 }
 287
 288 static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
 289 {
 290         mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
 291         mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
 292 }
 293
 294 static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi)
 295 {
 296         mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
 297         mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN);
 298         mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0);
 299 }
 300
 301 static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi)
 302 {
 303         mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0);
 304         mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
 305 }
 306
 307 static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi)
 308 {
 309         mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
 310         mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN);
 311         mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0);
 312 }
 313
 314 static bool mtk_dsi_clk_hs_state(struct mtk_dsi *dsi)
 315 {
 316         return readl(dsi->regs + DSI_PHY_LCCON) & LC_HS_TX_EN;
 317 }
 318
 319 static void mtk_dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter)
 320 {
 321         if (enter && !mtk_dsi_clk_hs_state(dsi))
 322                 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN);
 323         else if (!enter && mtk_dsi_clk_hs_state(dsi))
 324                 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
 325 }
 326
 327 static void mtk_dsi_set_mode(struct mtk_dsi *dsi)
 328 {
 329         u32 vid_mode = CMD_MODE;
 330
 331         if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
 332                 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
 333                         vid_mode = BURST_MODE;
 334                 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
 335                         vid_mode = SYNC_PULSE_MODE;
 336                 else
 337                         vid_mode = SYNC_EVENT_MODE;
 338         }
 339
 340         writel(vid_mode, dsi->regs + DSI_MODE_CTRL);
 341 }
 342
 343 static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi)
 344 {
 345         mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, VM_CMD_EN);
 346         mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN);
 347 }
 348
 349 static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi)
 350 {
 351         struct videomode *vm = &dsi->vm;
 352         u32 dsi_buf_bpp, ps_wc;
 353         u32 ps_bpp_mode;
 354
 355         if (dsi->format == MIPI_DSI_FMT_RGB565)
 356                 dsi_buf_bpp = 2;
 357         else
 358                 dsi_buf_bpp = 3;
 359
 360         ps_wc = vm->hactive * dsi_buf_bpp;
 361         ps_bpp_mode = ps_wc;
 362
 363         switch (dsi->format) {
 364         case MIPI_DSI_FMT_RGB888:
 365                 ps_bpp_mode |= PACKED_PS_24BIT_RGB888;
 366                 break;
 367         case MIPI_DSI_FMT_RGB666:
 368                 ps_bpp_mode |= PACKED_PS_18BIT_RGB666;
 369                 break;
 370         case MIPI_DSI_FMT_RGB666_PACKED:
 371                 ps_bpp_mode |= LOOSELY_PS_18BIT_RGB666;
 372                 break;
 373         case MIPI_DSI_FMT_RGB565:
 374                 ps_bpp_mode |= PACKED_PS_16BIT_RGB565;
 375                 break;
 376         }
 377
 378         writel(vm->vactive, dsi->regs + DSI_VACT_NL);
 379         writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL);
 380         writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC);
 381 }
 382
 383 static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi)
 384 {
 385         u32 tmp_reg;
 386
 387         switch (dsi->lanes) {
 388         case 1:
 389                 tmp_reg = 1 << 2;
 390                 break;
 391         case 2:
 392                 tmp_reg = 3 << 2;
 393                 break;
 394         case 3:
 395                 tmp_reg = 7 << 2;
 396                 break;
 397         case 4:
 398                 tmp_reg = 0xf << 2;
 399                 break;
 400         default:
 401                 tmp_reg = 0xf << 2;
 402                 break;
 403         }
 404
 405         if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
 406                 tmp_reg |= HSTX_CKLP_EN;
 407
 408         if (!(dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET))
 409                 tmp_reg |= DIS_EOT;
 410
 411         writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL);
 412 }
 413
 414 static void mtk_dsi_ps_control(struct mtk_dsi *dsi)
 415 {
 416         u32 dsi_tmp_buf_bpp;
 417         u32 tmp_reg;
 418
 419         switch (dsi->format) {
 420         case MIPI_DSI_FMT_RGB888:
 421                 tmp_reg = PACKED_PS_24BIT_RGB888;
 422                 dsi_tmp_buf_bpp = 3;
 423                 break;
 424         case MIPI_DSI_FMT_RGB666:
 425                 tmp_reg = LOOSELY_PS_18BIT_RGB666;
 426                 dsi_tmp_buf_bpp = 3;
 427                 break;
 428         case MIPI_DSI_FMT_RGB666_PACKED:
 429                 tmp_reg = PACKED_PS_18BIT_RGB666;
 430                 dsi_tmp_buf_bpp = 3;
 431                 break;
 432         case MIPI_DSI_FMT_RGB565:
 433                 tmp_reg = PACKED_PS_16BIT_RGB565;
 434                 dsi_tmp_buf_bpp = 2;
 435                 break;
 436         default:
 437                 tmp_reg = PACKED_PS_24BIT_RGB888;
 438                 dsi_tmp_buf_bpp = 3;
 439                 break;
 440         }
 441
 442         tmp_reg += dsi->vm.hactive * dsi_tmp_buf_bpp & DSI_PS_WC;
 443         writel(tmp_reg, dsi->regs + DSI_PSCTRL);
 444 }
 445
 446 static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
 447 {
 448         u32 horizontal_sync_active_byte;
 449         u32 horizontal_backporch_byte;
 450         u32 horizontal_frontporch_byte;
 451         u32 horizontal_front_back_byte;
 452         u32 data_phy_cycles_byte;
 453         u32 dsi_tmp_buf_bpp, data_phy_cycles;
 454         u32 delta;
 455         struct mtk_phy_timing *timing = &dsi->phy_timing;
 456
 457         struct videomode *vm = &dsi->vm;
 458
 459         if (dsi->format == MIPI_DSI_FMT_RGB565)
 460                 dsi_tmp_buf_bpp = 2;
 461         else
 462                 dsi_tmp_buf_bpp = 3;
 463
 464         writel(vm->vsync_len, dsi->regs + DSI_VSA_NL);
 465         writel(vm->vback_porch, dsi->regs + DSI_VBP_NL);
 466         writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
 467         writel(vm->vactive, dsi->regs + DSI_VACT_NL);
 468
 469         if (dsi->driver_data->has_size_ctl)
 470                 writel(vm->vactive << 16 | vm->hactive,
 471                        dsi->regs + DSI_SIZE_CON);
 472
 473         horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
 474
 475         if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
 476                 horizontal_backporch_byte = vm->hback_porch * dsi_tmp_buf_bpp - 10;
 477         else
 478                 horizontal_backporch_byte = (vm->hback_porch + vm->hsync_len) *
 479                                             dsi_tmp_buf_bpp - 10;
 480
 481         data_phy_cycles = timing->lpx + timing->da_hs_prepare +
 482                           timing->da_hs_zero + timing->da_hs_exit + 3;
 483
 484         delta = dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST ? 18 : 12;
 485         delta += dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET ? 2 : 0;
 486
 487         horizontal_frontporch_byte = vm->hfront_porch * dsi_tmp_buf_bpp;
 488         horizontal_front_back_byte = horizontal_frontporch_byte + horizontal_backporch_byte;
 489         data_phy_cycles_byte = data_phy_cycles * dsi->lanes + delta;
 490
 491         if (horizontal_front_back_byte > data_phy_cycles_byte) {
 492                 horizontal_frontporch_byte -= data_phy_cycles_byte *
 493                                               horizontal_frontporch_byte /
 494                                               horizontal_front_back_byte;
 495
 496                 horizontal_backporch_byte -= data_phy_cycles_byte *
 497                                              horizontal_backporch_byte /
 498                                              horizontal_front_back_byte;
 499         } else {
 500                 DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
 501         }
 502
 503         if ((dsi->mode_flags & MIPI_DSI_HS_PKT_END_ALIGNED) &&
 504             (dsi->lanes == 4)) {
 505                 horizontal_sync_active_byte =
 506                         roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
 507                 horizontal_frontporch_byte =
 508                         roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
 509                 horizontal_backporch_byte =
 510                         roundup(horizontal_backporch_byte, dsi->lanes) - 2;
 511                 horizontal_backporch_byte -=
 512                         (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes;
 513         }
 514
 515         writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
 516         writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
 517         writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
 518
 519         mtk_dsi_ps_control(dsi);
 520 }
 521
 522 static void mtk_dsi_start(struct mtk_dsi *dsi)
 523 {
 524         writel(0, dsi->regs + DSI_START);
 525         writel(1, dsi->regs + DSI_START);
 526 }
 527
 528 static void mtk_dsi_stop(struct mtk_dsi *dsi)
 529 {
 530         writel(0, dsi->regs + DSI_START);
 531 }
 532
 533 static void mtk_dsi_set_cmd_mode(struct mtk_dsi *dsi)
 534 {
 535         writel(CMD_MODE, dsi->regs + DSI_MODE_CTRL);
 536 }
 537
 538 static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi)
 539 {
 540         u32 inten = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
 541
 542         writel(inten, dsi->regs + DSI_INTEN);
 543 }
 544
 545 static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit)
 546 {
 547         dsi->irq_data |= irq_bit;
 548 }
 549
 550 static void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit)
 551 {
 552         dsi->irq_data &= ~irq_bit;
 553 }
 554
 555 static s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag,
 556                                      unsigned int timeout)
 557 {
 558         s32 ret = 0;
 559         unsigned long jiffies = msecs_to_jiffies(timeout);
 560
 561         ret = wait_event_interruptible_timeout(dsi->irq_wait_queue,
 562                                                dsi->irq_data & irq_flag,
 563                                                jiffies);
 564         if (ret == 0) {
 565                 DRM_WARN("Wait DSI IRQ(0x%08x) Timeout\n", irq_flag);
 566
 567                 mtk_dsi_enable(dsi);
 568                 mtk_dsi_reset_engine(dsi);
 569         }
 570
 571         return ret;
 572 }
 573
 574 static irqreturn_t mtk_dsi_irq(int irq, void *dev_id)
 575 {
 576         struct mtk_dsi *dsi = dev_id;
 577         u32 status, tmp;
 578         u32 flag = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
 579
 580         status = readl(dsi->regs + DSI_INTSTA) & flag;
 581
 582         if (status) {
 583                 do {
 584                         mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK);
 585                         tmp = readl(dsi->regs + DSI_INTSTA);
 586                 } while (tmp & DSI_BUSY);
 587
 588                 mtk_dsi_mask(dsi, DSI_INTSTA, status, 0);
 589                 mtk_dsi_irq_data_set(dsi, status);
 590                 wake_up_interruptible(&dsi->irq_wait_queue);
 591         }
 592
 593         return IRQ_HANDLED;
 594 }
 595
 596 static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t)
 597 {
 598         mtk_dsi_irq_data_clear(dsi, irq_flag);
 599         mtk_dsi_set_cmd_mode(dsi);
 600
 601         if (!mtk_dsi_wait_for_irq_done(dsi, irq_flag, t)) {
 602                 DRM_ERROR("failed to switch cmd mode\n");
 603                 return -ETIME;
 604         } else {
 605                 return 0;
 606         }
 607 }
 608
 609 static int mtk_dsi_poweron(struct mtk_dsi *dsi)
 610 {
 611         struct device *dev = dsi->host.dev;
 612         int ret;
 613         u32 bit_per_pixel;
 614
 615         if (++dsi->refcount != 1)
 616                 return 0;
 617
 618         switch (dsi->format) {
 619         case MIPI_DSI_FMT_RGB565:
 620                 bit_per_pixel = 16;
 621                 break;
 622         case MIPI_DSI_FMT_RGB666_PACKED:
 623                 bit_per_pixel = 18;
 624                 break;
 625         case MIPI_DSI_FMT_RGB666:
 626         case MIPI_DSI_FMT_RGB888:
 627         default:
 628                 bit_per_pixel = 24;
 629                 break;
 630         }
 631
 632         dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel,
 633                                           dsi->lanes);
 634
 635         ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
 636         if (ret < 0) {
 637                 dev_err(dev, "Failed to set data rate: %d\n", ret);
 638                 goto err_refcount;
 639         }
 640
 641         phy_power_on(dsi->phy);
 642
 643         ret = clk_prepare_enable(dsi->engine_clk);
 644         if (ret < 0) {
 645                 dev_err(dev, "Failed to enable engine clock: %d\n", ret);
 646                 goto err_phy_power_off;
 647         }
 648
 649         ret = clk_prepare_enable(dsi->digital_clk);
 650         if (ret < 0) {
 651                 dev_err(dev, "Failed to enable digital clock: %d\n", ret);
 652                 goto err_disable_engine_clk;
 653         }
 654
 655         mtk_dsi_enable(dsi);
 656
 657         if (dsi->driver_data->has_shadow_ctl)
 658                 writel(FORCE_COMMIT | BYPASS_SHADOW,
 659                        dsi->regs + DSI_SHADOW_DEBUG);
 660
 661         mtk_dsi_reset_engine(dsi);
 662         mtk_dsi_phy_timconfig(dsi);
 663
 664         mtk_dsi_rxtx_control(dsi);
 665         usleep_range(30, 100);
 666         mtk_dsi_reset_dphy(dsi);
 667         mtk_dsi_ps_control_vact(dsi);
 668         mtk_dsi_set_vm_cmd(dsi);
 669         mtk_dsi_config_vdo_timing(dsi);
 670         mtk_dsi_set_interrupt_enable(dsi);
 671
 672         mtk_dsi_clk_ulp_mode_leave(dsi);
 673         mtk_dsi_lane0_ulp_mode_leave(dsi);
 674         mtk_dsi_clk_hs_mode(dsi, 0);
 675
 676         return 0;
 677 err_disable_engine_clk:
 678         clk_disable_unprepare(dsi->engine_clk);
 679 err_phy_power_off:
 680         phy_power_off(dsi->phy);
 681 err_refcount:
 682         dsi->refcount--;
 683         return ret;
 684 }
 685
 686 static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
 687 {
 688         if (WARN_ON(dsi->refcount == 0))
 689                 return;
 690
 691         if (--dsi->refcount != 0)
 692                 return;
 693
 694         /*
 695          * mtk_dsi_stop() and mtk_dsi_start() is asymmetric, since
 696          * mtk_dsi_stop() should be called after mtk_drm_crtc_atomic_disable(),
 697          * which needs irq for vblank, and mtk_dsi_stop() will disable irq.
 698          * mtk_dsi_start() needs to be called in mtk_output_dsi_enable(),
 699          * after dsi is fully set.
 700          */
 701         mtk_dsi_stop(dsi);
 702
 703         mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500);
 704         mtk_dsi_reset_engine(dsi);
 705         mtk_dsi_lane0_ulp_mode_enter(dsi);
 706         mtk_dsi_clk_ulp_mode_enter(dsi);
 707
 708         mtk_dsi_disable(dsi);
 709
 710         clk_disable_unprepare(dsi->engine_clk);
 711         clk_disable_unprepare(dsi->digital_clk);
 712
 713         phy_power_off(dsi->phy);
 714 }
 715
 716 static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
 717 {
 718         int ret;
 719
 720         if (dsi->enabled)
 721                 return;
 722
 723         ret = mtk_dsi_poweron(dsi);
 724         if (ret < 0) {
 725                 DRM_ERROR("failed to power on dsi\n");
 726                 return;
 727         }
 728
 729         mtk_dsi_set_mode(dsi);
 730         mtk_dsi_clk_hs_mode(dsi, 1);
 731
 732         mtk_dsi_start(dsi);
 733
 734         dsi->enabled = true;
 735 }
 736
 737 static void mtk_output_dsi_disable(struct mtk_dsi *dsi)
 738 {
 739         if (!dsi->enabled)
 740                 return;
 741
 742         mtk_dsi_poweroff(dsi);
 743
 744         dsi->enabled = false;
 745 }
 746
 747 static int mtk_dsi_bridge_attach(struct drm_bridge *bridge,
 748                                  enum drm_bridge_attach_flags flags)
 749 {
 750         struct mtk_dsi *dsi = bridge_to_dsi(bridge);
 751
 752         /* Attach the panel or bridge to the dsi bridge */
 753         return drm_bridge_attach(bridge->encoder, dsi->next_bridge,
 754                                  &dsi->bridge, flags);
 755 }
 756
 757 static void mtk_dsi_bridge_mode_set(struct drm_bridge *bridge,
 758                                     const struct drm_display_mode *mode,
 759                                     const struct drm_display_mode *adjusted)
 760 {
 761         struct mtk_dsi *dsi = bridge_to_dsi(bridge);
 762
 763         drm_display_mode_to_videomode(adjusted, &dsi->vm);
 764 }
 765
 766 static void mtk_dsi_bridge_disable(struct drm_bridge *bridge)
 767 {
 768         struct mtk_dsi *dsi = bridge_to_dsi(bridge);
 769
 770         mtk_output_dsi_disable(dsi);
 771 }
 772
 773 static void mtk_dsi_bridge_enable(struct drm_bridge *bridge)
 774 {
 775         struct mtk_dsi *dsi = bridge_to_dsi(bridge);
 776
 777         mtk_output_dsi_enable(dsi);
 778 }
 779
 780 static const struct drm_bridge_funcs mtk_dsi_bridge_funcs = {
 781         .attach = mtk_dsi_bridge_attach,
 782         .disable = mtk_dsi_bridge_disable,
 783         .enable = mtk_dsi_bridge_enable,
 784         .mode_set = mtk_dsi_bridge_mode_set,
 785 };
 786
 787 void mtk_dsi_ddp_start(struct device *dev)
 788 {
 789         struct mtk_dsi *dsi = dev_get_drvdata(dev);
 790
 791         mtk_dsi_poweron(dsi);
 792 }
 793
 794 void mtk_dsi_ddp_stop(struct device *dev)
 795 {
 796         struct mtk_dsi *dsi = dev_get_drvdata(dev);
 797
 798         mtk_dsi_poweroff(dsi);
 799 }
 800
 801 static int mtk_dsi_encoder_init(struct drm_device *drm, struct mtk_dsi *dsi)
 802 {
 803         int ret;
 804
 805         ret = drm_simple_encoder_init(drm, &dsi->encoder,
 806                                       DRM_MODE_ENCODER_DSI);
 807         if (ret) {
 808                 DRM_ERROR("Failed to encoder init to drm\n");
 809                 return ret;
 810         }
 811
 812         dsi->encoder.possible_crtcs = mtk_drm_find_possible_crtc_by_comp(drm, dsi->host.dev);
 813
 814         ret = drm_bridge_attach(&dsi->encoder, &dsi->bridge, NULL,
 815                                 DRM_BRIDGE_ATTACH_NO_CONNECTOR);
 816         if (ret)
 817                 goto err_cleanup_encoder;
 818
 819         dsi->connector = drm_bridge_connector_init(drm, &dsi->encoder);
 820         if (IS_ERR(dsi->connector)) {
 821                 DRM_ERROR("Unable to create bridge connector\n");
 822                 ret = PTR_ERR(dsi->connector);
 823                 goto err_cleanup_encoder;
 824         }
 825         drm_connector_attach_encoder(dsi->connector, &dsi->encoder);
 826
 827         return 0;
 828
 829 err_cleanup_encoder:
 830         drm_encoder_cleanup(&dsi->encoder);
 831         return ret;
 832 }
 833
 834 static int mtk_dsi_bind(struct device *dev, struct device *master, void *data)
 835 {
 836         int ret;
 837         struct drm_device *drm = data;
 838         struct mtk_dsi *dsi = dev_get_drvdata(dev);
 839
 840         ret = mtk_dsi_encoder_init(drm, dsi);
 841         if (ret)
 842                 return ret;
 843
 844         return device_reset_optional(dev);
 845 }
 846
 847 static void mtk_dsi_unbind(struct device *dev, struct device *master,
 848                            void *data)
 849 {
 850         struct mtk_dsi *dsi = dev_get_drvdata(dev);
 851
 852         drm_encoder_cleanup(&dsi->encoder);
 853 }
 854
 855 static const struct component_ops mtk_dsi_component_ops = {
 856         .bind = mtk_dsi_bind,
 857         .unbind = mtk_dsi_unbind,
 858 };
 859
 860 static int mtk_dsi_host_attach(struct mipi_dsi_host *host,
 861                                struct mipi_dsi_device *device)
 862 {
 863         struct mtk_dsi *dsi = host_to_dsi(host);
 864         struct device *dev = host->dev;
 865         int ret;
 866
 867         dsi->lanes = device->lanes;
 868         dsi->format = device->format;
 869         dsi->mode_flags = device->mode_flags;
 870         dsi->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 0, 0);
 871         if (IS_ERR(dsi->next_bridge))
 872                 return PTR_ERR(dsi->next_bridge);
 873
 874         drm_bridge_add(&dsi->bridge);
 875
 876         ret = component_add(host->dev, &mtk_dsi_component_ops);
 877         if (ret) {
 878                 DRM_ERROR("failed to add dsi_host component: %d\n", ret);
 879                 drm_bridge_remove(&dsi->bridge);
 880                 return ret;
 881         }
 882
 883         return 0;
 884 }
 885
 886 static int mtk_dsi_host_detach(struct mipi_dsi_host *host,
 887                                struct mipi_dsi_device *device)
 888 {
 889         struct mtk_dsi *dsi = host_to_dsi(host);
 890
 891         component_del(host->dev, &mtk_dsi_component_ops);
 892         drm_bridge_remove(&dsi->bridge);
 893         return 0;
 894 }
 895
 896 static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi)
 897 {
 898         int ret;
 899         u32 val;
 900
 901         ret = readl_poll_timeout(dsi->regs + DSI_INTSTA, val, !(val & DSI_BUSY),
 902                                  4, 2000000);
 903         if (ret) {
 904                 DRM_WARN("polling dsi wait not busy timeout!\n");
 905
 906                 mtk_dsi_enable(dsi);
 907                 mtk_dsi_reset_engine(dsi);
 908         }
 909 }
 910
 911 static u32 mtk_dsi_recv_cnt(u8 type, u8 *read_data)
 912 {
 913         switch (type) {
 914         case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
 915         case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
 916                 return 1;
 917         case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
 918         case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
 919                 return 2;
 920         case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
 921         case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
 922                 return read_data[1] + read_data[2] * 16;
 923         case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
 924                 DRM_INFO("type is 0x02, try again\n");
 925                 break;
 926         default:
 927                 DRM_INFO("type(0x%x) not recognized\n", type);
 928                 break;
 929         }
 930
 931         return 0;
 932 }
 933
 934 static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg)
 935 {
 936         const char *tx_buf = msg->tx_buf;
 937         u8 config, cmdq_size, cmdq_off, type = msg->type;
 938         u32 reg_val, cmdq_mask, i;
 939         u32 reg_cmdq_off = dsi->driver_data->reg_cmdq_off;
 940
 941         if (MTK_DSI_HOST_IS_READ(type))
 942                 config = BTA;
 943         else
 944                 config = (msg->tx_len > 2) ? LONG_PACKET : SHORT_PACKET;
 945
 946         if (msg->tx_len > 2) {
 947                 cmdq_size = 1 + (msg->tx_len + 3) / 4;
 948                 cmdq_off = 4;
 949                 cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1;
 950                 reg_val = (msg->tx_len << 16) | (type << 8) | config;
 951         } else {
 952                 cmdq_size = 1;
 953                 cmdq_off = 2;
 954                 cmdq_mask = CONFIG | DATA_ID;
 955                 reg_val = (type << 8) | config;
 956         }
 957
 958         for (i = 0; i < msg->tx_len; i++)
 959                 mtk_dsi_mask(dsi, (reg_cmdq_off + cmdq_off + i) & (~0x3U),
 960                              (0xffUL << (((i + cmdq_off) & 3U) * 8U)),
 961                              tx_buf[i] << (((i + cmdq_off) & 3U) * 8U));
 962
 963         mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val);
 964         mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
 965 }
 966
 967 static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi,
 968                                      const struct mipi_dsi_msg *msg, u8 flag)
 969 {
 970         mtk_dsi_wait_for_idle(dsi);
 971         mtk_dsi_irq_data_clear(dsi, flag);
 972         mtk_dsi_cmdq(dsi, msg);
 973         mtk_dsi_start(dsi);
 974
 975         if (!mtk_dsi_wait_for_irq_done(dsi, flag, 2000))
 976                 return -ETIME;
 977         else
 978                 return 0;
 979 }
 980
 981 static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_host *host,
 982                                      const struct mipi_dsi_msg *msg)
 983 {
 984         struct mtk_dsi *dsi = host_to_dsi(host);
 985         u32 recv_cnt, i;
 986         u8 read_data[16];
 987         void *src_addr;
 988         u8 irq_flag = CMD_DONE_INT_FLAG;
 989         u32 dsi_mode;
 990         int ret;
 991
 992         dsi_mode = readl(dsi->regs + DSI_MODE_CTRL);
 993         if (dsi_mode & MODE) {
 994                 mtk_dsi_stop(dsi);
 995                 ret = mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500);
 996                 if (ret)
 997                         goto restore_dsi_mode;
 998         }
 999
1000         if (MTK_DSI_HOST_IS_READ(msg->type))
1001                 irq_flag |= LPRX_RD_RDY_INT_FLAG;
1002
1003         ret = mtk_dsi_host_send_cmd(dsi, msg, irq_flag);
1004         if (ret)
1005                 goto restore_dsi_mode;
1006
1007         if (!MTK_DSI_HOST_IS_READ(msg->type)) {
1008                 recv_cnt = 0;
1009                 goto restore_dsi_mode;
1010         }
1011
1012         if (!msg->rx_buf) {
1013                 DRM_ERROR("dsi receive buffer size may be NULL\n");
1014                 ret = -EINVAL;
1015                 goto restore_dsi_mode;
1016         }
1017
1018         for (i = 0; i < 16; i++)
1019                 *(read_data + i) = readb(dsi->regs + DSI_RX_DATA0 + i);
1020
1021         recv_cnt = mtk_dsi_recv_cnt(read_data[0], read_data);
1022
1023         if (recv_cnt > 2)
1024                 src_addr = &read_data[4];
1025         else
1026                 src_addr = &read_data[1];
1027
1028         if (recv_cnt > 10)
1029                 recv_cnt = 10;
1030
1031         if (recv_cnt > msg->rx_len)
1032                 recv_cnt = msg->rx_len;
1033
1034         if (recv_cnt)
1035                 memcpy(msg->rx_buf, src_addr, recv_cnt);
1036
1037         DRM_INFO("dsi get %d byte data from the panel address(0x%x)\n",
1038                  recv_cnt, *((u8 *)(msg->tx_buf)));
1039
1040 restore_dsi_mode:
1041         if (dsi_mode & MODE) {
1042                 mtk_dsi_set_mode(dsi);
1043                 mtk_dsi_start(dsi);
1044         }
1045
1046         return ret < 0 ? ret : recv_cnt;
1047 }
1048
1049 static const struct mipi_dsi_host_ops mtk_dsi_ops = {
1050         .attach = mtk_dsi_host_attach,
1051         .detach = mtk_dsi_host_detach,
1052         .transfer = mtk_dsi_host_transfer,
1053 };
1054
1055 static int mtk_dsi_probe(struct platform_device *pdev)
1056 {
1057         struct mtk_dsi *dsi;
1058         struct device *dev = &pdev->dev;
1059         struct resource *regs;
1060         int irq_num;
1061         int ret;
1062
1063         dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1064         if (!dsi)
1065                 return -ENOMEM;
1066
1067         dsi->host.ops = &mtk_dsi_ops;
1068         dsi->host.dev = dev;
1069         ret = mipi_dsi_host_register(&dsi->host);
1070         if (ret < 0) {
1071                 dev_err(dev, "failed to register DSI host: %d\n", ret);
1072                 return ret;
1073         }
1074
1075         dsi->driver_data = of_device_get_match_data(dev);
1076
1077         dsi->engine_clk = devm_clk_get(dev, "engine");
1078         if (IS_ERR(dsi->engine_clk)) {
1079                 ret = PTR_ERR(dsi->engine_clk);
1080
1081                 if (ret != -EPROBE_DEFER)
1082                         dev_err(dev, "Failed to get engine clock: %d\n", ret);
1083                 goto err_unregister_host;
1084         }
1085
1086         dsi->digital_clk = devm_clk_get(dev, "digital");
1087         if (IS_ERR(dsi->digital_clk)) {
1088                 ret = PTR_ERR(dsi->digital_clk);
1089
1090                 if (ret != -EPROBE_DEFER)
1091                         dev_err(dev, "Failed to get digital clock: %d\n", ret);
1092                 goto err_unregister_host;
1093         }
1094
1095         dsi->hs_clk = devm_clk_get(dev, "hs");
1096         if (IS_ERR(dsi->hs_clk)) {
1097                 ret = PTR_ERR(dsi->hs_clk);
1098                 dev_err(dev, "Failed to get hs clock: %d\n", ret);
1099                 goto err_unregister_host;
1100         }
1101
1102         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1103         dsi->regs = devm_ioremap_resource(dev, regs);
1104         if (IS_ERR(dsi->regs)) {
1105                 ret = PTR_ERR(dsi->regs);
1106                 dev_err(dev, "Failed to ioremap memory: %d\n", ret);
1107                 goto err_unregister_host;
1108         }
1109
1110         dsi->phy = devm_phy_get(dev, "dphy");
1111         if (IS_ERR(dsi->phy)) {
1112                 ret = PTR_ERR(dsi->phy);
1113                 dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret);
1114                 goto err_unregister_host;
1115         }
1116
1117         irq_num = platform_get_irq(pdev, 0);
1118         if (irq_num < 0) {
1119                 ret = irq_num;
1120                 goto err_unregister_host;
1121         }
1122
1123         ret = devm_request_irq(&pdev->dev, irq_num, mtk_dsi_irq,
1124                                IRQF_TRIGGER_NONE, dev_name(&pdev->dev), dsi);
1125         if (ret) {
1126                 dev_err(&pdev->dev, "failed to request mediatek dsi irq\n");
1127                 goto err_unregister_host;
1128         }
1129
1130         init_waitqueue_head(&dsi->irq_wait_queue);
1131
1132         platform_set_drvdata(pdev, dsi);
1133
1134         dsi->bridge.funcs = &mtk_dsi_bridge_funcs;
1135         dsi->bridge.of_node = dev->of_node;
1136         dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
1137
1138         return 0;
1139
1140 err_unregister_host:
1141         mipi_dsi_host_unregister(&dsi->host);
1142         return ret;
1143 }
1144
1145 static int mtk_dsi_remove(struct platform_device *pdev)
1146 {
1147         struct mtk_dsi *dsi = platform_get_drvdata(pdev);
1148
1149         mtk_output_dsi_disable(dsi);
1150         mipi_dsi_host_unregister(&dsi->host);
1151
1152         return 0;
1153 }
1154
1155 static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = {
1156         .reg_cmdq_off = 0x200,
1157 };
1158
1159 static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = {
1160         .reg_cmdq_off = 0x180,
1161 };
1162
1163 static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = {
1164         .reg_cmdq_off = 0x200,
1165         .has_shadow_ctl = true,
1166         .has_size_ctl = true,
1167 };
1168
1169 static const struct of_device_id mtk_dsi_of_match[] = {
1170         { .compatible = "mediatek,mt2701-dsi",
1171           .data = &mt2701_dsi_driver_data },
1172         { .compatible = "mediatek,mt8173-dsi",
1173           .data = &mt8173_dsi_driver_data },
1174         { .compatible = "mediatek,mt8183-dsi",
1175           .data = &mt8183_dsi_driver_data },
1176         { },
1177 };
1178 MODULE_DEVICE_TABLE(of, mtk_dsi_of_match);
1179
1180 struct platform_driver mtk_dsi_driver = {
1181         .probe = mtk_dsi_probe,
1182         .remove = mtk_dsi_remove,
1183         .driver = {
1184                 .name = "mtk-dsi",
1185                 .of_match_table = mtk_dsi_of_match,
1186         },
1187 };