drivers/gpu/drm/mediatek/mtk_dsi.c

   1 /*
   2  * Copyright (c) 2015 MediaTek Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <drm/drmP.h>
  15 #include <drm/drm_atomic_helper.h>
  16 #include <drm/drm_crtc_helper.h>
  17 #include <drm/drm_mipi_dsi.h>
  18 #include <drm/drm_panel.h>
  19 #include <drm/drm_of.h>
  20 #include <linux/clk.h>
  21 #include <linux/component.h>
  22 #include <linux/iopoll.h>
  23 #include <linux/irq.h>
  24 #include <linux/of.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/phy/phy.h>
  27 #include <linux/platform_device.h>
  28 #include <video/mipi_display.h>
  29 #include <video/videomode.h>
  30
  31 #include "mtk_drm_ddp_comp.h"
  32
  33 #define DSI_START               0x00
  34
  35 #define DSI_INTEN               0x08
  36
  37 #define DSI_INTSTA              0x0c
  38 #define LPRX_RD_RDY_INT_FLAG            BIT(0)
  39 #define CMD_DONE_INT_FLAG               BIT(1)
  40 #define TE_RDY_INT_FLAG                 BIT(2)
  41 #define VM_DONE_INT_FLAG                BIT(3)
  42 #define EXT_TE_RDY_INT_FLAG             BIT(4)
  43 #define DSI_BUSY                        BIT(31)
  44
  45 #define DSI_CON_CTRL            0x10
  46 #define DSI_RESET                       BIT(0)
  47 #define DSI_EN                          BIT(1)
  48
  49 #define DSI_MODE_CTRL           0x14
  50 #define MODE                            (3)
  51 #define CMD_MODE                        0
  52 #define SYNC_PULSE_MODE                 1
  53 #define SYNC_EVENT_MODE                 2
  54 #define BURST_MODE                      3
  55 #define FRM_MODE                        BIT(16)
  56 #define MIX_MODE                        BIT(17)
  57
  58 #define DSI_TXRX_CTRL           0x18
  59 #define VC_NUM                          BIT(1)
  60 #define LANE_NUM                        (0xf << 2)
  61 #define DIS_EOT                         BIT(6)
  62 #define NULL_EN                         BIT(7)
  63 #define TE_FREERUN                      BIT(8)
  64 #define EXT_TE_EN                       BIT(9)
  65 #define EXT_TE_EDGE                     BIT(10)
  66 #define MAX_RTN_SIZE                    (0xf << 12)
  67 #define HSTX_CKLP_EN                    BIT(16)
  68
  69 #define DSI_PSCTRL              0x1c
  70 #define DSI_PS_WC                       0x3fff
  71 #define DSI_PS_SEL                      (3 << 16)
  72 #define PACKED_PS_16BIT_RGB565          (0 << 16)
  73 #define LOOSELY_PS_18BIT_RGB666         (1 << 16)
  74 #define PACKED_PS_18BIT_RGB666          (2 << 16)
  75 #define PACKED_PS_24BIT_RGB888          (3 << 16)
  76
  77 #define DSI_VSA_NL              0x20
  78 #define DSI_VBP_NL              0x24
  79 #define DSI_VFP_NL              0x28
  80 #define DSI_VACT_NL             0x2C
  81 #define DSI_HSA_WC              0x50
  82 #define DSI_HBP_WC              0x54
  83 #define DSI_HFP_WC              0x58
  84
  85 #define DSI_CMDQ_SIZE           0x60
  86 #define CMDQ_SIZE                       0x3f
  87
  88 #define DSI_HSTX_CKL_WC         0x64
  89
  90 #define DSI_RX_DATA0            0x74
  91 #define DSI_RX_DATA1            0x78
  92 #define DSI_RX_DATA2            0x7c
  93 #define DSI_RX_DATA3            0x80
  94
  95 #define DSI_RACK                0x84
  96 #define RACK                            BIT(0)
  97
  98 #define DSI_PHY_LCCON           0x104
  99 #define LC_HS_TX_EN                     BIT(0)
 100 #define LC_ULPM_EN                      BIT(1)
 101 #define LC_WAKEUP_EN                    BIT(2)
 102
 103 #define DSI_PHY_LD0CON          0x108
 104 #define LD0_HS_TX_EN                    BIT(0)
 105 #define LD0_ULPM_EN                     BIT(1)
 106 #define LD0_WAKEUP_EN                   BIT(2)
 107
 108 #define DSI_PHY_TIMECON0        0x110
 109 #define LPX                             (0xff << 0)
 110 #define HS_PREP                         (0xff << 8)
 111 #define HS_ZERO                         (0xff << 16)
 112 #define HS_TRAIL                        (0xff << 24)
 113
 114 #define DSI_PHY_TIMECON1        0x114
 115 #define TA_GO                           (0xff << 0)
 116 #define TA_SURE                         (0xff << 8)
 117 #define TA_GET                          (0xff << 16)
 118 #define DA_HS_EXIT                      (0xff << 24)
 119
 120 #define DSI_PHY_TIMECON2        0x118
 121 #define CONT_DET                        (0xff << 0)
 122 #define CLK_ZERO                        (0xff << 16)
 123 #define CLK_TRAIL                       (0xff << 24)
 124
 125 #define DSI_PHY_TIMECON3        0x11c
 126 #define CLK_HS_PREP                     (0xff << 0)
 127 #define CLK_HS_POST                     (0xff << 8)
 128 #define CLK_HS_EXIT                     (0xff << 16)
 129
 130 #define DSI_VM_CMD_CON          0x130
 131 #define VM_CMD_EN                       BIT(0)
 132 #define TS_VFP_EN                       BIT(5)
 133
 134 #define DSI_CMDQ0               0x180
 135 #define CONFIG                          (0xff << 0)
 136 #define SHORT_PACKET                    0
 137 #define LONG_PACKET                     2
 138 #define BTA                             BIT(2)
 139 #define DATA_ID                         (0xff << 8)
 140 #define DATA_0                          (0xff << 16)
 141 #define DATA_1                          (0xff << 24)
 142
 143 #define T_LPX           5
 144 #define T_HS_PREP       6
 145 #define T_HS_TRAIL      8
 146 #define T_HS_EXIT       7
 147 #define T_HS_ZERO       10
 148
 149 #define NS_TO_CYCLE(n, c)    ((n) / (c) + (((n) % (c)) ? 1 : 0))
 150
 151 #define MTK_DSI_HOST_IS_READ(type) \
 152         ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
 153         (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
 154         (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
 155         (type == MIPI_DSI_DCS_READ))
 156
 157 struct phy;
 158
 159 struct mtk_dsi {
 160         struct mtk_ddp_comp ddp_comp;
 161         struct device *dev;
 162         struct mipi_dsi_host host;
 163         struct drm_encoder encoder;
 164         struct drm_connector conn;
 165         struct drm_panel *panel;
 166         struct drm_bridge *bridge;
 167         struct phy *phy;
 168
 169         void __iomem *regs;
 170
 171         struct clk *engine_clk;
 172         struct clk *digital_clk;
 173         struct clk *hs_clk;
 174
 175         u32 data_rate;
 176
 177         unsigned long mode_flags;
 178         enum mipi_dsi_pixel_format format;
 179         unsigned int lanes;
 180         struct videomode vm;
 181         int refcount;
 182         bool enabled;
 183         u32 irq_data;
 184         wait_queue_head_t irq_wait_queue;
 185 };
 186
 187 static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e)
 188 {
 189         return container_of(e, struct mtk_dsi, encoder);
 190 }
 191
 192 static inline struct mtk_dsi *connector_to_dsi(struct drm_connector *c)
 193 {
 194         return container_of(c, struct mtk_dsi, conn);
 195 }
 196
 197 static inline struct mtk_dsi *host_to_dsi(struct mipi_dsi_host *h)
 198 {
 199         return container_of(h, struct mtk_dsi, host);
 200 }
 201
 202 static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data)
 203 {
 204         u32 temp = readl(dsi->regs + offset);
 205
 206         writel((temp & ~mask) | (data & mask), dsi->regs + offset);
 207 }
 208
 209 static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
 210 {
 211         u32 timcon0, timcon1, timcon2, timcon3;
 212         u32 ui, cycle_time;
 213
 214         ui = 1000 / dsi->data_rate + 0x01;
 215         cycle_time = 8000 / dsi->data_rate + 0x01;
 216
 217         timcon0 = T_LPX | T_HS_PREP << 8 | T_HS_ZERO << 16 | T_HS_TRAIL << 24;
 218         timcon1 = 4 * T_LPX | (3 * T_LPX / 2) << 8 | 5 * T_LPX << 16 |
 219                   T_HS_EXIT << 24;
 220         timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
 221                   (NS_TO_CYCLE(0x150, cycle_time) << 16);
 222         timcon3 = NS_TO_CYCLE(0x40, cycle_time) | (2 * T_LPX) << 16 |
 223                   NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8;
 224
 225         writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
 226         writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
 227         writel(timcon2, dsi->regs + DSI_PHY_TIMECON2);
 228         writel(timcon3, dsi->regs + DSI_PHY_TIMECON3);
 229 }
 230
 231 static void mtk_dsi_enable(struct mtk_dsi *dsi)
 232 {
 233         mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, DSI_EN);
 234 }
 235
 236 static void mtk_dsi_disable(struct mtk_dsi *dsi)
 237 {
 238         mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0);
 239 }
 240
 241 static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
 242 {
 243         mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET);
 244         mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
 245 }
 246
 247 static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
 248 {
 249         mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
 250         mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
 251 }
 252
 253 static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi)
 254 {
 255         mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
 256         mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN);
 257         mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0);
 258 }
 259
 260 static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi)
 261 {
 262         mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0);
 263         mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
 264 }
 265
 266 static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi)
 267 {
 268         mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
 269         mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN);
 270         mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0);
 271 }
 272
 273 static bool mtk_dsi_clk_hs_state(struct mtk_dsi *dsi)
 274 {
 275         u32 tmp_reg1;
 276
 277         tmp_reg1 = readl(dsi->regs + DSI_PHY_LCCON);
 278         return ((tmp_reg1 & LC_HS_TX_EN) == 1) ? true : false;
 279 }
 280
 281 static void mtk_dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter)
 282 {
 283         if (enter && !mtk_dsi_clk_hs_state(dsi))
 284                 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN);
 285         else if (!enter && mtk_dsi_clk_hs_state(dsi))
 286                 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
 287 }
 288
 289 static void mtk_dsi_set_mode(struct mtk_dsi *dsi)
 290 {
 291         u32 vid_mode = CMD_MODE;
 292
 293         if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
 294                 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
 295                         vid_mode = BURST_MODE;
 296                 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
 297                         vid_mode = SYNC_PULSE_MODE;
 298                 else
 299                         vid_mode = SYNC_EVENT_MODE;
 300         }
 301
 302         writel(vid_mode, dsi->regs + DSI_MODE_CTRL);
 303 }
 304
 305 static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi)
 306 {
 307         mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, VM_CMD_EN);
 308         mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN);
 309 }
 310
 311 static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi)
 312 {
 313         struct videomode *vm = &dsi->vm;
 314         u32 dsi_buf_bpp, ps_wc;
 315         u32 ps_bpp_mode;
 316
 317         if (dsi->format == MIPI_DSI_FMT_RGB565)
 318                 dsi_buf_bpp = 2;
 319         else
 320                 dsi_buf_bpp = 3;
 321
 322         ps_wc = vm->hactive * dsi_buf_bpp;
 323         ps_bpp_mode = ps_wc;
 324
 325         switch (dsi->format) {
 326         case MIPI_DSI_FMT_RGB888:
 327                 ps_bpp_mode |= PACKED_PS_24BIT_RGB888;
 328                 break;
 329         case MIPI_DSI_FMT_RGB666:
 330                 ps_bpp_mode |= PACKED_PS_18BIT_RGB666;
 331                 break;
 332         case MIPI_DSI_FMT_RGB666_PACKED:
 333                 ps_bpp_mode |= LOOSELY_PS_18BIT_RGB666;
 334                 break;
 335         case MIPI_DSI_FMT_RGB565:
 336                 ps_bpp_mode |= PACKED_PS_16BIT_RGB565;
 337                 break;
 338         }
 339
 340         writel(vm->vactive, dsi->regs + DSI_VACT_NL);
 341         writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL);
 342         writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC);
 343 }
 344
 345 static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi)
 346 {
 347         u32 tmp_reg;
 348
 349         switch (dsi->lanes) {
 350         case 1:
 351                 tmp_reg = 1 << 2;
 352                 break;
 353         case 2:
 354                 tmp_reg = 3 << 2;
 355                 break;
 356         case 3:
 357                 tmp_reg = 7 << 2;
 358                 break;
 359         case 4:
 360                 tmp_reg = 0xf << 2;
 361                 break;
 362         default:
 363                 tmp_reg = 0xf << 2;
 364                 break;
 365         }
 366
 367         tmp_reg |= (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6;
 368         tmp_reg |= (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3;
 369
 370         writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL);
 371 }
 372
 373 static void mtk_dsi_ps_control(struct mtk_dsi *dsi)
 374 {
 375         u32 dsi_tmp_buf_bpp;
 376         u32 tmp_reg;
 377
 378         switch (dsi->format) {
 379         case MIPI_DSI_FMT_RGB888:
 380                 tmp_reg = PACKED_PS_24BIT_RGB888;
 381                 dsi_tmp_buf_bpp = 3;
 382                 break;
 383         case MIPI_DSI_FMT_RGB666:
 384                 tmp_reg = LOOSELY_PS_18BIT_RGB666;
 385                 dsi_tmp_buf_bpp = 3;
 386                 break;
 387         case MIPI_DSI_FMT_RGB666_PACKED:
 388                 tmp_reg = PACKED_PS_18BIT_RGB666;
 389                 dsi_tmp_buf_bpp = 3;
 390                 break;
 391         case MIPI_DSI_FMT_RGB565:
 392                 tmp_reg = PACKED_PS_16BIT_RGB565;
 393                 dsi_tmp_buf_bpp = 2;
 394                 break;
 395         default:
 396                 tmp_reg = PACKED_PS_24BIT_RGB888;
 397                 dsi_tmp_buf_bpp = 3;
 398                 break;
 399         }
 400
 401         tmp_reg += dsi->vm.hactive * dsi_tmp_buf_bpp & DSI_PS_WC;
 402         writel(tmp_reg, dsi->regs + DSI_PSCTRL);
 403 }
 404
 405 static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
 406 {
 407         u32 horizontal_sync_active_byte;
 408         u32 horizontal_backporch_byte;
 409         u32 horizontal_frontporch_byte;
 410         u32 dsi_tmp_buf_bpp;
 411
 412         struct videomode *vm = &dsi->vm;
 413
 414         if (dsi->format == MIPI_DSI_FMT_RGB565)
 415                 dsi_tmp_buf_bpp = 2;
 416         else
 417                 dsi_tmp_buf_bpp = 3;
 418
 419         writel(vm->vsync_len, dsi->regs + DSI_VSA_NL);
 420         writel(vm->vback_porch, dsi->regs + DSI_VBP_NL);
 421         writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
 422         writel(vm->vactive, dsi->regs + DSI_VACT_NL);
 423
 424         horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
 425
 426         if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
 427                 horizontal_backporch_byte =
 428                         (vm->hback_porch * dsi_tmp_buf_bpp - 10);
 429         else
 430                 horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) *
 431                         dsi_tmp_buf_bpp - 10);
 432
 433         horizontal_frontporch_byte = (vm->hfront_porch * dsi_tmp_buf_bpp - 12);
 434
 435         writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
 436         writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
 437         writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
 438
 439         mtk_dsi_ps_control(dsi);
 440 }
 441
 442 static void mtk_dsi_start(struct mtk_dsi *dsi)
 443 {
 444         writel(0, dsi->regs + DSI_START);
 445         writel(1, dsi->regs + DSI_START);
 446 }
 447
 448 static void mtk_dsi_stop(struct mtk_dsi *dsi)
 449 {
 450         writel(0, dsi->regs + DSI_START);
 451 }
 452
 453 static void mtk_dsi_set_cmd_mode(struct mtk_dsi *dsi)
 454 {
 455         writel(CMD_MODE, dsi->regs + DSI_MODE_CTRL);
 456 }
 457
 458 static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi)
 459 {
 460         u32 inten = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
 461
 462         writel(inten, dsi->regs + DSI_INTEN);
 463 }
 464
 465 static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit)
 466 {
 467         dsi->irq_data |= irq_bit;
 468 }
 469
 470 static void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit)
 471 {
 472         dsi->irq_data &= ~irq_bit;
 473 }
 474
 475 static s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag,
 476                                      unsigned int timeout)
 477 {
 478         s32 ret = 0;
 479         unsigned long jiffies = msecs_to_jiffies(timeout);
 480
 481         ret = wait_event_interruptible_timeout(dsi->irq_wait_queue,
 482                                                dsi->irq_data & irq_flag,
 483                                                jiffies);
 484         if (ret == 0) {
 485                 DRM_WARN("Wait DSI IRQ(0x%08x) Timeout\n", irq_flag);
 486
 487                 mtk_dsi_enable(dsi);
 488                 mtk_dsi_reset_engine(dsi);
 489         }
 490
 491         return ret;
 492 }
 493
 494 static irqreturn_t mtk_dsi_irq(int irq, void *dev_id)
 495 {
 496         struct mtk_dsi *dsi = dev_id;
 497         u32 status, tmp;
 498         u32 flag = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
 499
 500         status = readl(dsi->regs + DSI_INTSTA) & flag;
 501
 502         if (status) {
 503                 do {
 504                         mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK);
 505                         tmp = readl(dsi->regs + DSI_INTSTA);
 506                 } while (tmp & DSI_BUSY);
 507
 508                 mtk_dsi_mask(dsi, DSI_INTSTA, status, 0);
 509                 mtk_dsi_irq_data_set(dsi, status);
 510                 wake_up_interruptible(&dsi->irq_wait_queue);
 511         }
 512
 513         return IRQ_HANDLED;
 514 }
 515
 516 static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t)
 517 {
 518         mtk_dsi_irq_data_clear(dsi, irq_flag);
 519         mtk_dsi_set_cmd_mode(dsi);
 520
 521         if (!mtk_dsi_wait_for_irq_done(dsi, irq_flag, t)) {
 522                 DRM_ERROR("failed to switch cmd mode\n");
 523                 return -ETIME;
 524         } else {
 525                 return 0;
 526         }
 527 }
 528
 529 static int mtk_dsi_poweron(struct mtk_dsi *dsi)
 530 {
 531         struct device *dev = dsi->dev;
 532         int ret;
 533         u64 pixel_clock, total_bits;
 534         u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits;
 535
 536         if (++dsi->refcount != 1)
 537                 return 0;
 538
 539         switch (dsi->format) {
 540         case MIPI_DSI_FMT_RGB565:
 541                 bit_per_pixel = 16;
 542                 break;
 543         case MIPI_DSI_FMT_RGB666_PACKED:
 544                 bit_per_pixel = 18;
 545                 break;
 546         case MIPI_DSI_FMT_RGB666:
 547         case MIPI_DSI_FMT_RGB888:
 548         default:
 549                 bit_per_pixel = 24;
 550                 break;
 551         }
 552
 553         /**
 554          * htotal_time = htotal * byte_per_pixel / num_lanes
 555          * overhead_time = lpx + hs_prepare + hs_zero + hs_trail + hs_exit
 556          * mipi_ratio = (htotal_time + overhead_time) / htotal_time
 557          * data_rate = pixel_clock * bit_per_pixel * mipi_ratio / num_lanes;
 558          */
 559         pixel_clock = dsi->vm.pixelclock;
 560         htotal = dsi->vm.hactive + dsi->vm.hback_porch + dsi->vm.hfront_porch +
 561                         dsi->vm.hsync_len;
 562         htotal_bits = htotal * bit_per_pixel;
 563
 564         overhead_cycles = T_LPX + T_HS_PREP + T_HS_ZERO + T_HS_TRAIL +
 565                         T_HS_EXIT;
 566         overhead_bits = overhead_cycles * dsi->lanes * 8;
 567         total_bits = htotal_bits + overhead_bits;
 568
 569         dsi->data_rate = DIV_ROUND_UP_ULL(pixel_clock * total_bits,
 570                                           htotal * dsi->lanes);
 571
 572         ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
 573         if (ret < 0) {
 574                 dev_err(dev, "Failed to set data rate: %d\n", ret);
 575                 goto err_refcount;
 576         }
 577
 578         phy_power_on(dsi->phy);
 579
 580         ret = clk_prepare_enable(dsi->engine_clk);
 581         if (ret < 0) {
 582                 dev_err(dev, "Failed to enable engine clock: %d\n", ret);
 583                 goto err_phy_power_off;
 584         }
 585
 586         ret = clk_prepare_enable(dsi->digital_clk);
 587         if (ret < 0) {
 588                 dev_err(dev, "Failed to enable digital clock: %d\n", ret);
 589                 goto err_disable_engine_clk;
 590         }
 591
 592         mtk_dsi_enable(dsi);
 593         mtk_dsi_reset_engine(dsi);
 594         mtk_dsi_phy_timconfig(dsi);
 595
 596         mtk_dsi_rxtx_control(dsi);
 597         mtk_dsi_ps_control_vact(dsi);
 598         mtk_dsi_set_vm_cmd(dsi);
 599         mtk_dsi_config_vdo_timing(dsi);
 600         mtk_dsi_set_interrupt_enable(dsi);
 601
 602         mtk_dsi_clk_ulp_mode_leave(dsi);
 603         mtk_dsi_lane0_ulp_mode_leave(dsi);
 604         mtk_dsi_clk_hs_mode(dsi, 0);
 605
 606         if (dsi->panel) {
 607                 if (drm_panel_prepare(dsi->panel)) {
 608                         DRM_ERROR("failed to prepare the panel\n");
 609                         goto err_disable_digital_clk;
 610                 }
 611         }
 612
 613         return 0;
 614 err_disable_digital_clk:
 615         clk_disable_unprepare(dsi->digital_clk);
 616 err_disable_engine_clk:
 617         clk_disable_unprepare(dsi->engine_clk);
 618 err_phy_power_off:
 619         phy_power_off(dsi->phy);
 620 err_refcount:
 621         dsi->refcount--;
 622         return ret;
 623 }
 624
 625 static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
 626 {
 627         if (WARN_ON(dsi->refcount == 0))
 628                 return;
 629
 630         if (--dsi->refcount != 0)
 631                 return;
 632
 633         /*
 634          * mtk_dsi_stop() and mtk_dsi_start() is asymmetric, since
 635          * mtk_dsi_stop() should be called after mtk_drm_crtc_atomic_disable(),
 636          * which needs irq for vblank, and mtk_dsi_stop() will disable irq.
 637          * mtk_dsi_start() needs to be called in mtk_output_dsi_enable(),
 638          * after dsi is fully set.
 639          */
 640         mtk_dsi_stop(dsi);
 641
 642         if (!mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500)) {
 643                 if (dsi->panel) {
 644                         if (drm_panel_unprepare(dsi->panel)) {
 645                                 DRM_ERROR("failed to unprepare the panel\n");
 646                                 return;
 647                         }
 648                 }
 649         }
 650
 651         mtk_dsi_reset_engine(dsi);
 652         mtk_dsi_lane0_ulp_mode_enter(dsi);
 653         mtk_dsi_clk_ulp_mode_enter(dsi);
 654
 655         mtk_dsi_disable(dsi);
 656
 657         clk_disable_unprepare(dsi->engine_clk);
 658         clk_disable_unprepare(dsi->digital_clk);
 659
 660         phy_power_off(dsi->phy);
 661 }
 662
 663 static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
 664 {
 665         int ret;
 666
 667         if (dsi->enabled)
 668                 return;
 669
 670         ret = mtk_dsi_poweron(dsi);
 671         if (ret < 0) {
 672                 DRM_ERROR("failed to power on dsi\n");
 673                 return;
 674         }
 675
 676         mtk_dsi_set_mode(dsi);
 677         mtk_dsi_clk_hs_mode(dsi, 1);
 678
 679         mtk_dsi_start(dsi);
 680
 681         if (dsi->panel) {
 682                 if (drm_panel_enable(dsi->panel)) {
 683                         DRM_ERROR("failed to enable the panel\n");
 684                         goto err_dsi_power_off;
 685                 }
 686         }
 687
 688         dsi->enabled = true;
 689
 690         return;
 691 err_dsi_power_off:
 692         mtk_dsi_stop(dsi);
 693         mtk_dsi_poweroff(dsi);
 694 }
 695
 696 static void mtk_output_dsi_disable(struct mtk_dsi *dsi)
 697 {
 698         if (!dsi->enabled)
 699                 return;
 700
 701         if (dsi->panel) {
 702                 if (drm_panel_disable(dsi->panel)) {
 703                         DRM_ERROR("failed to disable the panel\n");
 704                         return;
 705                 }
 706         }
 707
 708         mtk_dsi_poweroff(dsi);
 709
 710         dsi->enabled = false;
 711 }
 712
 713 static void mtk_dsi_encoder_destroy(struct drm_encoder *encoder)
 714 {
 715         drm_encoder_cleanup(encoder);
 716 }
 717
 718 static const struct drm_encoder_funcs mtk_dsi_encoder_funcs = {
 719         .destroy = mtk_dsi_encoder_destroy,
 720 };
 721
 722 static bool mtk_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
 723                                        const struct drm_display_mode *mode,
 724                                        struct drm_display_mode *adjusted_mode)
 725 {
 726         return true;
 727 }
 728
 729 static void mtk_dsi_encoder_mode_set(struct drm_encoder *encoder,
 730                                      struct drm_display_mode *mode,
 731                                      struct drm_display_mode *adjusted)
 732 {
 733         struct mtk_dsi *dsi = encoder_to_dsi(encoder);
 734
 735         drm_display_mode_to_videomode(adjusted, &dsi->vm);
 736 }
 737
 738 static void mtk_dsi_encoder_disable(struct drm_encoder *encoder)
 739 {
 740         struct mtk_dsi *dsi = encoder_to_dsi(encoder);
 741
 742         mtk_output_dsi_disable(dsi);
 743 }
 744
 745 static void mtk_dsi_encoder_enable(struct drm_encoder *encoder)
 746 {
 747         struct mtk_dsi *dsi = encoder_to_dsi(encoder);
 748
 749         mtk_output_dsi_enable(dsi);
 750 }
 751
 752 static int mtk_dsi_connector_get_modes(struct drm_connector *connector)
 753 {
 754         struct mtk_dsi *dsi = connector_to_dsi(connector);
 755
 756         return drm_panel_get_modes(dsi->panel);
 757 }
 758
 759 static const struct drm_encoder_helper_funcs mtk_dsi_encoder_helper_funcs = {
 760         .mode_fixup = mtk_dsi_encoder_mode_fixup,
 761         .mode_set = mtk_dsi_encoder_mode_set,
 762         .disable = mtk_dsi_encoder_disable,
 763         .enable = mtk_dsi_encoder_enable,
 764 };
 765
 766 static const struct drm_connector_funcs mtk_dsi_connector_funcs = {
 767         .fill_modes = drm_helper_probe_single_connector_modes,
 768         .destroy = drm_connector_cleanup,
 769         .reset = drm_atomic_helper_connector_reset,
 770         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 771         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 772 };
 773
 774 static const struct drm_connector_helper_funcs
 775         mtk_dsi_connector_helper_funcs = {
 776         .get_modes = mtk_dsi_connector_get_modes,
 777 };
 778
 779 static int mtk_dsi_create_connector(struct drm_device *drm, struct mtk_dsi *dsi)
 780 {
 781         int ret;
 782
 783         ret = drm_connector_init(drm, &dsi->conn, &mtk_dsi_connector_funcs,
 784                                  DRM_MODE_CONNECTOR_DSI);
 785         if (ret) {
 786                 DRM_ERROR("Failed to connector init to drm\n");
 787                 return ret;
 788         }
 789
 790         drm_connector_helper_add(&dsi->conn, &mtk_dsi_connector_helper_funcs);
 791
 792         dsi->conn.dpms = DRM_MODE_DPMS_OFF;
 793         drm_connector_attach_encoder(&dsi->conn, &dsi->encoder);
 794
 795         if (dsi->panel) {
 796                 ret = drm_panel_attach(dsi->panel, &dsi->conn);
 797                 if (ret) {
 798                         DRM_ERROR("Failed to attach panel to drm\n");
 799                         goto err_connector_cleanup;
 800                 }
 801         }
 802
 803         return 0;
 804
 805 err_connector_cleanup:
 806         drm_connector_cleanup(&dsi->conn);
 807         return ret;
 808 }
 809
 810 static int mtk_dsi_create_conn_enc(struct drm_device *drm, struct mtk_dsi *dsi)
 811 {
 812         int ret;
 813
 814         ret = drm_encoder_init(drm, &dsi->encoder, &mtk_dsi_encoder_funcs,
 815                                DRM_MODE_ENCODER_DSI, NULL);
 816         if (ret) {
 817                 DRM_ERROR("Failed to encoder init to drm\n");
 818                 return ret;
 819         }
 820         drm_encoder_helper_add(&dsi->encoder, &mtk_dsi_encoder_helper_funcs);
 821
 822         /*
 823          * Currently display data paths are statically assigned to a crtc each.
 824          * crtc 0 is OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0
 825          */
 826         dsi->encoder.possible_crtcs = 1;
 827
 828         /* If there's a bridge, attach to it and let it create the connector */
 829         ret = drm_bridge_attach(&dsi->encoder, dsi->bridge, NULL);
 830         if (ret) {
 831                 DRM_ERROR("Failed to attach bridge to drm\n");
 832
 833                 /* Otherwise create our own connector and attach to a panel */
 834                 ret = mtk_dsi_create_connector(drm, dsi);
 835                 if (ret)
 836                         goto err_encoder_cleanup;
 837         }
 838
 839         return 0;
 840
 841 err_encoder_cleanup:
 842         drm_encoder_cleanup(&dsi->encoder);
 843         return ret;
 844 }
 845
 846 static void mtk_dsi_destroy_conn_enc(struct mtk_dsi *dsi)
 847 {
 848         drm_encoder_cleanup(&dsi->encoder);
 849         /* Skip connector cleanup if creation was delegated to the bridge */
 850         if (dsi->conn.dev)
 851                 drm_connector_cleanup(&dsi->conn);
 852         if (dsi->panel)
 853                 drm_panel_detach(dsi->panel);
 854 }
 855
 856 static void mtk_dsi_ddp_start(struct mtk_ddp_comp *comp)
 857 {
 858         struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp);
 859
 860         mtk_dsi_poweron(dsi);
 861 }
 862
 863 static void mtk_dsi_ddp_stop(struct mtk_ddp_comp *comp)
 864 {
 865         struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp);
 866
 867         mtk_dsi_poweroff(dsi);
 868 }
 869
 870 static const struct mtk_ddp_comp_funcs mtk_dsi_funcs = {
 871         .start = mtk_dsi_ddp_start,
 872         .stop = mtk_dsi_ddp_stop,
 873 };
 874
 875 static int mtk_dsi_host_attach(struct mipi_dsi_host *host,
 876                                struct mipi_dsi_device *device)
 877 {
 878         struct mtk_dsi *dsi = host_to_dsi(host);
 879
 880         dsi->lanes = device->lanes;
 881         dsi->format = device->format;
 882         dsi->mode_flags = device->mode_flags;
 883
 884         if (dsi->conn.dev)
 885                 drm_helper_hpd_irq_event(dsi->conn.dev);
 886
 887         return 0;
 888 }
 889
 890 static int mtk_dsi_host_detach(struct mipi_dsi_host *host,
 891                                struct mipi_dsi_device *device)
 892 {
 893         struct mtk_dsi *dsi = host_to_dsi(host);
 894
 895         if (dsi->conn.dev)
 896                 drm_helper_hpd_irq_event(dsi->conn.dev);
 897
 898         return 0;
 899 }
 900
 901 static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi)
 902 {
 903         int ret;
 904         u32 val;
 905
 906         ret = readl_poll_timeout(dsi->regs + DSI_INTSTA, val, !(val & DSI_BUSY),
 907                                  4, 2000000);
 908         if (ret) {
 909                 DRM_WARN("polling dsi wait not busy timeout!\n");
 910
 911                 mtk_dsi_enable(dsi);
 912                 mtk_dsi_reset_engine(dsi);
 913         }
 914 }
 915
 916 static u32 mtk_dsi_recv_cnt(u8 type, u8 *read_data)
 917 {
 918         switch (type) {
 919         case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
 920         case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
 921                 return 1;
 922         case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
 923         case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
 924                 return 2;
 925         case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
 926         case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
 927                 return read_data[1] + read_data[2] * 16;
 928         case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
 929                 DRM_INFO("type is 0x02, try again\n");
 930                 break;
 931         default:
 932                 DRM_INFO("type(0x%x) not recognized\n", type);
 933                 break;
 934         }
 935
 936         return 0;
 937 }
 938
 939 static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg)
 940 {
 941         const char *tx_buf = msg->tx_buf;
 942         u8 config, cmdq_size, cmdq_off, type = msg->type;
 943         u32 reg_val, cmdq_mask, i;
 944
 945         if (MTK_DSI_HOST_IS_READ(type))
 946                 config = BTA;
 947         else
 948                 config = (msg->tx_len > 2) ? LONG_PACKET : SHORT_PACKET;
 949
 950         if (msg->tx_len > 2) {
 951                 cmdq_size = 1 + (msg->tx_len + 3) / 4;
 952                 cmdq_off = 4;
 953                 cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1;
 954                 reg_val = (msg->tx_len << 16) | (type << 8) | config;
 955         } else {
 956                 cmdq_size = 1;
 957                 cmdq_off = 2;
 958                 cmdq_mask = CONFIG | DATA_ID;
 959                 reg_val = (type << 8) | config;
 960         }
 961
 962         for (i = 0; i < msg->tx_len; i++)
 963                 writeb(tx_buf[i], dsi->regs + DSI_CMDQ0 + cmdq_off + i);
 964
 965         mtk_dsi_mask(dsi, DSI_CMDQ0, cmdq_mask, reg_val);
 966         mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
 967 }
 968
 969 static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi,
 970                                      const struct mipi_dsi_msg *msg, u8 flag)
 971 {
 972         mtk_dsi_wait_for_idle(dsi);
 973         mtk_dsi_irq_data_clear(dsi, flag);
 974         mtk_dsi_cmdq(dsi, msg);
 975         mtk_dsi_start(dsi);
 976
 977         if (!mtk_dsi_wait_for_irq_done(dsi, flag, 2000))
 978                 return -ETIME;
 979         else
 980                 return 0;
 981 }
 982
 983 static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_host *host,
 984                                      const struct mipi_dsi_msg *msg)
 985 {
 986         struct mtk_dsi *dsi = host_to_dsi(host);
 987         u32 recv_cnt, i;
 988         u8 read_data[16];
 989         void *src_addr;
 990         u8 irq_flag = CMD_DONE_INT_FLAG;
 991
 992         if (readl(dsi->regs + DSI_MODE_CTRL) & MODE) {
 993                 DRM_ERROR("dsi engine is not command mode\n");
 994                 return -EINVAL;
 995         }
 996
 997         if (MTK_DSI_HOST_IS_READ(msg->type))
 998                 irq_flag |= LPRX_RD_RDY_INT_FLAG;
 999
1000         if (mtk_dsi_host_send_cmd(dsi, msg, irq_flag) < 0)
1001                 return -ETIME;
1002
1003         if (!MTK_DSI_HOST_IS_READ(msg->type))
1004                 return 0;
1005
1006         if (!msg->rx_buf) {
1007                 DRM_ERROR("dsi receive buffer size may be NULL\n");
1008                 return -EINVAL;
1009         }
1010
1011         for (i = 0; i < 16; i++)
1012                 *(read_data + i) = readb(dsi->regs + DSI_RX_DATA0 + i);
1013
1014         recv_cnt = mtk_dsi_recv_cnt(read_data[0], read_data);
1015
1016         if (recv_cnt > 2)
1017                 src_addr = &read_data[4];
1018         else
1019                 src_addr = &read_data[1];
1020
1021         if (recv_cnt > 10)
1022                 recv_cnt = 10;
1023
1024         if (recv_cnt > msg->rx_len)
1025                 recv_cnt = msg->rx_len;
1026
1027         if (recv_cnt)
1028                 memcpy(msg->rx_buf, src_addr, recv_cnt);
1029
1030         DRM_INFO("dsi get %d byte data from the panel address(0x%x)\n",
1031                  recv_cnt, *((u8 *)(msg->tx_buf)));
1032
1033         return recv_cnt;
1034 }
1035
1036 static const struct mipi_dsi_host_ops mtk_dsi_ops = {
1037         .attach = mtk_dsi_host_attach,
1038         .detach = mtk_dsi_host_detach,
1039         .transfer = mtk_dsi_host_transfer,
1040 };
1041
1042 static int mtk_dsi_bind(struct device *dev, struct device *master, void *data)
1043 {
1044         int ret;
1045         struct drm_device *drm = data;
1046         struct mtk_dsi *dsi = dev_get_drvdata(dev);
1047
1048         ret = mtk_ddp_comp_register(drm, &dsi->ddp_comp);
1049         if (ret < 0) {
1050                 dev_err(dev, "Failed to register component %pOF: %d\n",
1051                         dev->of_node, ret);
1052                 return ret;
1053         }
1054
1055         ret = mipi_dsi_host_register(&dsi->host);
1056         if (ret < 0) {
1057                 dev_err(dev, "failed to register DSI host: %d\n", ret);
1058                 goto err_ddp_comp_unregister;
1059         }
1060
1061         ret = mtk_dsi_create_conn_enc(drm, dsi);
1062         if (ret) {
1063                 DRM_ERROR("Encoder create failed with %d\n", ret);
1064                 goto err_unregister;
1065         }
1066
1067         return 0;
1068
1069 err_unregister:
1070         mipi_dsi_host_unregister(&dsi->host);
1071 err_ddp_comp_unregister:
1072         mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
1073         return ret;
1074 }
1075
1076 static void mtk_dsi_unbind(struct device *dev, struct device *master,
1077                            void *data)
1078 {
1079         struct drm_device *drm = data;
1080         struct mtk_dsi *dsi = dev_get_drvdata(dev);
1081
1082         mtk_dsi_destroy_conn_enc(dsi);
1083         mipi_dsi_host_unregister(&dsi->host);
1084         mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
1085 }
1086
1087 static const struct component_ops mtk_dsi_component_ops = {
1088         .bind = mtk_dsi_bind,
1089         .unbind = mtk_dsi_unbind,
1090 };
1091
1092 static int mtk_dsi_probe(struct platform_device *pdev)
1093 {
1094         struct mtk_dsi *dsi;
1095         struct device *dev = &pdev->dev;
1096         struct resource *regs;
1097         int irq_num;
1098         int comp_id;
1099         int ret;
1100
1101         dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1102         if (!dsi)
1103                 return -ENOMEM;
1104
1105         dsi->host.ops = &mtk_dsi_ops;
1106         dsi->host.dev = dev;
1107
1108         ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
1109                                           &dsi->panel, &dsi->bridge);
1110         if (ret)
1111                 return ret;
1112
1113         dsi->engine_clk = devm_clk_get(dev, "engine");
1114         if (IS_ERR(dsi->engine_clk)) {
1115                 ret = PTR_ERR(dsi->engine_clk);
1116                 dev_err(dev, "Failed to get engine clock: %d\n", ret);
1117                 return ret;
1118         }
1119
1120         dsi->digital_clk = devm_clk_get(dev, "digital");
1121         if (IS_ERR(dsi->digital_clk)) {
1122                 ret = PTR_ERR(dsi->digital_clk);
1123                 dev_err(dev, "Failed to get digital clock: %d\n", ret);
1124                 return ret;
1125         }
1126
1127         dsi->hs_clk = devm_clk_get(dev, "hs");
1128         if (IS_ERR(dsi->hs_clk)) {
1129                 ret = PTR_ERR(dsi->hs_clk);
1130                 dev_err(dev, "Failed to get hs clock: %d\n", ret);
1131                 return ret;
1132         }
1133
1134         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1135         dsi->regs = devm_ioremap_resource(dev, regs);
1136         if (IS_ERR(dsi->regs)) {
1137                 ret = PTR_ERR(dsi->regs);
1138                 dev_err(dev, "Failed to ioremap memory: %d\n", ret);
1139                 return ret;
1140         }
1141
1142         dsi->phy = devm_phy_get(dev, "dphy");
1143         if (IS_ERR(dsi->phy)) {
1144                 ret = PTR_ERR(dsi->phy);
1145                 dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret);
1146                 return ret;
1147         }
1148
1149         comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI);
1150         if (comp_id < 0) {
1151                 dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
1152                 return comp_id;
1153         }
1154
1155         ret = mtk_ddp_comp_init(dev, dev->of_node, &dsi->ddp_comp, comp_id,
1156                                 &mtk_dsi_funcs);
1157         if (ret) {
1158                 dev_err(dev, "Failed to initialize component: %d\n", ret);
1159                 return ret;
1160         }
1161
1162         irq_num = platform_get_irq(pdev, 0);
1163         if (irq_num < 0) {
1164                 dev_err(&pdev->dev, "failed to request dsi irq resource\n");
1165                 return -EPROBE_DEFER;
1166         }
1167
1168         irq_set_status_flags(irq_num, IRQ_TYPE_LEVEL_LOW);
1169         ret = devm_request_irq(&pdev->dev, irq_num, mtk_dsi_irq,
1170                                IRQF_TRIGGER_LOW, dev_name(&pdev->dev), dsi);
1171         if (ret) {
1172                 dev_err(&pdev->dev, "failed to request mediatek dsi irq\n");
1173                 return -EPROBE_DEFER;
1174         }
1175
1176         init_waitqueue_head(&dsi->irq_wait_queue);
1177
1178         platform_set_drvdata(pdev, dsi);
1179
1180         return component_add(&pdev->dev, &mtk_dsi_component_ops);
1181 }
1182
1183 static int mtk_dsi_remove(struct platform_device *pdev)
1184 {
1185         struct mtk_dsi *dsi = platform_get_drvdata(pdev);
1186
1187         mtk_output_dsi_disable(dsi);
1188         component_del(&pdev->dev, &mtk_dsi_component_ops);
1189
1190         return 0;
1191 }
1192
1193 static const struct of_device_id mtk_dsi_of_match[] = {
1194         { .compatible = "mediatek,mt2701-dsi" },
1195         { .compatible = "mediatek,mt8173-dsi" },
1196         { },
1197 };
1198
1199 struct platform_driver mtk_dsi_driver = {
1200         .probe = mtk_dsi_probe,
1201         .remove = mtk_dsi_remove,
1202         .driver = {
1203                 .name = "mtk-dsi",
1204                 .of_match_table = mtk_dsi_of_match,
1205         },
1206 };