2 * Copyright (c) 2015 MediaTek Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <asm/barrier.h>
16 #include <drm/drm_atomic_helper.h>
17 #include <drm/drm_crtc_helper.h>
18 #include <drm/drm_plane_helper.h>
19 #include <linux/clk.h>
20 #include <linux/pm_runtime.h>
21 #include <soc/mediatek/smi.h>
23 #include "mtk_drm_drv.h"
24 #include "mtk_drm_crtc.h"
25 #include "mtk_drm_ddp.h"
26 #include "mtk_drm_ddp_comp.h"
27 #include "mtk_drm_gem.h"
28 #include "mtk_drm_plane.h"
31 * struct mtk_drm_crtc - MediaTek specific crtc structure.
33 * @enabled: records whether crtc_enable succeeded
34 * @planes: array of 4 drm_plane structures, one for each overlay plane
35 * @pending_planes: whether any plane has pending changes to be applied
36 * @config_regs: memory mapped mmsys configuration register space
37 * @mutex: handle to one of the ten disp_mutex streams
38 * @ddp_comp_nr: number of components in ddp_comp
39 * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc
45 bool pending_needs_vblank;
46 struct drm_pending_vblank_event *event;
48 struct drm_plane *planes;
49 unsigned int layer_nr;
52 void __iomem *config_regs;
53 struct mtk_disp_mutex *mutex;
54 unsigned int ddp_comp_nr;
55 struct mtk_ddp_comp **ddp_comp;
58 struct mtk_crtc_state {
59 struct drm_crtc_state base;
62 unsigned int pending_width;
63 unsigned int pending_height;
64 unsigned int pending_vrefresh;
67 static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c)
69 return container_of(c, struct mtk_drm_crtc, base);
72 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s)
74 return container_of(s, struct mtk_crtc_state, base);
77 static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
79 struct drm_crtc *crtc = &mtk_crtc->base;
82 spin_lock_irqsave(&crtc->dev->event_lock, flags);
83 drm_crtc_send_vblank_event(crtc, mtk_crtc->event);
84 drm_crtc_vblank_put(crtc);
85 mtk_crtc->event = NULL;
86 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
89 static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
91 drm_crtc_handle_vblank(&mtk_crtc->base);
92 if (mtk_crtc->pending_needs_vblank) {
93 mtk_drm_crtc_finish_page_flip(mtk_crtc);
94 mtk_crtc->pending_needs_vblank = false;
98 static void mtk_drm_crtc_destroy(struct drm_crtc *crtc)
100 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
103 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
104 clk_unprepare(mtk_crtc->ddp_comp[i]->clk);
106 mtk_disp_mutex_put(mtk_crtc->mutex);
108 drm_crtc_cleanup(crtc);
111 static void mtk_drm_crtc_reset(struct drm_crtc *crtc)
113 struct mtk_crtc_state *state;
116 __drm_atomic_helper_crtc_destroy_state(crtc->state);
118 state = to_mtk_crtc_state(crtc->state);
119 memset(state, 0, sizeof(*state));
121 state = kzalloc(sizeof(*state), GFP_KERNEL);
124 crtc->state = &state->base;
127 state->base.crtc = crtc;
130 static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc)
132 struct mtk_crtc_state *state;
134 state = kzalloc(sizeof(*state), GFP_KERNEL);
138 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
140 WARN_ON(state->base.crtc != crtc);
141 state->base.crtc = crtc;
146 static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc,
147 struct drm_crtc_state *state)
149 __drm_atomic_helper_crtc_destroy_state(state);
150 kfree(to_mtk_crtc_state(state));
153 static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc,
154 const struct drm_display_mode *mode,
155 struct drm_display_mode *adjusted_mode)
157 /* Nothing to do here, but this callback is mandatory. */
161 static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
163 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state);
165 state->pending_width = crtc->mode.hdisplay;
166 state->pending_height = crtc->mode.vdisplay;
167 state->pending_vrefresh = crtc->mode.vrefresh;
168 wmb(); /* Make sure the above parameters are set before update */
169 state->pending_config = true;
172 static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc)
174 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
175 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
177 mtk_ddp_comp_enable_vblank(comp, &mtk_crtc->base);
182 static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc)
184 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
185 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
187 mtk_ddp_comp_disable_vblank(comp);
190 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc)
195 DRM_DEBUG_DRIVER("%s\n", __func__);
196 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
197 ret = clk_enable(mtk_crtc->ddp_comp[i]->clk);
199 DRM_ERROR("Failed to enable clock %d: %d\n", i, ret);
207 clk_disable(mtk_crtc->ddp_comp[i]->clk);
211 static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc)
215 DRM_DEBUG_DRIVER("%s\n", __func__);
216 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
217 clk_disable(mtk_crtc->ddp_comp[i]->clk);
220 static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
222 struct drm_crtc *crtc = &mtk_crtc->base;
223 struct drm_connector *connector;
224 struct drm_encoder *encoder;
225 struct drm_connector_list_iter conn_iter;
226 unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC;
230 DRM_DEBUG_DRIVER("%s\n", __func__);
231 if (WARN_ON(!crtc->state))
234 width = crtc->state->adjusted_mode.hdisplay;
235 height = crtc->state->adjusted_mode.vdisplay;
236 vrefresh = crtc->state->adjusted_mode.vrefresh;
238 drm_for_each_encoder(encoder, crtc->dev) {
239 if (encoder->crtc != crtc)
242 drm_connector_list_iter_begin(crtc->dev, &conn_iter);
243 drm_for_each_connector_iter(connector, &conn_iter) {
244 if (connector->encoder != encoder)
246 if (connector->display_info.bpc != 0 &&
247 bpc > connector->display_info.bpc)
248 bpc = connector->display_info.bpc;
250 drm_connector_list_iter_end(&conn_iter);
253 ret = pm_runtime_get_sync(crtc->dev->dev);
255 DRM_ERROR("Failed to enable power domain: %d\n", ret);
259 ret = mtk_disp_mutex_prepare(mtk_crtc->mutex);
261 DRM_ERROR("Failed to enable mutex clock: %d\n", ret);
262 goto err_pm_runtime_put;
265 ret = mtk_crtc_ddp_clk_enable(mtk_crtc);
267 DRM_ERROR("Failed to enable component clocks: %d\n", ret);
268 goto err_mutex_unprepare;
271 DRM_DEBUG_DRIVER("mediatek_ddp_ddp_path_setup\n");
272 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
273 mtk_ddp_add_comp_to_path(mtk_crtc->config_regs,
274 mtk_crtc->ddp_comp[i]->id,
275 mtk_crtc->ddp_comp[i + 1]->id);
276 mtk_disp_mutex_add_comp(mtk_crtc->mutex,
277 mtk_crtc->ddp_comp[i]->id);
279 mtk_disp_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
280 mtk_disp_mutex_enable(mtk_crtc->mutex);
282 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
283 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i];
285 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc);
286 mtk_ddp_comp_start(comp);
289 /* Initially configure all planes */
290 for (i = 0; i < mtk_crtc->layer_nr; i++) {
291 struct drm_plane *plane = &mtk_crtc->planes[i];
292 struct mtk_plane_state *plane_state;
294 plane_state = to_mtk_plane_state(plane->state);
295 mtk_ddp_comp_layer_config(mtk_crtc->ddp_comp[0], i,
302 mtk_disp_mutex_unprepare(mtk_crtc->mutex);
304 pm_runtime_put(crtc->dev->dev);
308 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc)
310 struct drm_device *drm = mtk_crtc->base.dev;
311 struct drm_crtc *crtc = &mtk_crtc->base;
314 DRM_DEBUG_DRIVER("%s\n", __func__);
315 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
316 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]);
317 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
318 mtk_disp_mutex_remove_comp(mtk_crtc->mutex,
319 mtk_crtc->ddp_comp[i]->id);
320 mtk_disp_mutex_disable(mtk_crtc->mutex);
321 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
322 mtk_ddp_remove_comp_from_path(mtk_crtc->config_regs,
323 mtk_crtc->ddp_comp[i]->id,
324 mtk_crtc->ddp_comp[i + 1]->id);
325 mtk_disp_mutex_remove_comp(mtk_crtc->mutex,
326 mtk_crtc->ddp_comp[i]->id);
328 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
329 mtk_crtc_ddp_clk_disable(mtk_crtc);
330 mtk_disp_mutex_unprepare(mtk_crtc->mutex);
332 pm_runtime_put(drm->dev);
334 if (crtc->state->event && !crtc->state->active) {
335 spin_lock_irq(&crtc->dev->event_lock);
336 drm_crtc_send_vblank_event(crtc, crtc->state->event);
337 crtc->state->event = NULL;
338 spin_unlock_irq(&crtc->dev->event_lock);
342 static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
344 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
345 struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
346 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
350 * TODO: instead of updating the registers here, we should prepare
351 * working registers in atomic_commit and let the hardware command
352 * queue update module registers on vblank.
354 if (state->pending_config) {
355 mtk_ddp_comp_config(comp, state->pending_width,
356 state->pending_height,
357 state->pending_vrefresh, 0);
359 state->pending_config = false;
362 if (mtk_crtc->pending_planes) {
363 for (i = 0; i < mtk_crtc->layer_nr; i++) {
364 struct drm_plane *plane = &mtk_crtc->planes[i];
365 struct mtk_plane_state *plane_state;
367 plane_state = to_mtk_plane_state(plane->state);
369 if (plane_state->pending.config) {
370 mtk_ddp_comp_layer_config(comp, i, plane_state);
371 plane_state->pending.config = false;
374 mtk_crtc->pending_planes = false;
378 static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,
379 struct drm_crtc_state *old_state)
381 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
382 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
385 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
387 ret = mtk_smi_larb_get(comp->larb_dev);
389 DRM_ERROR("Failed to get larb: %d\n", ret);
393 ret = mtk_crtc_ddp_hw_init(mtk_crtc);
395 mtk_smi_larb_put(comp->larb_dev);
399 drm_crtc_vblank_on(crtc);
400 mtk_crtc->enabled = true;
403 static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc,
404 struct drm_crtc_state *old_state)
406 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
407 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
410 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
411 if (!mtk_crtc->enabled)
414 /* Set all pending plane state to disabled */
415 for (i = 0; i < mtk_crtc->layer_nr; i++) {
416 struct drm_plane *plane = &mtk_crtc->planes[i];
417 struct mtk_plane_state *plane_state;
419 plane_state = to_mtk_plane_state(plane->state);
420 plane_state->pending.enable = false;
421 plane_state->pending.config = true;
423 mtk_crtc->pending_planes = true;
425 /* Wait for planes to be disabled */
426 drm_crtc_wait_one_vblank(crtc);
428 drm_crtc_vblank_off(crtc);
429 mtk_crtc_ddp_hw_fini(mtk_crtc);
430 mtk_smi_larb_put(comp->larb_dev);
432 mtk_crtc->enabled = false;
435 static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc,
436 struct drm_crtc_state *old_crtc_state)
438 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state);
439 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
441 if (mtk_crtc->event && state->base.event)
442 DRM_ERROR("new event while there is still a pending event\n");
444 if (state->base.event) {
445 state->base.event->pipe = drm_crtc_index(crtc);
446 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
447 mtk_crtc->event = state->base.event;
448 state->base.event = NULL;
452 static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
453 struct drm_crtc_state *old_crtc_state)
455 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
456 struct mtk_drm_private *priv = crtc->dev->dev_private;
457 unsigned int pending_planes = 0;
461 mtk_crtc->pending_needs_vblank = true;
462 for (i = 0; i < mtk_crtc->layer_nr; i++) {
463 struct drm_plane *plane = &mtk_crtc->planes[i];
464 struct mtk_plane_state *plane_state;
466 plane_state = to_mtk_plane_state(plane->state);
467 if (plane_state->pending.dirty) {
468 plane_state->pending.config = true;
469 plane_state->pending.dirty = false;
470 pending_planes |= BIT(i);
474 mtk_crtc->pending_planes = true;
475 if (crtc->state->color_mgmt_changed)
476 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
477 mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
479 if (priv->data->shadow_register) {
480 mtk_disp_mutex_acquire(mtk_crtc->mutex);
481 mtk_crtc_ddp_config(crtc);
482 mtk_disp_mutex_release(mtk_crtc->mutex);
486 static const struct drm_crtc_funcs mtk_crtc_funcs = {
487 .set_config = drm_atomic_helper_set_config,
488 .page_flip = drm_atomic_helper_page_flip,
489 .destroy = mtk_drm_crtc_destroy,
490 .reset = mtk_drm_crtc_reset,
491 .atomic_duplicate_state = mtk_drm_crtc_duplicate_state,
492 .atomic_destroy_state = mtk_drm_crtc_destroy_state,
493 .gamma_set = drm_atomic_helper_legacy_gamma_set,
494 .enable_vblank = mtk_drm_crtc_enable_vblank,
495 .disable_vblank = mtk_drm_crtc_disable_vblank,
498 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = {
499 .mode_fixup = mtk_drm_crtc_mode_fixup,
500 .mode_set_nofb = mtk_drm_crtc_mode_set_nofb,
501 .atomic_begin = mtk_drm_crtc_atomic_begin,
502 .atomic_flush = mtk_drm_crtc_atomic_flush,
503 .atomic_enable = mtk_drm_crtc_atomic_enable,
504 .atomic_disable = mtk_drm_crtc_atomic_disable,
507 static int mtk_drm_crtc_init(struct drm_device *drm,
508 struct mtk_drm_crtc *mtk_crtc,
511 struct drm_plane *primary = NULL;
512 struct drm_plane *cursor = NULL;
515 for (i = 0; i < mtk_crtc->layer_nr; i++) {
516 if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_PRIMARY)
517 primary = &mtk_crtc->planes[i];
518 else if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_CURSOR)
519 cursor = &mtk_crtc->planes[i];
522 ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor,
523 &mtk_crtc_funcs, NULL);
525 goto err_cleanup_crtc;
527 drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs);
532 drm_crtc_cleanup(&mtk_crtc->base);
536 void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp)
538 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
539 struct mtk_drm_private *priv = crtc->dev->dev_private;
541 if (!priv->data->shadow_register)
542 mtk_crtc_ddp_config(crtc);
544 mtk_drm_finish_page_flip(mtk_crtc);
547 int mtk_drm_crtc_create(struct drm_device *drm_dev,
548 const enum mtk_ddp_comp_id *path, unsigned int path_len)
550 struct mtk_drm_private *priv = drm_dev->dev_private;
551 struct device *dev = drm_dev->dev;
552 struct mtk_drm_crtc *mtk_crtc;
553 enum drm_plane_type type;
555 int pipe = priv->num_pipes;
562 for (i = 0; i < path_len; i++) {
563 enum mtk_ddp_comp_id comp_id = path[i];
564 struct device_node *node;
566 node = priv->comp_node[comp_id];
569 "Not creating crtc %d because component %d is disabled or missing\n",
575 mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL);
579 mtk_crtc->config_regs = priv->config_regs;
580 mtk_crtc->ddp_comp_nr = path_len;
581 mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr,
582 sizeof(*mtk_crtc->ddp_comp),
584 if (!mtk_crtc->ddp_comp)
587 mtk_crtc->mutex = mtk_disp_mutex_get(priv->mutex_dev, pipe);
588 if (IS_ERR(mtk_crtc->mutex)) {
589 ret = PTR_ERR(mtk_crtc->mutex);
590 dev_err(dev, "Failed to get mutex: %d\n", ret);
594 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
595 enum mtk_ddp_comp_id comp_id = path[i];
596 struct mtk_ddp_comp *comp;
597 struct device_node *node;
599 node = priv->comp_node[comp_id];
600 comp = priv->ddp_comp[comp_id];
602 dev_err(dev, "Component %pOF not initialized\n", node);
607 ret = clk_prepare(comp->clk);
610 "Failed to prepare clock for component %pOF: %d\n",
615 mtk_crtc->ddp_comp[i] = comp;
618 mtk_crtc->layer_nr = mtk_ddp_comp_layer_nr(mtk_crtc->ddp_comp[0]);
619 mtk_crtc->planes = devm_kcalloc(dev, mtk_crtc->layer_nr,
620 sizeof(struct drm_plane),
623 for (zpos = 0; zpos < mtk_crtc->layer_nr; zpos++) {
624 type = (zpos == 0) ? DRM_PLANE_TYPE_PRIMARY :
625 (zpos == 1) ? DRM_PLANE_TYPE_CURSOR :
626 DRM_PLANE_TYPE_OVERLAY;
627 ret = mtk_plane_init(drm_dev, &mtk_crtc->planes[zpos],
633 ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe);
636 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE);
637 drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE);
644 clk_unprepare(mtk_crtc->ddp_comp[i]->clk);