drivers/gpu/drm/ingenic/ingenic-drm-drv.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Ingenic JZ47xx KMS driver
   4 //
   5 // Copyright (C) 2019, Paul Cercueil <paul@crapouillou.net>
   6
   7 #include "ingenic-drm.h"
   8
   9 #include <linux/bitfield.h>
  10 #include <linux/component.h>
  11 #include <linux/clk.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/mutex.h>
  16 #include <linux/of_device.h>
  17 #include <linux/of_reserved_mem.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pm.h>
  20 #include <linux/regmap.h>
  21
  22 #include <drm/drm_atomic.h>
  23 #include <drm/drm_atomic_helper.h>
  24 #include <drm/drm_bridge.h>
  25 #include <drm/drm_bridge_connector.h>
  26 #include <drm/drm_color_mgmt.h>
  27 #include <drm/drm_crtc.h>
  28 #include <drm/drm_crtc_helper.h>
  29 #include <drm/drm_damage_helper.h>
  30 #include <drm/drm_drv.h>
  31 #include <drm/drm_encoder.h>
  32 #include <drm/drm_gem_cma_helper.h>
  33 #include <drm/drm_fb_cma_helper.h>
  34 #include <drm/drm_fb_helper.h>
  35 #include <drm/drm_fourcc.h>
  36 #include <drm/drm_gem_atomic_helper.h>
  37 #include <drm/drm_gem_framebuffer_helper.h>
  38 #include <drm/drm_managed.h>
  39 #include <drm/drm_of.h>
  40 #include <drm/drm_panel.h>
  41 #include <drm/drm_plane.h>
  42 #include <drm/drm_plane_helper.h>
  43 #include <drm/drm_probe_helper.h>
  44 #include <drm/drm_vblank.h>
  45
  46 #define HWDESC_PALETTE 2
  47
  48 struct ingenic_dma_hwdesc {
  49         u32 next;
  50         u32 addr;
  51         u32 id;
  52         u32 cmd;
  53         /* extended hw descriptor for jz4780 */
  54         u32 offsize;
  55         u32 pagewidth;
  56         u32 cpos;
  57         u32 dessize;
  58 } __aligned(16);
  59
  60 struct ingenic_dma_hwdescs {
  61         struct ingenic_dma_hwdesc hwdesc[3];
  62         u16 palette[256] __aligned(16);
  63 };
  64
  65 struct jz_soc_info {
  66         bool needs_dev_clk;
  67         bool has_osd;
  68         bool has_alpha;
  69         bool map_noncoherent;
  70         bool use_extended_hwdesc;
  71         bool plane_f0_not_working;
  72         unsigned int max_width, max_height;
  73         const u32 *formats_f0, *formats_f1;
  74         unsigned int num_formats_f0, num_formats_f1;
  75 };
  76
  77 struct ingenic_drm_private_state {
  78         struct drm_private_state base;
  79         bool use_palette;
  80 };
  81
  82 struct ingenic_drm {
  83         struct drm_device drm;
  84         /*
  85          * f1 (aka. foreground1) is our primary plane, on top of which
  86          * f0 (aka. foreground0) can be overlayed. Z-order is fixed in
  87          * hardware and cannot be changed.
  88          */
  89         struct drm_plane f0, f1, *ipu_plane;
  90         struct drm_crtc crtc;
  91
  92         struct device *dev;
  93         struct regmap *map;
  94         struct clk *lcd_clk, *pix_clk;
  95         const struct jz_soc_info *soc_info;
  96
  97         struct ingenic_dma_hwdescs *dma_hwdescs;
  98         dma_addr_t dma_hwdescs_phys;
  99
 100         bool panel_is_sharp;
 101         bool no_vblank;
 102
 103         /*
 104          * clk_mutex is used to synchronize the pixel clock rate update with
 105          * the VBLANK. When the pixel clock's parent clock needs to be updated,
 106          * clock_nb's notifier function will lock the mutex, then wait until the
 107          * next VBLANK. At that point, the parent clock's rate can be updated,
 108          * and the mutex is then unlocked. If an atomic commit happens in the
 109          * meantime, it will lock on the mutex, effectively waiting until the
 110          * clock update process finishes. Finally, the pixel clock's rate will
 111          * be recomputed when the mutex has been released, in the pending atomic
 112          * commit, or a future one.
 113          */
 114         struct mutex clk_mutex;
 115         bool update_clk_rate;
 116         struct notifier_block clock_nb;
 117
 118         struct drm_private_obj private_obj;
 119 };
 120
 121 struct ingenic_drm_bridge {
 122         struct drm_encoder encoder;
 123         struct drm_bridge bridge, *next_bridge;
 124
 125         struct drm_bus_cfg bus_cfg;
 126 };
 127
 128 static inline struct ingenic_drm_bridge *
 129 to_ingenic_drm_bridge(struct drm_encoder *encoder)
 130 {
 131         return container_of(encoder, struct ingenic_drm_bridge, encoder);
 132 }
 133
 134 static inline struct ingenic_drm_private_state *
 135 to_ingenic_drm_priv_state(struct drm_private_state *state)
 136 {
 137         return container_of(state, struct ingenic_drm_private_state, base);
 138 }
 139
 140 static struct ingenic_drm_private_state *
 141 ingenic_drm_get_priv_state(struct ingenic_drm *priv, struct drm_atomic_state *state)
 142 {
 143         struct drm_private_state *priv_state;
 144
 145         priv_state = drm_atomic_get_private_obj_state(state, &priv->private_obj);
 146         if (IS_ERR(priv_state))
 147                 return ERR_CAST(priv_state);
 148
 149         return to_ingenic_drm_priv_state(priv_state);
 150 }
 151
 152 static struct ingenic_drm_private_state *
 153 ingenic_drm_get_new_priv_state(struct ingenic_drm *priv, struct drm_atomic_state *state)
 154 {
 155         struct drm_private_state *priv_state;
 156
 157         priv_state = drm_atomic_get_new_private_obj_state(state, &priv->private_obj);
 158         if (!priv_state)
 159                 return NULL;
 160
 161         return to_ingenic_drm_priv_state(priv_state);
 162 }
 163
 164 static bool ingenic_drm_writeable_reg(struct device *dev, unsigned int reg)
 165 {
 166         switch (reg) {
 167         case JZ_REG_LCD_IID:
 168         case JZ_REG_LCD_SA0:
 169         case JZ_REG_LCD_FID0:
 170         case JZ_REG_LCD_CMD0:
 171         case JZ_REG_LCD_SA1:
 172         case JZ_REG_LCD_FID1:
 173         case JZ_REG_LCD_CMD1:
 174                 return false;
 175         default:
 176                 return true;
 177         }
 178 }
 179
 180 static const struct regmap_config ingenic_drm_regmap_config = {
 181         .reg_bits = 32,
 182         .val_bits = 32,
 183         .reg_stride = 4,
 184
 185         .writeable_reg = ingenic_drm_writeable_reg,
 186 };
 187
 188 static inline struct ingenic_drm *drm_device_get_priv(struct drm_device *drm)
 189 {
 190         return container_of(drm, struct ingenic_drm, drm);
 191 }
 192
 193 static inline struct ingenic_drm *drm_crtc_get_priv(struct drm_crtc *crtc)
 194 {
 195         return container_of(crtc, struct ingenic_drm, crtc);
 196 }
 197
 198 static inline struct ingenic_drm *drm_nb_get_priv(struct notifier_block *nb)
 199 {
 200         return container_of(nb, struct ingenic_drm, clock_nb);
 201 }
 202
 203 static inline dma_addr_t dma_hwdesc_addr(const struct ingenic_drm *priv,
 204                                          unsigned int idx)
 205 {
 206         u32 offset = offsetof(struct ingenic_dma_hwdescs, hwdesc[idx]);
 207
 208         return priv->dma_hwdescs_phys + offset;
 209 }
 210
 211 static int ingenic_drm_update_pixclk(struct notifier_block *nb,
 212                                      unsigned long action,
 213                                      void *data)
 214 {
 215         struct ingenic_drm *priv = drm_nb_get_priv(nb);
 216
 217         switch (action) {
 218         case PRE_RATE_CHANGE:
 219                 mutex_lock(&priv->clk_mutex);
 220                 priv->update_clk_rate = true;
 221                 drm_crtc_wait_one_vblank(&priv->crtc);
 222                 return NOTIFY_OK;
 223         default:
 224                 mutex_unlock(&priv->clk_mutex);
 225                 return NOTIFY_OK;
 226         }
 227 }
 228
 229 static void ingenic_drm_bridge_atomic_enable(struct drm_bridge *bridge,
 230                                              struct drm_bridge_state *old_bridge_state)
 231 {
 232         struct ingenic_drm *priv = drm_device_get_priv(bridge->dev);
 233
 234         regmap_write(priv->map, JZ_REG_LCD_STATE, 0);
 235
 236         regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
 237                            JZ_LCD_CTRL_ENABLE | JZ_LCD_CTRL_DISABLE,
 238                            JZ_LCD_CTRL_ENABLE);
 239 }
 240
 241 static void ingenic_drm_crtc_atomic_enable(struct drm_crtc *crtc,
 242                                            struct drm_atomic_state *state)
 243 {
 244         struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 245         struct ingenic_drm_private_state *priv_state;
 246         unsigned int next_id;
 247
 248         priv_state = ingenic_drm_get_priv_state(priv, state);
 249         if (WARN_ON(IS_ERR(priv_state)))
 250                 return;
 251
 252         /* Set addresses of our DMA descriptor chains */
 253         next_id = priv_state->use_palette ? HWDESC_PALETTE : 0;
 254         regmap_write(priv->map, JZ_REG_LCD_DA0, dma_hwdesc_addr(priv, next_id));
 255         regmap_write(priv->map, JZ_REG_LCD_DA1, dma_hwdesc_addr(priv, 1));
 256
 257         drm_crtc_vblank_on(crtc);
 258 }
 259
 260 static void ingenic_drm_bridge_atomic_disable(struct drm_bridge *bridge,
 261                                               struct drm_bridge_state *old_bridge_state)
 262 {
 263         struct ingenic_drm *priv = drm_device_get_priv(bridge->dev);
 264         unsigned int var;
 265
 266         regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
 267                            JZ_LCD_CTRL_DISABLE, JZ_LCD_CTRL_DISABLE);
 268
 269         regmap_read_poll_timeout(priv->map, JZ_REG_LCD_STATE, var,
 270                                  var & JZ_LCD_STATE_DISABLED,
 271                                  1000, 0);
 272 }
 273
 274 static void ingenic_drm_crtc_atomic_disable(struct drm_crtc *crtc,
 275                                             struct drm_atomic_state *state)
 276 {
 277         drm_crtc_vblank_off(crtc);
 278 }
 279
 280 static void ingenic_drm_crtc_update_timings(struct ingenic_drm *priv,
 281                                             struct drm_display_mode *mode)
 282 {
 283         unsigned int vpe, vds, vde, vt, hpe, hds, hde, ht;
 284
 285         vpe = mode->crtc_vsync_end - mode->crtc_vsync_start;
 286         vds = mode->crtc_vtotal - mode->crtc_vsync_start;
 287         vde = vds + mode->crtc_vdisplay;
 288         vt = vde + mode->crtc_vsync_start - mode->crtc_vdisplay;
 289
 290         hpe = mode->crtc_hsync_end - mode->crtc_hsync_start;
 291         hds = mode->crtc_htotal - mode->crtc_hsync_start;
 292         hde = hds + mode->crtc_hdisplay;
 293         ht = hde + mode->crtc_hsync_start - mode->crtc_hdisplay;
 294
 295         regmap_write(priv->map, JZ_REG_LCD_VSYNC,
 296                      0 << JZ_LCD_VSYNC_VPS_OFFSET |
 297                      vpe << JZ_LCD_VSYNC_VPE_OFFSET);
 298
 299         regmap_write(priv->map, JZ_REG_LCD_HSYNC,
 300                      0 << JZ_LCD_HSYNC_HPS_OFFSET |
 301                      hpe << JZ_LCD_HSYNC_HPE_OFFSET);
 302
 303         regmap_write(priv->map, JZ_REG_LCD_VAT,
 304                      ht << JZ_LCD_VAT_HT_OFFSET |
 305                      vt << JZ_LCD_VAT_VT_OFFSET);
 306
 307         regmap_write(priv->map, JZ_REG_LCD_DAH,
 308                      hds << JZ_LCD_DAH_HDS_OFFSET |
 309                      hde << JZ_LCD_DAH_HDE_OFFSET);
 310         regmap_write(priv->map, JZ_REG_LCD_DAV,
 311                      vds << JZ_LCD_DAV_VDS_OFFSET |
 312                      vde << JZ_LCD_DAV_VDE_OFFSET);
 313
 314         if (priv->panel_is_sharp) {
 315                 regmap_write(priv->map, JZ_REG_LCD_PS, hde << 16 | (hde + 1));
 316                 regmap_write(priv->map, JZ_REG_LCD_CLS, hde << 16 | (hde + 1));
 317                 regmap_write(priv->map, JZ_REG_LCD_SPL, hpe << 16 | (hpe + 1));
 318                 regmap_write(priv->map, JZ_REG_LCD_REV, mode->htotal << 16);
 319         }
 320
 321         regmap_set_bits(priv->map, JZ_REG_LCD_CTRL,
 322                         JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16);
 323
 324         /*
 325          * IPU restart - specify how much time the LCDC will wait before
 326          * transferring a new frame from the IPU. The value is the one
 327          * suggested in the programming manual.
 328          */
 329         regmap_write(priv->map, JZ_REG_LCD_IPUR, JZ_LCD_IPUR_IPUREN |
 330                      (ht * vpe / 3) << JZ_LCD_IPUR_IPUR_LSB);
 331 }
 332
 333 static int ingenic_drm_crtc_atomic_check(struct drm_crtc *crtc,
 334                                          struct drm_atomic_state *state)
 335 {
 336         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
 337                                                                           crtc);
 338         struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 339         struct drm_plane_state *f1_state, *f0_state, *ipu_state = NULL;
 340
 341         if (crtc_state->gamma_lut &&
 342             drm_color_lut_size(crtc_state->gamma_lut) != ARRAY_SIZE(priv->dma_hwdescs->palette)) {
 343                 dev_dbg(priv->dev, "Invalid palette size\n");
 344                 return -EINVAL;
 345         }
 346
 347         if (drm_atomic_crtc_needs_modeset(crtc_state) && priv->soc_info->has_osd) {
 348                 f1_state = drm_atomic_get_plane_state(crtc_state->state,
 349                                                       &priv->f1);
 350                 if (IS_ERR(f1_state))
 351                         return PTR_ERR(f1_state);
 352
 353                 f0_state = drm_atomic_get_plane_state(crtc_state->state,
 354                                                       &priv->f0);
 355                 if (IS_ERR(f0_state))
 356                         return PTR_ERR(f0_state);
 357
 358                 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && priv->ipu_plane) {
 359                         ipu_state = drm_atomic_get_plane_state(crtc_state->state,
 360                                                                priv->ipu_plane);
 361                         if (IS_ERR(ipu_state))
 362                                 return PTR_ERR(ipu_state);
 363
 364                         /* IPU and F1 planes cannot be enabled at the same time. */
 365                         if (f1_state->fb && ipu_state->fb) {
 366                                 dev_dbg(priv->dev, "Cannot enable both F1 and IPU\n");
 367                                 return -EINVAL;
 368                         }
 369                 }
 370
 371                 /* If all the planes are disabled, we won't get a VBLANK IRQ */
 372                 priv->no_vblank = !f1_state->fb && !f0_state->fb &&
 373                                   !(ipu_state && ipu_state->fb);
 374         }
 375
 376         return 0;
 377 }
 378
 379 static enum drm_mode_status
 380 ingenic_drm_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode)
 381 {
 382         struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 383         long rate;
 384
 385         if (mode->hdisplay > priv->soc_info->max_width)
 386                 return MODE_BAD_HVALUE;
 387         if (mode->vdisplay > priv->soc_info->max_height)
 388                 return MODE_BAD_VVALUE;
 389
 390         rate = clk_round_rate(priv->pix_clk, mode->clock * 1000);
 391         if (rate < 0)
 392                 return MODE_CLOCK_RANGE;
 393
 394         return MODE_OK;
 395 }
 396
 397 static void ingenic_drm_crtc_atomic_begin(struct drm_crtc *crtc,
 398                                           struct drm_atomic_state *state)
 399 {
 400         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
 401                                                                           crtc);
 402         struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 403         u32 ctrl = 0;
 404
 405         if (priv->soc_info->has_osd &&
 406             drm_atomic_crtc_needs_modeset(crtc_state)) {
 407                 /*
 408                  * If IPU plane is enabled, enable IPU as source for the F1
 409                  * plane; otherwise use regular DMA.
 410                  */
 411                 if (priv->ipu_plane && priv->ipu_plane->state->fb)
 412                         ctrl |= JZ_LCD_OSDCTRL_IPU;
 413
 414                 regmap_update_bits(priv->map, JZ_REG_LCD_OSDCTRL,
 415                                    JZ_LCD_OSDCTRL_IPU, ctrl);
 416         }
 417 }
 418
 419 static void ingenic_drm_crtc_atomic_flush(struct drm_crtc *crtc,
 420                                           struct drm_atomic_state *state)
 421 {
 422         struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 423         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
 424                                                                           crtc);
 425         struct drm_pending_vblank_event *event = crtc_state->event;
 426
 427         if (drm_atomic_crtc_needs_modeset(crtc_state)) {
 428                 ingenic_drm_crtc_update_timings(priv, &crtc_state->adjusted_mode);
 429                 priv->update_clk_rate = true;
 430         }
 431
 432         if (priv->update_clk_rate) {
 433                 mutex_lock(&priv->clk_mutex);
 434                 clk_set_rate(priv->pix_clk,
 435                              crtc_state->adjusted_mode.crtc_clock * 1000);
 436                 priv->update_clk_rate = false;
 437                 mutex_unlock(&priv->clk_mutex);
 438         }
 439
 440         if (event) {
 441                 crtc_state->event = NULL;
 442
 443                 spin_lock_irq(&crtc->dev->event_lock);
 444                 if (drm_crtc_vblank_get(crtc) == 0)
 445                         drm_crtc_arm_vblank_event(crtc, event);
 446                 else
 447                         drm_crtc_send_vblank_event(crtc, event);
 448                 spin_unlock_irq(&crtc->dev->event_lock);
 449         }
 450 }
 451
 452 static int ingenic_drm_plane_atomic_check(struct drm_plane *plane,
 453                                           struct drm_atomic_state *state)
 454 {
 455         struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state,
 456                                                                                  plane);
 457         struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
 458                                                                                  plane);
 459         struct ingenic_drm *priv = drm_device_get_priv(plane->dev);
 460         struct ingenic_drm_private_state *priv_state;
 461         struct drm_crtc_state *crtc_state;
 462         struct drm_crtc *crtc = new_plane_state->crtc ?: old_plane_state->crtc;
 463         int ret;
 464
 465         if (!crtc)
 466                 return 0;
 467
 468         if (priv->soc_info->plane_f0_not_working && plane == &priv->f0)
 469                 return -EINVAL;
 470
 471         crtc_state = drm_atomic_get_existing_crtc_state(state,
 472                                                         crtc);
 473         if (WARN_ON(!crtc_state))
 474                 return -EINVAL;
 475
 476         priv_state = ingenic_drm_get_priv_state(priv, state);
 477         if (IS_ERR(priv_state))
 478                 return PTR_ERR(priv_state);
 479
 480         ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
 481                                                   DRM_PLANE_HELPER_NO_SCALING,
 482                                                   DRM_PLANE_HELPER_NO_SCALING,
 483                                                   priv->soc_info->has_osd,
 484                                                   true);
 485         if (ret)
 486                 return ret;
 487
 488         /*
 489          * If OSD is not available, check that the width/height match.
 490          * Note that state->src_* are in 16.16 fixed-point format.
 491          */
 492         if (!priv->soc_info->has_osd &&
 493             (new_plane_state->src_x != 0 ||
 494              (new_plane_state->src_w >> 16) != new_plane_state->crtc_w ||
 495              (new_plane_state->src_h >> 16) != new_plane_state->crtc_h))
 496                 return -EINVAL;
 497
 498         priv_state->use_palette = new_plane_state->fb &&
 499                 new_plane_state->fb->format->format == DRM_FORMAT_C8;
 500
 501         /*
 502          * Require full modeset if enabling or disabling a plane, or changing
 503          * its position, size or depth.
 504          */
 505         if (priv->soc_info->has_osd &&
 506             (!old_plane_state->fb || !new_plane_state->fb ||
 507              old_plane_state->crtc_x != new_plane_state->crtc_x ||
 508              old_plane_state->crtc_y != new_plane_state->crtc_y ||
 509              old_plane_state->crtc_w != new_plane_state->crtc_w ||
 510              old_plane_state->crtc_h != new_plane_state->crtc_h ||
 511              old_plane_state->fb->format->format != new_plane_state->fb->format->format))
 512                 crtc_state->mode_changed = true;
 513
 514         if (priv->soc_info->map_noncoherent)
 515                 drm_atomic_helper_check_plane_damage(state, new_plane_state);
 516
 517         return 0;
 518 }
 519
 520 static void ingenic_drm_plane_enable(struct ingenic_drm *priv,
 521                                      struct drm_plane *plane)
 522 {
 523         unsigned int en_bit;
 524
 525         if (priv->soc_info->has_osd) {
 526                 if (plane != &priv->f0)
 527                         en_bit = JZ_LCD_OSDC_F1EN;
 528                 else
 529                         en_bit = JZ_LCD_OSDC_F0EN;
 530
 531                 regmap_set_bits(priv->map, JZ_REG_LCD_OSDC, en_bit);
 532         }
 533 }
 534
 535 void ingenic_drm_plane_disable(struct device *dev, struct drm_plane *plane)
 536 {
 537         struct ingenic_drm *priv = dev_get_drvdata(dev);
 538         unsigned int en_bit;
 539
 540         if (priv->soc_info->has_osd) {
 541                 if (plane != &priv->f0)
 542                         en_bit = JZ_LCD_OSDC_F1EN;
 543                 else
 544                         en_bit = JZ_LCD_OSDC_F0EN;
 545
 546                 regmap_clear_bits(priv->map, JZ_REG_LCD_OSDC, en_bit);
 547         }
 548 }
 549
 550 static void ingenic_drm_plane_atomic_disable(struct drm_plane *plane,
 551                                              struct drm_atomic_state *state)
 552 {
 553         struct ingenic_drm *priv = drm_device_get_priv(plane->dev);
 554
 555         ingenic_drm_plane_disable(priv->dev, plane);
 556 }
 557
 558 void ingenic_drm_plane_config(struct device *dev,
 559                               struct drm_plane *plane, u32 fourcc)
 560 {
 561         struct ingenic_drm *priv = dev_get_drvdata(dev);
 562         struct drm_plane_state *state = plane->state;
 563         unsigned int xy_reg, size_reg;
 564         unsigned int ctrl = 0;
 565
 566         ingenic_drm_plane_enable(priv, plane);
 567
 568         if (priv->soc_info->has_osd && plane != &priv->f0) {
 569                 switch (fourcc) {
 570                 case DRM_FORMAT_XRGB1555:
 571                         ctrl |= JZ_LCD_OSDCTRL_RGB555;
 572                         fallthrough;
 573                 case DRM_FORMAT_RGB565:
 574                         ctrl |= JZ_LCD_OSDCTRL_BPP_15_16;
 575                         break;
 576                 case DRM_FORMAT_RGB888:
 577                         ctrl |= JZ_LCD_OSDCTRL_BPP_24_COMP;
 578                         break;
 579                 case DRM_FORMAT_XRGB8888:
 580                         ctrl |= JZ_LCD_OSDCTRL_BPP_18_24;
 581                         break;
 582                 case DRM_FORMAT_XRGB2101010:
 583                         ctrl |= JZ_LCD_OSDCTRL_BPP_30;
 584                         break;
 585                 }
 586
 587                 regmap_update_bits(priv->map, JZ_REG_LCD_OSDCTRL,
 588                                    JZ_LCD_OSDCTRL_BPP_MASK, ctrl);
 589         } else {
 590                 switch (fourcc) {
 591                 case DRM_FORMAT_C8:
 592                         ctrl |= JZ_LCD_CTRL_BPP_8;
 593                         break;
 594                 case DRM_FORMAT_XRGB1555:
 595                         ctrl |= JZ_LCD_CTRL_RGB555;
 596                         fallthrough;
 597                 case DRM_FORMAT_RGB565:
 598                         ctrl |= JZ_LCD_CTRL_BPP_15_16;
 599                         break;
 600                 case DRM_FORMAT_RGB888:
 601                         ctrl |= JZ_LCD_CTRL_BPP_24_COMP;
 602                         break;
 603                 case DRM_FORMAT_XRGB8888:
 604                         ctrl |= JZ_LCD_CTRL_BPP_18_24;
 605                         break;
 606                 case DRM_FORMAT_XRGB2101010:
 607                         ctrl |= JZ_LCD_CTRL_BPP_30;
 608                         break;
 609                 }
 610
 611                 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
 612                                    JZ_LCD_CTRL_BPP_MASK, ctrl);
 613         }
 614
 615         if (priv->soc_info->has_osd) {
 616                 if (plane != &priv->f0) {
 617                         xy_reg = JZ_REG_LCD_XYP1;
 618                         size_reg = JZ_REG_LCD_SIZE1;
 619                 } else {
 620                         xy_reg = JZ_REG_LCD_XYP0;
 621                         size_reg = JZ_REG_LCD_SIZE0;
 622                 }
 623
 624                 regmap_write(priv->map, xy_reg,
 625                              state->crtc_x << JZ_LCD_XYP01_XPOS_LSB |
 626                              state->crtc_y << JZ_LCD_XYP01_YPOS_LSB);
 627                 regmap_write(priv->map, size_reg,
 628                              state->crtc_w << JZ_LCD_SIZE01_WIDTH_LSB |
 629                              state->crtc_h << JZ_LCD_SIZE01_HEIGHT_LSB);
 630         }
 631 }
 632
 633 bool ingenic_drm_map_noncoherent(const struct device *dev)
 634 {
 635         const struct ingenic_drm *priv = dev_get_drvdata(dev);
 636
 637         return priv->soc_info->map_noncoherent;
 638 }
 639
 640 static void ingenic_drm_update_palette(struct ingenic_drm *priv,
 641                                        const struct drm_color_lut *lut)
 642 {
 643         unsigned int i;
 644
 645         for (i = 0; i < ARRAY_SIZE(priv->dma_hwdescs->palette); i++) {
 646                 u16 color = drm_color_lut_extract(lut[i].red, 5) << 11
 647                         | drm_color_lut_extract(lut[i].green, 6) << 5
 648                         | drm_color_lut_extract(lut[i].blue, 5);
 649
 650                 priv->dma_hwdescs->palette[i] = color;
 651         }
 652 }
 653
 654 static void ingenic_drm_plane_atomic_update(struct drm_plane *plane,
 655                                             struct drm_atomic_state *state)
 656 {
 657         struct ingenic_drm *priv = drm_device_get_priv(plane->dev);
 658         struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state, plane);
 659         struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state, plane);
 660         unsigned int width, height, cpp, next_id, plane_id;
 661         struct ingenic_drm_private_state *priv_state;
 662         struct drm_crtc_state *crtc_state;
 663         struct ingenic_dma_hwdesc *hwdesc;
 664         dma_addr_t addr;
 665         u32 fourcc;
 666
 667         if (newstate && newstate->fb) {
 668                 if (priv->soc_info->map_noncoherent)
 669                         drm_fb_cma_sync_non_coherent(&priv->drm, oldstate, newstate);
 670
 671                 crtc_state = newstate->crtc->state;
 672                 plane_id = !!(priv->soc_info->has_osd && plane != &priv->f0);
 673
 674                 addr = drm_fb_cma_get_gem_addr(newstate->fb, newstate, 0);
 675                 width = newstate->src_w >> 16;
 676                 height = newstate->src_h >> 16;
 677                 cpp = newstate->fb->format->cpp[0];
 678
 679                 priv_state = ingenic_drm_get_new_priv_state(priv, state);
 680                 next_id = (priv_state && priv_state->use_palette) ? HWDESC_PALETTE : plane_id;
 681
 682                 hwdesc = &priv->dma_hwdescs->hwdesc[plane_id];
 683                 hwdesc->addr = addr;
 684                 hwdesc->cmd = JZ_LCD_CMD_EOF_IRQ | (width * height * cpp / 4);
 685                 hwdesc->next = dma_hwdesc_addr(priv, next_id);
 686
 687                 if (priv->soc_info->use_extended_hwdesc) {
 688                         hwdesc->cmd |= JZ_LCD_CMD_FRM_ENABLE;
 689
 690                         /* Extended 8-byte descriptor */
 691                         hwdesc->cpos = 0;
 692                         hwdesc->offsize = 0;
 693                         hwdesc->pagewidth = 0;
 694
 695                         switch (newstate->fb->format->format) {
 696                         case DRM_FORMAT_XRGB1555:
 697                                 hwdesc->cpos |= JZ_LCD_CPOS_RGB555;
 698                                 fallthrough;
 699                         case DRM_FORMAT_RGB565:
 700                                 hwdesc->cpos |= JZ_LCD_CPOS_BPP_15_16;
 701                                 break;
 702                         case DRM_FORMAT_XRGB8888:
 703                                 hwdesc->cpos |= JZ_LCD_CPOS_BPP_18_24;
 704                                 break;
 705                         }
 706                         hwdesc->cpos |= (JZ_LCD_CPOS_COEFFICIENT_1 <<
 707                                          JZ_LCD_CPOS_COEFFICIENT_OFFSET);
 708                         hwdesc->dessize =
 709                                 (0xff << JZ_LCD_DESSIZE_ALPHA_OFFSET) |
 710                                 FIELD_PREP(JZ_LCD_DESSIZE_HEIGHT_MASK, height - 1) |
 711                                 FIELD_PREP(JZ_LCD_DESSIZE_WIDTH_MASK, width - 1);
 712                 }
 713
 714                 if (drm_atomic_crtc_needs_modeset(crtc_state)) {
 715                         fourcc = newstate->fb->format->format;
 716
 717                         ingenic_drm_plane_config(priv->dev, plane, fourcc);
 718
 719                         crtc_state->color_mgmt_changed = fourcc == DRM_FORMAT_C8;
 720                 }
 721
 722                 if (crtc_state->color_mgmt_changed)
 723                         ingenic_drm_update_palette(priv, crtc_state->gamma_lut->data);
 724         }
 725 }
 726
 727 static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder,
 728                                                 struct drm_crtc_state *crtc_state,
 729                                                 struct drm_connector_state *conn_state)
 730 {
 731         struct ingenic_drm *priv = drm_device_get_priv(encoder->dev);
 732         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 733         struct ingenic_drm_bridge *bridge = to_ingenic_drm_bridge(encoder);
 734         unsigned int cfg, rgbcfg = 0;
 735
 736         priv->panel_is_sharp = bridge->bus_cfg.flags & DRM_BUS_FLAG_SHARP_SIGNALS;
 737
 738         if (priv->panel_is_sharp) {
 739                 cfg = JZ_LCD_CFG_MODE_SPECIAL_TFT_1 | JZ_LCD_CFG_REV_POLARITY;
 740         } else {
 741                 cfg = JZ_LCD_CFG_PS_DISABLE | JZ_LCD_CFG_CLS_DISABLE
 742                     | JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE;
 743         }
 744
 745         if (priv->soc_info->use_extended_hwdesc)
 746                 cfg |= JZ_LCD_CFG_DESCRIPTOR_8;
 747
 748         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 749                 cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW;
 750         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 751                 cfg |= JZ_LCD_CFG_VSYNC_ACTIVE_LOW;
 752         if (bridge->bus_cfg.flags & DRM_BUS_FLAG_DE_LOW)
 753                 cfg |= JZ_LCD_CFG_DE_ACTIVE_LOW;
 754         if (bridge->bus_cfg.flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
 755                 cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE;
 756
 757         if (!priv->panel_is_sharp) {
 758                 if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_TV) {
 759                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 760                                 cfg |= JZ_LCD_CFG_MODE_TV_OUT_I;
 761                         else
 762                                 cfg |= JZ_LCD_CFG_MODE_TV_OUT_P;
 763                 } else {
 764                         switch (bridge->bus_cfg.format) {
 765                         case MEDIA_BUS_FMT_RGB565_1X16:
 766                                 cfg |= JZ_LCD_CFG_MODE_GENERIC_16BIT;
 767                                 break;
 768                         case MEDIA_BUS_FMT_RGB666_1X18:
 769                                 cfg |= JZ_LCD_CFG_MODE_GENERIC_18BIT;
 770                                 break;
 771                         case MEDIA_BUS_FMT_RGB888_1X24:
 772                                 cfg |= JZ_LCD_CFG_MODE_GENERIC_24BIT;
 773                                 break;
 774                         case MEDIA_BUS_FMT_RGB888_3X8_DELTA:
 775                                 rgbcfg = JZ_LCD_RGBC_EVEN_GBR | JZ_LCD_RGBC_ODD_RGB;
 776                                 fallthrough;
 777                         case MEDIA_BUS_FMT_RGB888_3X8:
 778                                 cfg |= JZ_LCD_CFG_MODE_8BIT_SERIAL;
 779                                 break;
 780                         default:
 781                                 break;
 782                         }
 783                 }
 784         }
 785
 786         regmap_write(priv->map, JZ_REG_LCD_CFG, cfg);
 787         regmap_write(priv->map, JZ_REG_LCD_RGBC, rgbcfg);
 788 }
 789
 790 static int ingenic_drm_bridge_attach(struct drm_bridge *bridge,
 791                                      enum drm_bridge_attach_flags flags)
 792 {
 793         struct ingenic_drm_bridge *ib = to_ingenic_drm_bridge(bridge->encoder);
 794
 795         return drm_bridge_attach(bridge->encoder, ib->next_bridge,
 796                                  &ib->bridge, flags);
 797 }
 798
 799 static int ingenic_drm_bridge_atomic_check(struct drm_bridge *bridge,
 800                                            struct drm_bridge_state *bridge_state,
 801                                            struct drm_crtc_state *crtc_state,
 802                                            struct drm_connector_state *conn_state)
 803 {
 804         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 805         struct ingenic_drm_bridge *ib = to_ingenic_drm_bridge(bridge->encoder);
 806
 807         ib->bus_cfg = bridge_state->output_bus_cfg;
 808
 809         if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_TV)
 810                 return 0;
 811
 812         switch (bridge_state->output_bus_cfg.format) {
 813         case MEDIA_BUS_FMT_RGB888_3X8:
 814         case MEDIA_BUS_FMT_RGB888_3X8_DELTA:
 815                 /*
 816                  * The LCD controller expects timing values in dot-clock ticks,
 817                  * which is 3x the timing values in pixels when using a 3x8-bit
 818                  * display; but it will count the display area size in pixels
 819                  * either way. Go figure.
 820                  */
 821                 mode->crtc_clock = mode->clock * 3;
 822                 mode->crtc_hsync_start = mode->hsync_start * 3 - mode->hdisplay * 2;
 823                 mode->crtc_hsync_end = mode->hsync_end * 3 - mode->hdisplay * 2;
 824                 mode->crtc_hdisplay = mode->hdisplay;
 825                 mode->crtc_htotal = mode->htotal * 3 - mode->hdisplay * 2;
 826                 return 0;
 827         case MEDIA_BUS_FMT_RGB565_1X16:
 828         case MEDIA_BUS_FMT_RGB666_1X18:
 829         case MEDIA_BUS_FMT_RGB888_1X24:
 830                 return 0;
 831         default:
 832                 return -EINVAL;
 833         }
 834 }
 835
 836 static u32 *
 837 ingenic_drm_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
 838                                              struct drm_bridge_state *bridge_state,
 839                                              struct drm_crtc_state *crtc_state,
 840                                              struct drm_connector_state *conn_state,
 841                                              u32 output_fmt,
 842                                              unsigned int *num_input_fmts)
 843 {
 844         switch (output_fmt) {
 845         case MEDIA_BUS_FMT_RGB888_1X24:
 846         case MEDIA_BUS_FMT_RGB666_1X18:
 847         case MEDIA_BUS_FMT_RGB565_1X16:
 848         case MEDIA_BUS_FMT_RGB888_3X8:
 849         case MEDIA_BUS_FMT_RGB888_3X8_DELTA:
 850                 break;
 851         default:
 852                 *num_input_fmts = 0;
 853                 return NULL;
 854         }
 855
 856         return drm_atomic_helper_bridge_propagate_bus_fmt(bridge, bridge_state,
 857                                                           crtc_state, conn_state,
 858                                                           output_fmt,
 859                                                           num_input_fmts);
 860 }
 861
 862 static irqreturn_t ingenic_drm_irq_handler(int irq, void *arg)
 863 {
 864         struct ingenic_drm *priv = drm_device_get_priv(arg);
 865         unsigned int state;
 866
 867         regmap_read(priv->map, JZ_REG_LCD_STATE, &state);
 868
 869         regmap_update_bits(priv->map, JZ_REG_LCD_STATE,
 870                            JZ_LCD_STATE_EOF_IRQ, 0);
 871
 872         if (state & JZ_LCD_STATE_EOF_IRQ)
 873                 drm_crtc_handle_vblank(&priv->crtc);
 874
 875         return IRQ_HANDLED;
 876 }
 877
 878 static int ingenic_drm_enable_vblank(struct drm_crtc *crtc)
 879 {
 880         struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 881
 882         if (priv->no_vblank)
 883                 return -EINVAL;
 884
 885         regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
 886                            JZ_LCD_CTRL_EOF_IRQ, JZ_LCD_CTRL_EOF_IRQ);
 887
 888         return 0;
 889 }
 890
 891 static void ingenic_drm_disable_vblank(struct drm_crtc *crtc)
 892 {
 893         struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 894
 895         regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, JZ_LCD_CTRL_EOF_IRQ, 0);
 896 }
 897
 898 static struct drm_framebuffer *
 899 ingenic_drm_gem_fb_create(struct drm_device *drm, struct drm_file *file,
 900                           const struct drm_mode_fb_cmd2 *mode_cmd)
 901 {
 902         struct ingenic_drm *priv = drm_device_get_priv(drm);
 903
 904         if (priv->soc_info->map_noncoherent)
 905                 return drm_gem_fb_create_with_dirty(drm, file, mode_cmd);
 906
 907         return drm_gem_fb_create(drm, file, mode_cmd);
 908 }
 909
 910 static struct drm_gem_object *
 911 ingenic_drm_gem_create_object(struct drm_device *drm, size_t size)
 912 {
 913         struct ingenic_drm *priv = drm_device_get_priv(drm);
 914         struct drm_gem_cma_object *obj;
 915
 916         obj = kzalloc(sizeof(*obj), GFP_KERNEL);
 917         if (!obj)
 918                 return ERR_PTR(-ENOMEM);
 919
 920         obj->map_noncoherent = priv->soc_info->map_noncoherent;
 921
 922         return &obj->base;
 923 }
 924
 925 static struct drm_private_state *
 926 ingenic_drm_duplicate_state(struct drm_private_obj *obj)
 927 {
 928         struct ingenic_drm_private_state *state = to_ingenic_drm_priv_state(obj->state);
 929
 930         state = kmemdup(state, sizeof(*state), GFP_KERNEL);
 931         if (!state)
 932                 return NULL;
 933
 934         __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
 935
 936         return &state->base;
 937 }
 938
 939 static void ingenic_drm_destroy_state(struct drm_private_obj *obj,
 940                                       struct drm_private_state *state)
 941 {
 942         struct ingenic_drm_private_state *priv_state = to_ingenic_drm_priv_state(state);
 943
 944         kfree(priv_state);
 945 }
 946
 947 DEFINE_DRM_GEM_CMA_FOPS(ingenic_drm_fops);
 948
 949 static const struct drm_driver ingenic_drm_driver_data = {
 950         .driver_features        = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
 951         .name                   = "ingenic-drm",
 952         .desc                   = "DRM module for Ingenic SoCs",
 953         .date                   = "20200716",
 954         .major                  = 1,
 955         .minor                  = 1,
 956         .patchlevel             = 0,
 957
 958         .fops                   = &ingenic_drm_fops,
 959         .gem_create_object      = ingenic_drm_gem_create_object,
 960         DRM_GEM_CMA_DRIVER_OPS,
 961 };
 962
 963 static const struct drm_plane_funcs ingenic_drm_primary_plane_funcs = {
 964         .update_plane           = drm_atomic_helper_update_plane,
 965         .disable_plane          = drm_atomic_helper_disable_plane,
 966         .reset                  = drm_atomic_helper_plane_reset,
 967         .destroy                = drm_plane_cleanup,
 968
 969         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 970         .atomic_destroy_state   = drm_atomic_helper_plane_destroy_state,
 971 };
 972
 973 static const struct drm_crtc_funcs ingenic_drm_crtc_funcs = {
 974         .set_config             = drm_atomic_helper_set_config,
 975         .page_flip              = drm_atomic_helper_page_flip,
 976         .reset                  = drm_atomic_helper_crtc_reset,
 977         .destroy                = drm_crtc_cleanup,
 978
 979         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 980         .atomic_destroy_state   = drm_atomic_helper_crtc_destroy_state,
 981
 982         .enable_vblank          = ingenic_drm_enable_vblank,
 983         .disable_vblank         = ingenic_drm_disable_vblank,
 984 };
 985
 986 static const struct drm_plane_helper_funcs ingenic_drm_plane_helper_funcs = {
 987         .atomic_update          = ingenic_drm_plane_atomic_update,
 988         .atomic_check           = ingenic_drm_plane_atomic_check,
 989         .atomic_disable         = ingenic_drm_plane_atomic_disable,
 990 };
 991
 992 static const struct drm_crtc_helper_funcs ingenic_drm_crtc_helper_funcs = {
 993         .atomic_enable          = ingenic_drm_crtc_atomic_enable,
 994         .atomic_disable         = ingenic_drm_crtc_atomic_disable,
 995         .atomic_begin           = ingenic_drm_crtc_atomic_begin,
 996         .atomic_flush           = ingenic_drm_crtc_atomic_flush,
 997         .atomic_check           = ingenic_drm_crtc_atomic_check,
 998         .mode_valid             = ingenic_drm_crtc_mode_valid,
 999 };
1000
1001 static const struct drm_encoder_helper_funcs ingenic_drm_encoder_helper_funcs = {
1002         .atomic_mode_set        = ingenic_drm_encoder_atomic_mode_set,
1003 };
1004
1005 static const struct drm_bridge_funcs ingenic_drm_bridge_funcs = {
1006         .attach                 = ingenic_drm_bridge_attach,
1007         .atomic_enable          = ingenic_drm_bridge_atomic_enable,
1008         .atomic_disable         = ingenic_drm_bridge_atomic_disable,
1009         .atomic_check           = ingenic_drm_bridge_atomic_check,
1010         .atomic_reset           = drm_atomic_helper_bridge_reset,
1011         .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1012         .atomic_destroy_state   = drm_atomic_helper_bridge_destroy_state,
1013         .atomic_get_input_bus_fmts = ingenic_drm_bridge_atomic_get_input_bus_fmts,
1014 };
1015
1016 static const struct drm_mode_config_funcs ingenic_drm_mode_config_funcs = {
1017         .fb_create              = ingenic_drm_gem_fb_create,
1018         .output_poll_changed    = drm_fb_helper_output_poll_changed,
1019         .atomic_check           = drm_atomic_helper_check,
1020         .atomic_commit          = drm_atomic_helper_commit,
1021 };
1022
1023 static struct drm_mode_config_helper_funcs ingenic_drm_mode_config_helpers = {
1024         .atomic_commit_tail = drm_atomic_helper_commit_tail,
1025 };
1026
1027 static const struct drm_private_state_funcs ingenic_drm_private_state_funcs = {
1028         .atomic_duplicate_state = ingenic_drm_duplicate_state,
1029         .atomic_destroy_state = ingenic_drm_destroy_state,
1030 };
1031
1032 static void ingenic_drm_unbind_all(void *d)
1033 {
1034         struct ingenic_drm *priv = d;
1035
1036         component_unbind_all(priv->dev, &priv->drm);
1037 }
1038
1039 static void __maybe_unused ingenic_drm_release_rmem(void *d)
1040 {
1041         of_reserved_mem_device_release(d);
1042 }
1043
1044 static void ingenic_drm_configure_hwdesc(struct ingenic_drm *priv,
1045                                          unsigned int hwdesc,
1046                                          unsigned int next_hwdesc, u32 id)
1047 {
1048         struct ingenic_dma_hwdesc *desc = &priv->dma_hwdescs->hwdesc[hwdesc];
1049
1050         desc->next = dma_hwdesc_addr(priv, next_hwdesc);
1051         desc->id = id;
1052 }
1053
1054 static void ingenic_drm_configure_hwdesc_palette(struct ingenic_drm *priv)
1055 {
1056         struct ingenic_dma_hwdesc *desc;
1057
1058         ingenic_drm_configure_hwdesc(priv, HWDESC_PALETTE, 0, 0xc0);
1059
1060         desc = &priv->dma_hwdescs->hwdesc[HWDESC_PALETTE];
1061         desc->addr = priv->dma_hwdescs_phys
1062                 + offsetof(struct ingenic_dma_hwdescs, palette);
1063         desc->cmd = JZ_LCD_CMD_ENABLE_PAL
1064                 | (sizeof(priv->dma_hwdescs->palette) / 4);
1065 }
1066
1067 static void ingenic_drm_configure_hwdesc_plane(struct ingenic_drm *priv,
1068                                                unsigned int plane)
1069 {
1070         ingenic_drm_configure_hwdesc(priv, plane, plane, 0xf0 | plane);
1071 }
1072
1073 static void ingenic_drm_atomic_private_obj_fini(struct drm_device *drm, void *private_obj)
1074 {
1075         drm_atomic_private_obj_fini(private_obj);
1076 }
1077
1078 static int ingenic_drm_bind(struct device *dev, bool has_components)
1079 {
1080         struct platform_device *pdev = to_platform_device(dev);
1081         struct ingenic_drm_private_state *private_state;
1082         const struct jz_soc_info *soc_info;
1083         struct ingenic_drm *priv;
1084         struct clk *parent_clk;
1085         struct drm_plane *primary;
1086         struct drm_bridge *bridge;
1087         struct drm_panel *panel;
1088         struct drm_connector *connector;
1089         struct drm_encoder *encoder;
1090         struct ingenic_drm_bridge *ib;
1091         struct drm_device *drm;
1092         void __iomem *base;
1093         struct resource *res;
1094         struct regmap_config regmap_config;
1095         long parent_rate;
1096         unsigned int i, clone_mask = 0;
1097         int ret, irq;
1098         u32 osdc = 0;
1099
1100         soc_info = of_device_get_match_data(dev);
1101         if (!soc_info) {
1102                 dev_err(dev, "Missing platform data\n");
1103                 return -EINVAL;
1104         }
1105
1106         if (IS_ENABLED(CONFIG_OF_RESERVED_MEM)) {
1107                 ret = of_reserved_mem_device_init(dev);
1108
1109                 if (ret && ret != -ENODEV)
1110                         dev_warn(dev, "Failed to get reserved memory: %d\n", ret);
1111
1112                 if (!ret) {
1113                         ret = devm_add_action_or_reset(dev, ingenic_drm_release_rmem, dev);
1114                         if (ret)
1115                                 return ret;
1116                 }
1117         }
1118
1119         priv = devm_drm_dev_alloc(dev, &ingenic_drm_driver_data,
1120                                   struct ingenic_drm, drm);
1121         if (IS_ERR(priv))
1122                 return PTR_ERR(priv);
1123
1124         priv->soc_info = soc_info;
1125         priv->dev = dev;
1126         drm = &priv->drm;
1127
1128         platform_set_drvdata(pdev, priv);
1129
1130         ret = drmm_mode_config_init(drm);
1131         if (ret)
1132                 return ret;
1133
1134         drm->mode_config.min_width = 0;
1135         drm->mode_config.min_height = 0;
1136         drm->mode_config.max_width = soc_info->max_width;
1137         drm->mode_config.max_height = 4095;
1138         drm->mode_config.funcs = &ingenic_drm_mode_config_funcs;
1139         drm->mode_config.helper_private = &ingenic_drm_mode_config_helpers;
1140
1141         base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1142         if (IS_ERR(base)) {
1143                 dev_err(dev, "Failed to get memory resource\n");
1144                 return PTR_ERR(base);
1145         }
1146
1147         regmap_config = ingenic_drm_regmap_config;
1148         regmap_config.max_register = res->end - res->start;
1149         priv->map = devm_regmap_init_mmio(dev, base,
1150                                           &regmap_config);
1151         if (IS_ERR(priv->map)) {
1152                 dev_err(dev, "Failed to create regmap\n");
1153                 return PTR_ERR(priv->map);
1154         }
1155
1156         irq = platform_get_irq(pdev, 0);
1157         if (irq < 0)
1158                 return irq;
1159
1160         if (soc_info->needs_dev_clk) {
1161                 priv->lcd_clk = devm_clk_get(dev, "lcd");
1162                 if (IS_ERR(priv->lcd_clk)) {
1163                         dev_err(dev, "Failed to get lcd clock\n");
1164                         return PTR_ERR(priv->lcd_clk);
1165                 }
1166         }
1167
1168         priv->pix_clk = devm_clk_get(dev, "lcd_pclk");
1169         if (IS_ERR(priv->pix_clk)) {
1170                 dev_err(dev, "Failed to get pixel clock\n");
1171                 return PTR_ERR(priv->pix_clk);
1172         }
1173
1174         priv->dma_hwdescs = dmam_alloc_coherent(dev,
1175                                                 sizeof(*priv->dma_hwdescs),
1176                                                 &priv->dma_hwdescs_phys,
1177                                                 GFP_KERNEL);
1178         if (!priv->dma_hwdescs)
1179                 return -ENOMEM;
1180
1181         /* Configure DMA hwdesc for foreground0 plane */
1182         ingenic_drm_configure_hwdesc_plane(priv, 0);
1183
1184         /* Configure DMA hwdesc for foreground1 plane */
1185         ingenic_drm_configure_hwdesc_plane(priv, 1);
1186
1187         /* Configure DMA hwdesc for palette */
1188         ingenic_drm_configure_hwdesc_palette(priv);
1189
1190         primary = priv->soc_info->has_osd ? &priv->f1 : &priv->f0;
1191
1192         drm_plane_helper_add(primary, &ingenic_drm_plane_helper_funcs);
1193
1194         ret = drm_universal_plane_init(drm, primary, 1,
1195                                        &ingenic_drm_primary_plane_funcs,
1196                                        priv->soc_info->formats_f1,
1197                                        priv->soc_info->num_formats_f1,
1198                                        NULL, DRM_PLANE_TYPE_PRIMARY, NULL);
1199         if (ret) {
1200                 dev_err(dev, "Failed to register plane: %i\n", ret);
1201                 return ret;
1202         }
1203
1204         if (soc_info->map_noncoherent)
1205                 drm_plane_enable_fb_damage_clips(&priv->f1);
1206
1207         drm_crtc_helper_add(&priv->crtc, &ingenic_drm_crtc_helper_funcs);
1208
1209         ret = drm_crtc_init_with_planes(drm, &priv->crtc, primary,
1210                                         NULL, &ingenic_drm_crtc_funcs, NULL);
1211         if (ret) {
1212                 dev_err(dev, "Failed to init CRTC: %i\n", ret);
1213                 return ret;
1214         }
1215
1216         drm_crtc_enable_color_mgmt(&priv->crtc, 0, false,
1217                                    ARRAY_SIZE(priv->dma_hwdescs->palette));
1218
1219         if (soc_info->has_osd) {
1220                 drm_plane_helper_add(&priv->f0,
1221                                      &ingenic_drm_plane_helper_funcs);
1222
1223                 ret = drm_universal_plane_init(drm, &priv->f0, 1,
1224                                                &ingenic_drm_primary_plane_funcs,
1225                                                priv->soc_info->formats_f0,
1226                                                priv->soc_info->num_formats_f0,
1227                                                NULL, DRM_PLANE_TYPE_OVERLAY,
1228                                                NULL);
1229                 if (ret) {
1230                         dev_err(dev, "Failed to register overlay plane: %i\n",
1231                                 ret);
1232                         return ret;
1233                 }
1234
1235                 if (soc_info->map_noncoherent)
1236                         drm_plane_enable_fb_damage_clips(&priv->f0);
1237
1238                 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && has_components) {
1239                         ret = component_bind_all(dev, drm);
1240                         if (ret) {
1241                                 if (ret != -EPROBE_DEFER)
1242                                         dev_err(dev, "Failed to bind components: %i\n", ret);
1243                                 return ret;
1244                         }
1245
1246                         ret = devm_add_action_or_reset(dev, ingenic_drm_unbind_all, priv);
1247                         if (ret)
1248                                 return ret;
1249
1250                         priv->ipu_plane = drm_plane_from_index(drm, 2);
1251                         if (!priv->ipu_plane) {
1252                                 dev_err(dev, "Failed to retrieve IPU plane\n");
1253                                 return -EINVAL;
1254                         }
1255                 }
1256         }
1257
1258         for (i = 0; ; i++) {
1259                 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, i, &panel, &bridge);
1260                 if (ret) {
1261                         if (ret == -ENODEV)
1262                                 break; /* we're done */
1263                         if (ret != -EPROBE_DEFER)
1264                                 dev_err(dev, "Failed to get bridge handle\n");
1265                         return ret;
1266                 }
1267
1268                 if (panel)
1269                         bridge = devm_drm_panel_bridge_add_typed(dev, panel,
1270                                                                  DRM_MODE_CONNECTOR_DPI);
1271
1272                 ib = drmm_encoder_alloc(drm, struct ingenic_drm_bridge, encoder,
1273                                         NULL, DRM_MODE_ENCODER_DPI, NULL);
1274                 if (IS_ERR(ib)) {
1275                         ret = PTR_ERR(ib);
1276                         dev_err(dev, "Failed to init encoder: %d\n", ret);
1277                         return ret;
1278                 }
1279
1280                 encoder = &ib->encoder;
1281                 encoder->possible_crtcs = drm_crtc_mask(&priv->crtc);
1282
1283                 drm_encoder_helper_add(encoder, &ingenic_drm_encoder_helper_funcs);
1284
1285                 ib->bridge.funcs = &ingenic_drm_bridge_funcs;
1286                 ib->next_bridge = bridge;
1287
1288                 ret = drm_bridge_attach(encoder, &ib->bridge, NULL,
1289                                         DRM_BRIDGE_ATTACH_NO_CONNECTOR);
1290                 if (ret) {
1291                         dev_err(dev, "Unable to attach bridge\n");
1292                         return ret;
1293                 }
1294
1295                 connector = drm_bridge_connector_init(drm, encoder);
1296                 if (IS_ERR(connector)) {
1297                         dev_err(dev, "Unable to init connector\n");
1298                         return PTR_ERR(connector);
1299                 }
1300
1301                 drm_connector_attach_encoder(connector, encoder);
1302         }
1303
1304         drm_for_each_encoder(encoder, drm) {
1305                 clone_mask |= BIT(drm_encoder_index(encoder));
1306         }
1307
1308         drm_for_each_encoder(encoder, drm) {
1309                 encoder->possible_clones = clone_mask;
1310         }
1311
1312         ret = devm_request_irq(dev, irq, ingenic_drm_irq_handler, 0, drm->driver->name, drm);
1313         if (ret) {
1314                 dev_err(dev, "Unable to install IRQ handler\n");
1315                 return ret;
1316         }
1317
1318         ret = drm_vblank_init(drm, 1);
1319         if (ret) {
1320                 dev_err(dev, "Failed calling drm_vblank_init()\n");
1321                 return ret;
1322         }
1323
1324         drm_mode_config_reset(drm);
1325
1326         ret = clk_prepare_enable(priv->pix_clk);
1327         if (ret) {
1328                 dev_err(dev, "Unable to start pixel clock\n");
1329                 return ret;
1330         }
1331
1332         if (priv->lcd_clk) {
1333                 parent_clk = clk_get_parent(priv->lcd_clk);
1334                 parent_rate = clk_get_rate(parent_clk);
1335
1336                 /* LCD Device clock must be 3x the pixel clock for STN panels,
1337                  * or 1.5x the pixel clock for TFT panels. To avoid having to
1338                  * check for the LCD device clock everytime we do a mode change,
1339                  * we set the LCD device clock to the highest rate possible.
1340                  */
1341                 ret = clk_set_rate(priv->lcd_clk, parent_rate);
1342                 if (ret) {
1343                         dev_err(dev, "Unable to set LCD clock rate\n");
1344                         goto err_pixclk_disable;
1345                 }
1346
1347                 ret = clk_prepare_enable(priv->lcd_clk);
1348                 if (ret) {
1349                         dev_err(dev, "Unable to start lcd clock\n");
1350                         goto err_pixclk_disable;
1351                 }
1352         }
1353
1354         /* Enable OSD if available */
1355         if (soc_info->has_osd)
1356                 osdc |= JZ_LCD_OSDC_OSDEN;
1357         if (soc_info->has_alpha)
1358                 osdc |= JZ_LCD_OSDC_ALPHAEN;
1359         regmap_write(priv->map, JZ_REG_LCD_OSDC, osdc);
1360
1361         mutex_init(&priv->clk_mutex);
1362         priv->clock_nb.notifier_call = ingenic_drm_update_pixclk;
1363
1364         parent_clk = clk_get_parent(priv->pix_clk);
1365         ret = clk_notifier_register(parent_clk, &priv->clock_nb);
1366         if (ret) {
1367                 dev_err(dev, "Unable to register clock notifier\n");
1368                 goto err_devclk_disable;
1369         }
1370
1371         private_state = kzalloc(sizeof(*private_state), GFP_KERNEL);
1372         if (!private_state) {
1373                 ret = -ENOMEM;
1374                 goto err_clk_notifier_unregister;
1375         }
1376
1377         drm_atomic_private_obj_init(drm, &priv->private_obj, &private_state->base,
1378                                     &ingenic_drm_private_state_funcs);
1379
1380         ret = drmm_add_action_or_reset(drm, ingenic_drm_atomic_private_obj_fini,
1381                                        &priv->private_obj);
1382         if (ret)
1383                 goto err_private_state_free;
1384
1385         ret = drm_dev_register(drm, 0);
1386         if (ret) {
1387                 dev_err(dev, "Failed to register DRM driver\n");
1388                 goto err_clk_notifier_unregister;
1389         }
1390
1391         drm_fbdev_generic_setup(drm, 32);
1392
1393         return 0;
1394
1395 err_private_state_free:
1396         kfree(private_state);
1397 err_clk_notifier_unregister:
1398         clk_notifier_unregister(parent_clk, &priv->clock_nb);
1399 err_devclk_disable:
1400         if (priv->lcd_clk)
1401                 clk_disable_unprepare(priv->lcd_clk);
1402 err_pixclk_disable:
1403         clk_disable_unprepare(priv->pix_clk);
1404         return ret;
1405 }
1406
1407 static int ingenic_drm_bind_with_components(struct device *dev)
1408 {
1409         return ingenic_drm_bind(dev, true);
1410 }
1411
1412 static void ingenic_drm_unbind(struct device *dev)
1413 {
1414         struct ingenic_drm *priv = dev_get_drvdata(dev);
1415         struct clk *parent_clk = clk_get_parent(priv->pix_clk);
1416
1417         clk_notifier_unregister(parent_clk, &priv->clock_nb);
1418         if (priv->lcd_clk)
1419                 clk_disable_unprepare(priv->lcd_clk);
1420         clk_disable_unprepare(priv->pix_clk);
1421
1422         drm_dev_unregister(&priv->drm);
1423         drm_atomic_helper_shutdown(&priv->drm);
1424 }
1425
1426 static const struct component_master_ops ingenic_master_ops = {
1427         .bind = ingenic_drm_bind_with_components,
1428         .unbind = ingenic_drm_unbind,
1429 };
1430
1431 static int ingenic_drm_probe(struct platform_device *pdev)
1432 {
1433         struct device *dev = &pdev->dev;
1434         struct component_match *match = NULL;
1435         struct device_node *np;
1436
1437         if (!IS_ENABLED(CONFIG_DRM_INGENIC_IPU))
1438                 return ingenic_drm_bind(dev, false);
1439
1440         /* IPU is at port address 8 */
1441         np = of_graph_get_remote_node(dev->of_node, 8, 0);
1442         if (!np)
1443                 return ingenic_drm_bind(dev, false);
1444
1445         drm_of_component_match_add(dev, &match, component_compare_of, np);
1446         of_node_put(np);
1447
1448         return component_master_add_with_match(dev, &ingenic_master_ops, match);
1449 }
1450
1451 static int ingenic_drm_remove(struct platform_device *pdev)
1452 {
1453         struct device *dev = &pdev->dev;
1454
1455         if (!IS_ENABLED(CONFIG_DRM_INGENIC_IPU))
1456                 ingenic_drm_unbind(dev);
1457         else
1458                 component_master_del(dev, &ingenic_master_ops);
1459
1460         return 0;
1461 }
1462
1463 static int __maybe_unused ingenic_drm_suspend(struct device *dev)
1464 {
1465         struct ingenic_drm *priv = dev_get_drvdata(dev);
1466
1467         return drm_mode_config_helper_suspend(&priv->drm);
1468 }
1469
1470 static int __maybe_unused ingenic_drm_resume(struct device *dev)
1471 {
1472         struct ingenic_drm *priv = dev_get_drvdata(dev);
1473
1474         return drm_mode_config_helper_resume(&priv->drm);
1475 }
1476
1477 static SIMPLE_DEV_PM_OPS(ingenic_drm_pm_ops, ingenic_drm_suspend, ingenic_drm_resume);
1478
1479 static const u32 jz4740_formats[] = {
1480         DRM_FORMAT_XRGB1555,
1481         DRM_FORMAT_RGB565,
1482         DRM_FORMAT_XRGB8888,
1483 };
1484
1485 static const u32 jz4725b_formats_f1[] = {
1486         DRM_FORMAT_XRGB1555,
1487         DRM_FORMAT_RGB565,
1488         DRM_FORMAT_XRGB8888,
1489 };
1490
1491 static const u32 jz4725b_formats_f0[] = {
1492         DRM_FORMAT_C8,
1493         DRM_FORMAT_XRGB1555,
1494         DRM_FORMAT_RGB565,
1495         DRM_FORMAT_XRGB8888,
1496 };
1497
1498 static const u32 jz4770_formats_f1[] = {
1499         DRM_FORMAT_XRGB1555,
1500         DRM_FORMAT_RGB565,
1501         DRM_FORMAT_RGB888,
1502         DRM_FORMAT_XRGB8888,
1503         DRM_FORMAT_XRGB2101010,
1504 };
1505
1506 static const u32 jz4770_formats_f0[] = {
1507         DRM_FORMAT_C8,
1508         DRM_FORMAT_XRGB1555,
1509         DRM_FORMAT_RGB565,
1510         DRM_FORMAT_RGB888,
1511         DRM_FORMAT_XRGB8888,
1512         DRM_FORMAT_XRGB2101010,
1513 };
1514
1515 static const struct jz_soc_info jz4740_soc_info = {
1516         .needs_dev_clk = true,
1517         .has_osd = false,
1518         .map_noncoherent = false,
1519         .max_width = 800,
1520         .max_height = 600,
1521         .formats_f1 = jz4740_formats,
1522         .num_formats_f1 = ARRAY_SIZE(jz4740_formats),
1523         /* JZ4740 has only one plane */
1524 };
1525
1526 static const struct jz_soc_info jz4725b_soc_info = {
1527         .needs_dev_clk = false,
1528         .has_osd = true,
1529         .map_noncoherent = false,
1530         .max_width = 800,
1531         .max_height = 600,
1532         .formats_f1 = jz4725b_formats_f1,
1533         .num_formats_f1 = ARRAY_SIZE(jz4725b_formats_f1),
1534         .formats_f0 = jz4725b_formats_f0,
1535         .num_formats_f0 = ARRAY_SIZE(jz4725b_formats_f0),
1536 };
1537
1538 static const struct jz_soc_info jz4770_soc_info = {
1539         .needs_dev_clk = false,
1540         .has_osd = true,
1541         .map_noncoherent = true,
1542         .max_width = 1280,
1543         .max_height = 720,
1544         .formats_f1 = jz4770_formats_f1,
1545         .num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1),
1546         .formats_f0 = jz4770_formats_f0,
1547         .num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0),
1548 };
1549
1550 static const struct jz_soc_info jz4780_soc_info = {
1551         .needs_dev_clk = true,
1552         .has_osd = true,
1553         .has_alpha = true,
1554         .use_extended_hwdesc = true,
1555         .plane_f0_not_working = true,   /* REVISIT */
1556         .max_width = 4096,
1557         .max_height = 2048,
1558         .formats_f1 = jz4770_formats_f1,
1559         .num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1),
1560         .formats_f0 = jz4770_formats_f0,
1561         .num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0),
1562 };
1563
1564 static const struct of_device_id ingenic_drm_of_match[] = {
1565         { .compatible = "ingenic,jz4740-lcd", .data = &jz4740_soc_info },
1566         { .compatible = "ingenic,jz4725b-lcd", .data = &jz4725b_soc_info },
1567         { .compatible = "ingenic,jz4770-lcd", .data = &jz4770_soc_info },
1568         { .compatible = "ingenic,jz4780-lcd", .data = &jz4780_soc_info },
1569         { /* sentinel */ },
1570 };
1571 MODULE_DEVICE_TABLE(of, ingenic_drm_of_match);
1572
1573 static struct platform_driver ingenic_drm_driver = {
1574         .driver = {
1575                 .name = "ingenic-drm",
1576                 .pm = pm_ptr(&ingenic_drm_pm_ops),
1577                 .of_match_table = of_match_ptr(ingenic_drm_of_match),
1578         },
1579         .probe = ingenic_drm_probe,
1580         .remove = ingenic_drm_remove,
1581 };
1582
1583 static int ingenic_drm_init(void)
1584 {
1585         int err;
1586
1587         if (drm_firmware_drivers_only())
1588                 return -ENODEV;
1589
1590         if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) {
1591                 err = platform_driver_register(ingenic_ipu_driver_ptr);
1592                 if (err)
1593                         return err;
1594         }
1595
1596         return platform_driver_register(&ingenic_drm_driver);
1597 }
1598 module_init(ingenic_drm_init);
1599
1600 static void ingenic_drm_exit(void)
1601 {
1602         platform_driver_unregister(&ingenic_drm_driver);
1603
1604         if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU))
1605                 platform_driver_unregister(ingenic_ipu_driver_ptr);
1606 }
1607 module_exit(ingenic_drm_exit);
1608
1609 MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
1610 MODULE_DESCRIPTION("DRM driver for the Ingenic SoCs\n");
1611 MODULE_LICENSE("GPL v2");