1 // SPDX-License-Identifier: GPL-2.0
3 // Ingenic JZ47xx KMS driver
5 // Copyright (C) 2019, Paul Cercueil <paul@crapouillou.net>
7 #include "ingenic-drm.h"
9 #include <linux/bitfield.h>
10 #include <linux/component.h>
11 #include <linux/clk.h>
12 #include <linux/dma-mapping.h>
14 #include <linux/module.h>
15 #include <linux/mutex.h>
16 #include <linux/of_device.h>
17 #include <linux/of_reserved_mem.h>
18 #include <linux/platform_device.h>
20 #include <linux/regmap.h>
22 #include <drm/drm_atomic.h>
23 #include <drm/drm_atomic_helper.h>
24 #include <drm/drm_bridge.h>
25 #include <drm/drm_bridge_connector.h>
26 #include <drm/drm_color_mgmt.h>
27 #include <drm/drm_crtc.h>
28 #include <drm/drm_crtc_helper.h>
29 #include <drm/drm_damage_helper.h>
30 #include <drm/drm_drv.h>
31 #include <drm/drm_encoder.h>
32 #include <drm/drm_gem_cma_helper.h>
33 #include <drm/drm_fb_cma_helper.h>
34 #include <drm/drm_fb_helper.h>
35 #include <drm/drm_fourcc.h>
36 #include <drm/drm_gem_atomic_helper.h>
37 #include <drm/drm_gem_framebuffer_helper.h>
38 #include <drm/drm_managed.h>
39 #include <drm/drm_of.h>
40 #include <drm/drm_panel.h>
41 #include <drm/drm_plane.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_probe_helper.h>
44 #include <drm/drm_vblank.h>
46 #define HWDESC_PALETTE 2
48 struct ingenic_dma_hwdesc {
53 /* extended hw descriptor for jz4780 */
60 struct ingenic_dma_hwdescs {
61 struct ingenic_dma_hwdesc hwdesc[3];
62 u16 palette[256] __aligned(16);
70 bool use_extended_hwdesc;
71 bool plane_f0_not_working;
72 unsigned int max_width, max_height;
73 const u32 *formats_f0, *formats_f1;
74 unsigned int num_formats_f0, num_formats_f1;
77 struct ingenic_drm_private_state {
78 struct drm_private_state base;
83 struct drm_device drm;
85 * f1 (aka. foreground1) is our primary plane, on top of which
86 * f0 (aka. foreground0) can be overlayed. Z-order is fixed in
87 * hardware and cannot be changed.
89 struct drm_plane f0, f1, *ipu_plane;
94 struct clk *lcd_clk, *pix_clk;
95 const struct jz_soc_info *soc_info;
97 struct ingenic_dma_hwdescs *dma_hwdescs;
98 dma_addr_t dma_hwdescs_phys;
104 * clk_mutex is used to synchronize the pixel clock rate update with
105 * the VBLANK. When the pixel clock's parent clock needs to be updated,
106 * clock_nb's notifier function will lock the mutex, then wait until the
107 * next VBLANK. At that point, the parent clock's rate can be updated,
108 * and the mutex is then unlocked. If an atomic commit happens in the
109 * meantime, it will lock on the mutex, effectively waiting until the
110 * clock update process finishes. Finally, the pixel clock's rate will
111 * be recomputed when the mutex has been released, in the pending atomic
112 * commit, or a future one.
114 struct mutex clk_mutex;
115 bool update_clk_rate;
116 struct notifier_block clock_nb;
118 struct drm_private_obj private_obj;
121 struct ingenic_drm_bridge {
122 struct drm_encoder encoder;
123 struct drm_bridge bridge, *next_bridge;
125 struct drm_bus_cfg bus_cfg;
128 static inline struct ingenic_drm_bridge *
129 to_ingenic_drm_bridge(struct drm_encoder *encoder)
131 return container_of(encoder, struct ingenic_drm_bridge, encoder);
134 static inline struct ingenic_drm_private_state *
135 to_ingenic_drm_priv_state(struct drm_private_state *state)
137 return container_of(state, struct ingenic_drm_private_state, base);
140 static struct ingenic_drm_private_state *
141 ingenic_drm_get_priv_state(struct ingenic_drm *priv, struct drm_atomic_state *state)
143 struct drm_private_state *priv_state;
145 priv_state = drm_atomic_get_private_obj_state(state, &priv->private_obj);
146 if (IS_ERR(priv_state))
147 return ERR_CAST(priv_state);
149 return to_ingenic_drm_priv_state(priv_state);
152 static struct ingenic_drm_private_state *
153 ingenic_drm_get_new_priv_state(struct ingenic_drm *priv, struct drm_atomic_state *state)
155 struct drm_private_state *priv_state;
157 priv_state = drm_atomic_get_new_private_obj_state(state, &priv->private_obj);
161 return to_ingenic_drm_priv_state(priv_state);
164 static bool ingenic_drm_writeable_reg(struct device *dev, unsigned int reg)
169 case JZ_REG_LCD_FID0:
170 case JZ_REG_LCD_CMD0:
172 case JZ_REG_LCD_FID1:
173 case JZ_REG_LCD_CMD1:
180 static const struct regmap_config ingenic_drm_regmap_config = {
185 .writeable_reg = ingenic_drm_writeable_reg,
188 static inline struct ingenic_drm *drm_device_get_priv(struct drm_device *drm)
190 return container_of(drm, struct ingenic_drm, drm);
193 static inline struct ingenic_drm *drm_crtc_get_priv(struct drm_crtc *crtc)
195 return container_of(crtc, struct ingenic_drm, crtc);
198 static inline struct ingenic_drm *drm_nb_get_priv(struct notifier_block *nb)
200 return container_of(nb, struct ingenic_drm, clock_nb);
203 static inline dma_addr_t dma_hwdesc_addr(const struct ingenic_drm *priv,
206 u32 offset = offsetof(struct ingenic_dma_hwdescs, hwdesc[idx]);
208 return priv->dma_hwdescs_phys + offset;
211 static int ingenic_drm_update_pixclk(struct notifier_block *nb,
212 unsigned long action,
215 struct ingenic_drm *priv = drm_nb_get_priv(nb);
218 case PRE_RATE_CHANGE:
219 mutex_lock(&priv->clk_mutex);
220 priv->update_clk_rate = true;
221 drm_crtc_wait_one_vblank(&priv->crtc);
224 mutex_unlock(&priv->clk_mutex);
229 static void ingenic_drm_bridge_atomic_enable(struct drm_bridge *bridge,
230 struct drm_bridge_state *old_bridge_state)
232 struct ingenic_drm *priv = drm_device_get_priv(bridge->dev);
234 regmap_write(priv->map, JZ_REG_LCD_STATE, 0);
236 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
237 JZ_LCD_CTRL_ENABLE | JZ_LCD_CTRL_DISABLE,
241 static void ingenic_drm_crtc_atomic_enable(struct drm_crtc *crtc,
242 struct drm_atomic_state *state)
244 struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
245 struct ingenic_drm_private_state *priv_state;
246 unsigned int next_id;
248 priv_state = ingenic_drm_get_priv_state(priv, state);
249 if (WARN_ON(IS_ERR(priv_state)))
252 /* Set addresses of our DMA descriptor chains */
253 next_id = priv_state->use_palette ? HWDESC_PALETTE : 0;
254 regmap_write(priv->map, JZ_REG_LCD_DA0, dma_hwdesc_addr(priv, next_id));
255 regmap_write(priv->map, JZ_REG_LCD_DA1, dma_hwdesc_addr(priv, 1));
257 drm_crtc_vblank_on(crtc);
260 static void ingenic_drm_bridge_atomic_disable(struct drm_bridge *bridge,
261 struct drm_bridge_state *old_bridge_state)
263 struct ingenic_drm *priv = drm_device_get_priv(bridge->dev);
266 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
267 JZ_LCD_CTRL_DISABLE, JZ_LCD_CTRL_DISABLE);
269 regmap_read_poll_timeout(priv->map, JZ_REG_LCD_STATE, var,
270 var & JZ_LCD_STATE_DISABLED,
274 static void ingenic_drm_crtc_atomic_disable(struct drm_crtc *crtc,
275 struct drm_atomic_state *state)
277 drm_crtc_vblank_off(crtc);
280 static void ingenic_drm_crtc_update_timings(struct ingenic_drm *priv,
281 struct drm_display_mode *mode)
283 unsigned int vpe, vds, vde, vt, hpe, hds, hde, ht;
285 vpe = mode->crtc_vsync_end - mode->crtc_vsync_start;
286 vds = mode->crtc_vtotal - mode->crtc_vsync_start;
287 vde = vds + mode->crtc_vdisplay;
288 vt = vde + mode->crtc_vsync_start - mode->crtc_vdisplay;
290 hpe = mode->crtc_hsync_end - mode->crtc_hsync_start;
291 hds = mode->crtc_htotal - mode->crtc_hsync_start;
292 hde = hds + mode->crtc_hdisplay;
293 ht = hde + mode->crtc_hsync_start - mode->crtc_hdisplay;
295 regmap_write(priv->map, JZ_REG_LCD_VSYNC,
296 0 << JZ_LCD_VSYNC_VPS_OFFSET |
297 vpe << JZ_LCD_VSYNC_VPE_OFFSET);
299 regmap_write(priv->map, JZ_REG_LCD_HSYNC,
300 0 << JZ_LCD_HSYNC_HPS_OFFSET |
301 hpe << JZ_LCD_HSYNC_HPE_OFFSET);
303 regmap_write(priv->map, JZ_REG_LCD_VAT,
304 ht << JZ_LCD_VAT_HT_OFFSET |
305 vt << JZ_LCD_VAT_VT_OFFSET);
307 regmap_write(priv->map, JZ_REG_LCD_DAH,
308 hds << JZ_LCD_DAH_HDS_OFFSET |
309 hde << JZ_LCD_DAH_HDE_OFFSET);
310 regmap_write(priv->map, JZ_REG_LCD_DAV,
311 vds << JZ_LCD_DAV_VDS_OFFSET |
312 vde << JZ_LCD_DAV_VDE_OFFSET);
314 if (priv->panel_is_sharp) {
315 regmap_write(priv->map, JZ_REG_LCD_PS, hde << 16 | (hde + 1));
316 regmap_write(priv->map, JZ_REG_LCD_CLS, hde << 16 | (hde + 1));
317 regmap_write(priv->map, JZ_REG_LCD_SPL, hpe << 16 | (hpe + 1));
318 regmap_write(priv->map, JZ_REG_LCD_REV, mode->htotal << 16);
321 regmap_set_bits(priv->map, JZ_REG_LCD_CTRL,
322 JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16);
325 * IPU restart - specify how much time the LCDC will wait before
326 * transferring a new frame from the IPU. The value is the one
327 * suggested in the programming manual.
329 regmap_write(priv->map, JZ_REG_LCD_IPUR, JZ_LCD_IPUR_IPUREN |
330 (ht * vpe / 3) << JZ_LCD_IPUR_IPUR_LSB);
333 static int ingenic_drm_crtc_atomic_check(struct drm_crtc *crtc,
334 struct drm_atomic_state *state)
336 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
338 struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
339 struct drm_plane_state *f1_state, *f0_state, *ipu_state = NULL;
341 if (crtc_state->gamma_lut &&
342 drm_color_lut_size(crtc_state->gamma_lut) != ARRAY_SIZE(priv->dma_hwdescs->palette)) {
343 dev_dbg(priv->dev, "Invalid palette size\n");
347 if (drm_atomic_crtc_needs_modeset(crtc_state) && priv->soc_info->has_osd) {
348 f1_state = drm_atomic_get_plane_state(crtc_state->state,
350 if (IS_ERR(f1_state))
351 return PTR_ERR(f1_state);
353 f0_state = drm_atomic_get_plane_state(crtc_state->state,
355 if (IS_ERR(f0_state))
356 return PTR_ERR(f0_state);
358 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && priv->ipu_plane) {
359 ipu_state = drm_atomic_get_plane_state(crtc_state->state,
361 if (IS_ERR(ipu_state))
362 return PTR_ERR(ipu_state);
364 /* IPU and F1 planes cannot be enabled at the same time. */
365 if (f1_state->fb && ipu_state->fb) {
366 dev_dbg(priv->dev, "Cannot enable both F1 and IPU\n");
371 /* If all the planes are disabled, we won't get a VBLANK IRQ */
372 priv->no_vblank = !f1_state->fb && !f0_state->fb &&
373 !(ipu_state && ipu_state->fb);
379 static enum drm_mode_status
380 ingenic_drm_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode)
382 struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
385 if (mode->hdisplay > priv->soc_info->max_width)
386 return MODE_BAD_HVALUE;
387 if (mode->vdisplay > priv->soc_info->max_height)
388 return MODE_BAD_VVALUE;
390 rate = clk_round_rate(priv->pix_clk, mode->clock * 1000);
392 return MODE_CLOCK_RANGE;
397 static void ingenic_drm_crtc_atomic_begin(struct drm_crtc *crtc,
398 struct drm_atomic_state *state)
400 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
402 struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
405 if (priv->soc_info->has_osd &&
406 drm_atomic_crtc_needs_modeset(crtc_state)) {
408 * If IPU plane is enabled, enable IPU as source for the F1
409 * plane; otherwise use regular DMA.
411 if (priv->ipu_plane && priv->ipu_plane->state->fb)
412 ctrl |= JZ_LCD_OSDCTRL_IPU;
414 regmap_update_bits(priv->map, JZ_REG_LCD_OSDCTRL,
415 JZ_LCD_OSDCTRL_IPU, ctrl);
419 static void ingenic_drm_crtc_atomic_flush(struct drm_crtc *crtc,
420 struct drm_atomic_state *state)
422 struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
423 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
425 struct drm_pending_vblank_event *event = crtc_state->event;
427 if (drm_atomic_crtc_needs_modeset(crtc_state)) {
428 ingenic_drm_crtc_update_timings(priv, &crtc_state->adjusted_mode);
429 priv->update_clk_rate = true;
432 if (priv->update_clk_rate) {
433 mutex_lock(&priv->clk_mutex);
434 clk_set_rate(priv->pix_clk,
435 crtc_state->adjusted_mode.crtc_clock * 1000);
436 priv->update_clk_rate = false;
437 mutex_unlock(&priv->clk_mutex);
441 crtc_state->event = NULL;
443 spin_lock_irq(&crtc->dev->event_lock);
444 if (drm_crtc_vblank_get(crtc) == 0)
445 drm_crtc_arm_vblank_event(crtc, event);
447 drm_crtc_send_vblank_event(crtc, event);
448 spin_unlock_irq(&crtc->dev->event_lock);
452 static int ingenic_drm_plane_atomic_check(struct drm_plane *plane,
453 struct drm_atomic_state *state)
455 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state,
457 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
459 struct ingenic_drm *priv = drm_device_get_priv(plane->dev);
460 struct ingenic_drm_private_state *priv_state;
461 struct drm_crtc_state *crtc_state;
462 struct drm_crtc *crtc = new_plane_state->crtc ?: old_plane_state->crtc;
468 if (priv->soc_info->plane_f0_not_working && plane == &priv->f0)
471 crtc_state = drm_atomic_get_existing_crtc_state(state,
473 if (WARN_ON(!crtc_state))
476 priv_state = ingenic_drm_get_priv_state(priv, state);
477 if (IS_ERR(priv_state))
478 return PTR_ERR(priv_state);
480 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
481 DRM_PLANE_HELPER_NO_SCALING,
482 DRM_PLANE_HELPER_NO_SCALING,
483 priv->soc_info->has_osd,
489 * If OSD is not available, check that the width/height match.
490 * Note that state->src_* are in 16.16 fixed-point format.
492 if (!priv->soc_info->has_osd &&
493 (new_plane_state->src_x != 0 ||
494 (new_plane_state->src_w >> 16) != new_plane_state->crtc_w ||
495 (new_plane_state->src_h >> 16) != new_plane_state->crtc_h))
498 priv_state->use_palette = new_plane_state->fb &&
499 new_plane_state->fb->format->format == DRM_FORMAT_C8;
502 * Require full modeset if enabling or disabling a plane, or changing
503 * its position, size or depth.
505 if (priv->soc_info->has_osd &&
506 (!old_plane_state->fb || !new_plane_state->fb ||
507 old_plane_state->crtc_x != new_plane_state->crtc_x ||
508 old_plane_state->crtc_y != new_plane_state->crtc_y ||
509 old_plane_state->crtc_w != new_plane_state->crtc_w ||
510 old_plane_state->crtc_h != new_plane_state->crtc_h ||
511 old_plane_state->fb->format->format != new_plane_state->fb->format->format))
512 crtc_state->mode_changed = true;
514 if (priv->soc_info->map_noncoherent)
515 drm_atomic_helper_check_plane_damage(state, new_plane_state);
520 static void ingenic_drm_plane_enable(struct ingenic_drm *priv,
521 struct drm_plane *plane)
525 if (priv->soc_info->has_osd) {
526 if (plane != &priv->f0)
527 en_bit = JZ_LCD_OSDC_F1EN;
529 en_bit = JZ_LCD_OSDC_F0EN;
531 regmap_set_bits(priv->map, JZ_REG_LCD_OSDC, en_bit);
535 void ingenic_drm_plane_disable(struct device *dev, struct drm_plane *plane)
537 struct ingenic_drm *priv = dev_get_drvdata(dev);
540 if (priv->soc_info->has_osd) {
541 if (plane != &priv->f0)
542 en_bit = JZ_LCD_OSDC_F1EN;
544 en_bit = JZ_LCD_OSDC_F0EN;
546 regmap_clear_bits(priv->map, JZ_REG_LCD_OSDC, en_bit);
550 static void ingenic_drm_plane_atomic_disable(struct drm_plane *plane,
551 struct drm_atomic_state *state)
553 struct ingenic_drm *priv = drm_device_get_priv(plane->dev);
555 ingenic_drm_plane_disable(priv->dev, plane);
558 void ingenic_drm_plane_config(struct device *dev,
559 struct drm_plane *plane, u32 fourcc)
561 struct ingenic_drm *priv = dev_get_drvdata(dev);
562 struct drm_plane_state *state = plane->state;
563 unsigned int xy_reg, size_reg;
564 unsigned int ctrl = 0;
566 ingenic_drm_plane_enable(priv, plane);
568 if (priv->soc_info->has_osd && plane != &priv->f0) {
570 case DRM_FORMAT_XRGB1555:
571 ctrl |= JZ_LCD_OSDCTRL_RGB555;
573 case DRM_FORMAT_RGB565:
574 ctrl |= JZ_LCD_OSDCTRL_BPP_15_16;
576 case DRM_FORMAT_RGB888:
577 ctrl |= JZ_LCD_OSDCTRL_BPP_24_COMP;
579 case DRM_FORMAT_XRGB8888:
580 ctrl |= JZ_LCD_OSDCTRL_BPP_18_24;
582 case DRM_FORMAT_XRGB2101010:
583 ctrl |= JZ_LCD_OSDCTRL_BPP_30;
587 regmap_update_bits(priv->map, JZ_REG_LCD_OSDCTRL,
588 JZ_LCD_OSDCTRL_BPP_MASK, ctrl);
592 ctrl |= JZ_LCD_CTRL_BPP_8;
594 case DRM_FORMAT_XRGB1555:
595 ctrl |= JZ_LCD_CTRL_RGB555;
597 case DRM_FORMAT_RGB565:
598 ctrl |= JZ_LCD_CTRL_BPP_15_16;
600 case DRM_FORMAT_RGB888:
601 ctrl |= JZ_LCD_CTRL_BPP_24_COMP;
603 case DRM_FORMAT_XRGB8888:
604 ctrl |= JZ_LCD_CTRL_BPP_18_24;
606 case DRM_FORMAT_XRGB2101010:
607 ctrl |= JZ_LCD_CTRL_BPP_30;
611 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
612 JZ_LCD_CTRL_BPP_MASK, ctrl);
615 if (priv->soc_info->has_osd) {
616 if (plane != &priv->f0) {
617 xy_reg = JZ_REG_LCD_XYP1;
618 size_reg = JZ_REG_LCD_SIZE1;
620 xy_reg = JZ_REG_LCD_XYP0;
621 size_reg = JZ_REG_LCD_SIZE0;
624 regmap_write(priv->map, xy_reg,
625 state->crtc_x << JZ_LCD_XYP01_XPOS_LSB |
626 state->crtc_y << JZ_LCD_XYP01_YPOS_LSB);
627 regmap_write(priv->map, size_reg,
628 state->crtc_w << JZ_LCD_SIZE01_WIDTH_LSB |
629 state->crtc_h << JZ_LCD_SIZE01_HEIGHT_LSB);
633 bool ingenic_drm_map_noncoherent(const struct device *dev)
635 const struct ingenic_drm *priv = dev_get_drvdata(dev);
637 return priv->soc_info->map_noncoherent;
640 static void ingenic_drm_update_palette(struct ingenic_drm *priv,
641 const struct drm_color_lut *lut)
645 for (i = 0; i < ARRAY_SIZE(priv->dma_hwdescs->palette); i++) {
646 u16 color = drm_color_lut_extract(lut[i].red, 5) << 11
647 | drm_color_lut_extract(lut[i].green, 6) << 5
648 | drm_color_lut_extract(lut[i].blue, 5);
650 priv->dma_hwdescs->palette[i] = color;
654 static void ingenic_drm_plane_atomic_update(struct drm_plane *plane,
655 struct drm_atomic_state *state)
657 struct ingenic_drm *priv = drm_device_get_priv(plane->dev);
658 struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state, plane);
659 struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state, plane);
660 unsigned int width, height, cpp, next_id, plane_id;
661 struct ingenic_drm_private_state *priv_state;
662 struct drm_crtc_state *crtc_state;
663 struct ingenic_dma_hwdesc *hwdesc;
667 if (newstate && newstate->fb) {
668 if (priv->soc_info->map_noncoherent)
669 drm_fb_cma_sync_non_coherent(&priv->drm, oldstate, newstate);
671 crtc_state = newstate->crtc->state;
672 plane_id = !!(priv->soc_info->has_osd && plane != &priv->f0);
674 addr = drm_fb_cma_get_gem_addr(newstate->fb, newstate, 0);
675 width = newstate->src_w >> 16;
676 height = newstate->src_h >> 16;
677 cpp = newstate->fb->format->cpp[0];
679 priv_state = ingenic_drm_get_new_priv_state(priv, state);
680 next_id = (priv_state && priv_state->use_palette) ? HWDESC_PALETTE : plane_id;
682 hwdesc = &priv->dma_hwdescs->hwdesc[plane_id];
684 hwdesc->cmd = JZ_LCD_CMD_EOF_IRQ | (width * height * cpp / 4);
685 hwdesc->next = dma_hwdesc_addr(priv, next_id);
687 if (priv->soc_info->use_extended_hwdesc) {
688 hwdesc->cmd |= JZ_LCD_CMD_FRM_ENABLE;
690 /* Extended 8-byte descriptor */
693 hwdesc->pagewidth = 0;
695 switch (newstate->fb->format->format) {
696 case DRM_FORMAT_XRGB1555:
697 hwdesc->cpos |= JZ_LCD_CPOS_RGB555;
699 case DRM_FORMAT_RGB565:
700 hwdesc->cpos |= JZ_LCD_CPOS_BPP_15_16;
702 case DRM_FORMAT_XRGB8888:
703 hwdesc->cpos |= JZ_LCD_CPOS_BPP_18_24;
706 hwdesc->cpos |= (JZ_LCD_CPOS_COEFFICIENT_1 <<
707 JZ_LCD_CPOS_COEFFICIENT_OFFSET);
709 (0xff << JZ_LCD_DESSIZE_ALPHA_OFFSET) |
710 FIELD_PREP(JZ_LCD_DESSIZE_HEIGHT_MASK, height - 1) |
711 FIELD_PREP(JZ_LCD_DESSIZE_WIDTH_MASK, width - 1);
714 if (drm_atomic_crtc_needs_modeset(crtc_state)) {
715 fourcc = newstate->fb->format->format;
717 ingenic_drm_plane_config(priv->dev, plane, fourcc);
719 crtc_state->color_mgmt_changed = fourcc == DRM_FORMAT_C8;
722 if (crtc_state->color_mgmt_changed)
723 ingenic_drm_update_palette(priv, crtc_state->gamma_lut->data);
727 static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder,
728 struct drm_crtc_state *crtc_state,
729 struct drm_connector_state *conn_state)
731 struct ingenic_drm *priv = drm_device_get_priv(encoder->dev);
732 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
733 struct ingenic_drm_bridge *bridge = to_ingenic_drm_bridge(encoder);
734 unsigned int cfg, rgbcfg = 0;
736 priv->panel_is_sharp = bridge->bus_cfg.flags & DRM_BUS_FLAG_SHARP_SIGNALS;
738 if (priv->panel_is_sharp) {
739 cfg = JZ_LCD_CFG_MODE_SPECIAL_TFT_1 | JZ_LCD_CFG_REV_POLARITY;
741 cfg = JZ_LCD_CFG_PS_DISABLE | JZ_LCD_CFG_CLS_DISABLE
742 | JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE;
745 if (priv->soc_info->use_extended_hwdesc)
746 cfg |= JZ_LCD_CFG_DESCRIPTOR_8;
748 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
749 cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW;
750 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
751 cfg |= JZ_LCD_CFG_VSYNC_ACTIVE_LOW;
752 if (bridge->bus_cfg.flags & DRM_BUS_FLAG_DE_LOW)
753 cfg |= JZ_LCD_CFG_DE_ACTIVE_LOW;
754 if (bridge->bus_cfg.flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
755 cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE;
757 if (!priv->panel_is_sharp) {
758 if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_TV) {
759 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
760 cfg |= JZ_LCD_CFG_MODE_TV_OUT_I;
762 cfg |= JZ_LCD_CFG_MODE_TV_OUT_P;
764 switch (bridge->bus_cfg.format) {
765 case MEDIA_BUS_FMT_RGB565_1X16:
766 cfg |= JZ_LCD_CFG_MODE_GENERIC_16BIT;
768 case MEDIA_BUS_FMT_RGB666_1X18:
769 cfg |= JZ_LCD_CFG_MODE_GENERIC_18BIT;
771 case MEDIA_BUS_FMT_RGB888_1X24:
772 cfg |= JZ_LCD_CFG_MODE_GENERIC_24BIT;
774 case MEDIA_BUS_FMT_RGB888_3X8_DELTA:
775 rgbcfg = JZ_LCD_RGBC_EVEN_GBR | JZ_LCD_RGBC_ODD_RGB;
777 case MEDIA_BUS_FMT_RGB888_3X8:
778 cfg |= JZ_LCD_CFG_MODE_8BIT_SERIAL;
786 regmap_write(priv->map, JZ_REG_LCD_CFG, cfg);
787 regmap_write(priv->map, JZ_REG_LCD_RGBC, rgbcfg);
790 static int ingenic_drm_bridge_attach(struct drm_bridge *bridge,
791 enum drm_bridge_attach_flags flags)
793 struct ingenic_drm_bridge *ib = to_ingenic_drm_bridge(bridge->encoder);
795 return drm_bridge_attach(bridge->encoder, ib->next_bridge,
799 static int ingenic_drm_bridge_atomic_check(struct drm_bridge *bridge,
800 struct drm_bridge_state *bridge_state,
801 struct drm_crtc_state *crtc_state,
802 struct drm_connector_state *conn_state)
804 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
805 struct ingenic_drm_bridge *ib = to_ingenic_drm_bridge(bridge->encoder);
807 ib->bus_cfg = bridge_state->output_bus_cfg;
809 if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_TV)
812 switch (bridge_state->output_bus_cfg.format) {
813 case MEDIA_BUS_FMT_RGB888_3X8:
814 case MEDIA_BUS_FMT_RGB888_3X8_DELTA:
816 * The LCD controller expects timing values in dot-clock ticks,
817 * which is 3x the timing values in pixels when using a 3x8-bit
818 * display; but it will count the display area size in pixels
819 * either way. Go figure.
821 mode->crtc_clock = mode->clock * 3;
822 mode->crtc_hsync_start = mode->hsync_start * 3 - mode->hdisplay * 2;
823 mode->crtc_hsync_end = mode->hsync_end * 3 - mode->hdisplay * 2;
824 mode->crtc_hdisplay = mode->hdisplay;
825 mode->crtc_htotal = mode->htotal * 3 - mode->hdisplay * 2;
827 case MEDIA_BUS_FMT_RGB565_1X16:
828 case MEDIA_BUS_FMT_RGB666_1X18:
829 case MEDIA_BUS_FMT_RGB888_1X24:
837 ingenic_drm_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
838 struct drm_bridge_state *bridge_state,
839 struct drm_crtc_state *crtc_state,
840 struct drm_connector_state *conn_state,
842 unsigned int *num_input_fmts)
844 switch (output_fmt) {
845 case MEDIA_BUS_FMT_RGB888_1X24:
846 case MEDIA_BUS_FMT_RGB666_1X18:
847 case MEDIA_BUS_FMT_RGB565_1X16:
848 case MEDIA_BUS_FMT_RGB888_3X8:
849 case MEDIA_BUS_FMT_RGB888_3X8_DELTA:
856 return drm_atomic_helper_bridge_propagate_bus_fmt(bridge, bridge_state,
857 crtc_state, conn_state,
862 static irqreturn_t ingenic_drm_irq_handler(int irq, void *arg)
864 struct ingenic_drm *priv = drm_device_get_priv(arg);
867 regmap_read(priv->map, JZ_REG_LCD_STATE, &state);
869 regmap_update_bits(priv->map, JZ_REG_LCD_STATE,
870 JZ_LCD_STATE_EOF_IRQ, 0);
872 if (state & JZ_LCD_STATE_EOF_IRQ)
873 drm_crtc_handle_vblank(&priv->crtc);
878 static int ingenic_drm_enable_vblank(struct drm_crtc *crtc)
880 struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
885 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
886 JZ_LCD_CTRL_EOF_IRQ, JZ_LCD_CTRL_EOF_IRQ);
891 static void ingenic_drm_disable_vblank(struct drm_crtc *crtc)
893 struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
895 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, JZ_LCD_CTRL_EOF_IRQ, 0);
898 static struct drm_framebuffer *
899 ingenic_drm_gem_fb_create(struct drm_device *drm, struct drm_file *file,
900 const struct drm_mode_fb_cmd2 *mode_cmd)
902 struct ingenic_drm *priv = drm_device_get_priv(drm);
904 if (priv->soc_info->map_noncoherent)
905 return drm_gem_fb_create_with_dirty(drm, file, mode_cmd);
907 return drm_gem_fb_create(drm, file, mode_cmd);
910 static struct drm_gem_object *
911 ingenic_drm_gem_create_object(struct drm_device *drm, size_t size)
913 struct ingenic_drm *priv = drm_device_get_priv(drm);
914 struct drm_gem_cma_object *obj;
916 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
918 return ERR_PTR(-ENOMEM);
920 obj->map_noncoherent = priv->soc_info->map_noncoherent;
925 static struct drm_private_state *
926 ingenic_drm_duplicate_state(struct drm_private_obj *obj)
928 struct ingenic_drm_private_state *state = to_ingenic_drm_priv_state(obj->state);
930 state = kmemdup(state, sizeof(*state), GFP_KERNEL);
934 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
939 static void ingenic_drm_destroy_state(struct drm_private_obj *obj,
940 struct drm_private_state *state)
942 struct ingenic_drm_private_state *priv_state = to_ingenic_drm_priv_state(state);
947 DEFINE_DRM_GEM_CMA_FOPS(ingenic_drm_fops);
949 static const struct drm_driver ingenic_drm_driver_data = {
950 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
951 .name = "ingenic-drm",
952 .desc = "DRM module for Ingenic SoCs",
958 .fops = &ingenic_drm_fops,
959 .gem_create_object = ingenic_drm_gem_create_object,
960 DRM_GEM_CMA_DRIVER_OPS,
963 static const struct drm_plane_funcs ingenic_drm_primary_plane_funcs = {
964 .update_plane = drm_atomic_helper_update_plane,
965 .disable_plane = drm_atomic_helper_disable_plane,
966 .reset = drm_atomic_helper_plane_reset,
967 .destroy = drm_plane_cleanup,
969 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
970 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
973 static const struct drm_crtc_funcs ingenic_drm_crtc_funcs = {
974 .set_config = drm_atomic_helper_set_config,
975 .page_flip = drm_atomic_helper_page_flip,
976 .reset = drm_atomic_helper_crtc_reset,
977 .destroy = drm_crtc_cleanup,
979 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
980 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
982 .enable_vblank = ingenic_drm_enable_vblank,
983 .disable_vblank = ingenic_drm_disable_vblank,
986 static const struct drm_plane_helper_funcs ingenic_drm_plane_helper_funcs = {
987 .atomic_update = ingenic_drm_plane_atomic_update,
988 .atomic_check = ingenic_drm_plane_atomic_check,
989 .atomic_disable = ingenic_drm_plane_atomic_disable,
992 static const struct drm_crtc_helper_funcs ingenic_drm_crtc_helper_funcs = {
993 .atomic_enable = ingenic_drm_crtc_atomic_enable,
994 .atomic_disable = ingenic_drm_crtc_atomic_disable,
995 .atomic_begin = ingenic_drm_crtc_atomic_begin,
996 .atomic_flush = ingenic_drm_crtc_atomic_flush,
997 .atomic_check = ingenic_drm_crtc_atomic_check,
998 .mode_valid = ingenic_drm_crtc_mode_valid,
1001 static const struct drm_encoder_helper_funcs ingenic_drm_encoder_helper_funcs = {
1002 .atomic_mode_set = ingenic_drm_encoder_atomic_mode_set,
1005 static const struct drm_bridge_funcs ingenic_drm_bridge_funcs = {
1006 .attach = ingenic_drm_bridge_attach,
1007 .atomic_enable = ingenic_drm_bridge_atomic_enable,
1008 .atomic_disable = ingenic_drm_bridge_atomic_disable,
1009 .atomic_check = ingenic_drm_bridge_atomic_check,
1010 .atomic_reset = drm_atomic_helper_bridge_reset,
1011 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1012 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1013 .atomic_get_input_bus_fmts = ingenic_drm_bridge_atomic_get_input_bus_fmts,
1016 static const struct drm_mode_config_funcs ingenic_drm_mode_config_funcs = {
1017 .fb_create = ingenic_drm_gem_fb_create,
1018 .output_poll_changed = drm_fb_helper_output_poll_changed,
1019 .atomic_check = drm_atomic_helper_check,
1020 .atomic_commit = drm_atomic_helper_commit,
1023 static struct drm_mode_config_helper_funcs ingenic_drm_mode_config_helpers = {
1024 .atomic_commit_tail = drm_atomic_helper_commit_tail,
1027 static const struct drm_private_state_funcs ingenic_drm_private_state_funcs = {
1028 .atomic_duplicate_state = ingenic_drm_duplicate_state,
1029 .atomic_destroy_state = ingenic_drm_destroy_state,
1032 static void ingenic_drm_unbind_all(void *d)
1034 struct ingenic_drm *priv = d;
1036 component_unbind_all(priv->dev, &priv->drm);
1039 static void __maybe_unused ingenic_drm_release_rmem(void *d)
1041 of_reserved_mem_device_release(d);
1044 static void ingenic_drm_configure_hwdesc(struct ingenic_drm *priv,
1045 unsigned int hwdesc,
1046 unsigned int next_hwdesc, u32 id)
1048 struct ingenic_dma_hwdesc *desc = &priv->dma_hwdescs->hwdesc[hwdesc];
1050 desc->next = dma_hwdesc_addr(priv, next_hwdesc);
1054 static void ingenic_drm_configure_hwdesc_palette(struct ingenic_drm *priv)
1056 struct ingenic_dma_hwdesc *desc;
1058 ingenic_drm_configure_hwdesc(priv, HWDESC_PALETTE, 0, 0xc0);
1060 desc = &priv->dma_hwdescs->hwdesc[HWDESC_PALETTE];
1061 desc->addr = priv->dma_hwdescs_phys
1062 + offsetof(struct ingenic_dma_hwdescs, palette);
1063 desc->cmd = JZ_LCD_CMD_ENABLE_PAL
1064 | (sizeof(priv->dma_hwdescs->palette) / 4);
1067 static void ingenic_drm_configure_hwdesc_plane(struct ingenic_drm *priv,
1070 ingenic_drm_configure_hwdesc(priv, plane, plane, 0xf0 | plane);
1073 static void ingenic_drm_atomic_private_obj_fini(struct drm_device *drm, void *private_obj)
1075 drm_atomic_private_obj_fini(private_obj);
1078 static int ingenic_drm_bind(struct device *dev, bool has_components)
1080 struct platform_device *pdev = to_platform_device(dev);
1081 struct ingenic_drm_private_state *private_state;
1082 const struct jz_soc_info *soc_info;
1083 struct ingenic_drm *priv;
1084 struct clk *parent_clk;
1085 struct drm_plane *primary;
1086 struct drm_bridge *bridge;
1087 struct drm_panel *panel;
1088 struct drm_connector *connector;
1089 struct drm_encoder *encoder;
1090 struct ingenic_drm_bridge *ib;
1091 struct drm_device *drm;
1093 struct resource *res;
1094 struct regmap_config regmap_config;
1096 unsigned int i, clone_mask = 0;
1100 soc_info = of_device_get_match_data(dev);
1102 dev_err(dev, "Missing platform data\n");
1106 if (IS_ENABLED(CONFIG_OF_RESERVED_MEM)) {
1107 ret = of_reserved_mem_device_init(dev);
1109 if (ret && ret != -ENODEV)
1110 dev_warn(dev, "Failed to get reserved memory: %d\n", ret);
1113 ret = devm_add_action_or_reset(dev, ingenic_drm_release_rmem, dev);
1119 priv = devm_drm_dev_alloc(dev, &ingenic_drm_driver_data,
1120 struct ingenic_drm, drm);
1122 return PTR_ERR(priv);
1124 priv->soc_info = soc_info;
1128 platform_set_drvdata(pdev, priv);
1130 ret = drmm_mode_config_init(drm);
1134 drm->mode_config.min_width = 0;
1135 drm->mode_config.min_height = 0;
1136 drm->mode_config.max_width = soc_info->max_width;
1137 drm->mode_config.max_height = 4095;
1138 drm->mode_config.funcs = &ingenic_drm_mode_config_funcs;
1139 drm->mode_config.helper_private = &ingenic_drm_mode_config_helpers;
1141 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1143 dev_err(dev, "Failed to get memory resource\n");
1144 return PTR_ERR(base);
1147 regmap_config = ingenic_drm_regmap_config;
1148 regmap_config.max_register = res->end - res->start;
1149 priv->map = devm_regmap_init_mmio(dev, base,
1151 if (IS_ERR(priv->map)) {
1152 dev_err(dev, "Failed to create regmap\n");
1153 return PTR_ERR(priv->map);
1156 irq = platform_get_irq(pdev, 0);
1160 if (soc_info->needs_dev_clk) {
1161 priv->lcd_clk = devm_clk_get(dev, "lcd");
1162 if (IS_ERR(priv->lcd_clk)) {
1163 dev_err(dev, "Failed to get lcd clock\n");
1164 return PTR_ERR(priv->lcd_clk);
1168 priv->pix_clk = devm_clk_get(dev, "lcd_pclk");
1169 if (IS_ERR(priv->pix_clk)) {
1170 dev_err(dev, "Failed to get pixel clock\n");
1171 return PTR_ERR(priv->pix_clk);
1174 priv->dma_hwdescs = dmam_alloc_coherent(dev,
1175 sizeof(*priv->dma_hwdescs),
1176 &priv->dma_hwdescs_phys,
1178 if (!priv->dma_hwdescs)
1181 /* Configure DMA hwdesc for foreground0 plane */
1182 ingenic_drm_configure_hwdesc_plane(priv, 0);
1184 /* Configure DMA hwdesc for foreground1 plane */
1185 ingenic_drm_configure_hwdesc_plane(priv, 1);
1187 /* Configure DMA hwdesc for palette */
1188 ingenic_drm_configure_hwdesc_palette(priv);
1190 primary = priv->soc_info->has_osd ? &priv->f1 : &priv->f0;
1192 drm_plane_helper_add(primary, &ingenic_drm_plane_helper_funcs);
1194 ret = drm_universal_plane_init(drm, primary, 1,
1195 &ingenic_drm_primary_plane_funcs,
1196 priv->soc_info->formats_f1,
1197 priv->soc_info->num_formats_f1,
1198 NULL, DRM_PLANE_TYPE_PRIMARY, NULL);
1200 dev_err(dev, "Failed to register plane: %i\n", ret);
1204 if (soc_info->map_noncoherent)
1205 drm_plane_enable_fb_damage_clips(&priv->f1);
1207 drm_crtc_helper_add(&priv->crtc, &ingenic_drm_crtc_helper_funcs);
1209 ret = drm_crtc_init_with_planes(drm, &priv->crtc, primary,
1210 NULL, &ingenic_drm_crtc_funcs, NULL);
1212 dev_err(dev, "Failed to init CRTC: %i\n", ret);
1216 drm_crtc_enable_color_mgmt(&priv->crtc, 0, false,
1217 ARRAY_SIZE(priv->dma_hwdescs->palette));
1219 if (soc_info->has_osd) {
1220 drm_plane_helper_add(&priv->f0,
1221 &ingenic_drm_plane_helper_funcs);
1223 ret = drm_universal_plane_init(drm, &priv->f0, 1,
1224 &ingenic_drm_primary_plane_funcs,
1225 priv->soc_info->formats_f0,
1226 priv->soc_info->num_formats_f0,
1227 NULL, DRM_PLANE_TYPE_OVERLAY,
1230 dev_err(dev, "Failed to register overlay plane: %i\n",
1235 if (soc_info->map_noncoherent)
1236 drm_plane_enable_fb_damage_clips(&priv->f0);
1238 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && has_components) {
1239 ret = component_bind_all(dev, drm);
1241 if (ret != -EPROBE_DEFER)
1242 dev_err(dev, "Failed to bind components: %i\n", ret);
1246 ret = devm_add_action_or_reset(dev, ingenic_drm_unbind_all, priv);
1250 priv->ipu_plane = drm_plane_from_index(drm, 2);
1251 if (!priv->ipu_plane) {
1252 dev_err(dev, "Failed to retrieve IPU plane\n");
1258 for (i = 0; ; i++) {
1259 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, i, &panel, &bridge);
1262 break; /* we're done */
1263 if (ret != -EPROBE_DEFER)
1264 dev_err(dev, "Failed to get bridge handle\n");
1269 bridge = devm_drm_panel_bridge_add_typed(dev, panel,
1270 DRM_MODE_CONNECTOR_DPI);
1272 ib = drmm_encoder_alloc(drm, struct ingenic_drm_bridge, encoder,
1273 NULL, DRM_MODE_ENCODER_DPI, NULL);
1276 dev_err(dev, "Failed to init encoder: %d\n", ret);
1280 encoder = &ib->encoder;
1281 encoder->possible_crtcs = drm_crtc_mask(&priv->crtc);
1283 drm_encoder_helper_add(encoder, &ingenic_drm_encoder_helper_funcs);
1285 ib->bridge.funcs = &ingenic_drm_bridge_funcs;
1286 ib->next_bridge = bridge;
1288 ret = drm_bridge_attach(encoder, &ib->bridge, NULL,
1289 DRM_BRIDGE_ATTACH_NO_CONNECTOR);
1291 dev_err(dev, "Unable to attach bridge\n");
1295 connector = drm_bridge_connector_init(drm, encoder);
1296 if (IS_ERR(connector)) {
1297 dev_err(dev, "Unable to init connector\n");
1298 return PTR_ERR(connector);
1301 drm_connector_attach_encoder(connector, encoder);
1304 drm_for_each_encoder(encoder, drm) {
1305 clone_mask |= BIT(drm_encoder_index(encoder));
1308 drm_for_each_encoder(encoder, drm) {
1309 encoder->possible_clones = clone_mask;
1312 ret = devm_request_irq(dev, irq, ingenic_drm_irq_handler, 0, drm->driver->name, drm);
1314 dev_err(dev, "Unable to install IRQ handler\n");
1318 ret = drm_vblank_init(drm, 1);
1320 dev_err(dev, "Failed calling drm_vblank_init()\n");
1324 drm_mode_config_reset(drm);
1326 ret = clk_prepare_enable(priv->pix_clk);
1328 dev_err(dev, "Unable to start pixel clock\n");
1332 if (priv->lcd_clk) {
1333 parent_clk = clk_get_parent(priv->lcd_clk);
1334 parent_rate = clk_get_rate(parent_clk);
1336 /* LCD Device clock must be 3x the pixel clock for STN panels,
1337 * or 1.5x the pixel clock for TFT panels. To avoid having to
1338 * check for the LCD device clock everytime we do a mode change,
1339 * we set the LCD device clock to the highest rate possible.
1341 ret = clk_set_rate(priv->lcd_clk, parent_rate);
1343 dev_err(dev, "Unable to set LCD clock rate\n");
1344 goto err_pixclk_disable;
1347 ret = clk_prepare_enable(priv->lcd_clk);
1349 dev_err(dev, "Unable to start lcd clock\n");
1350 goto err_pixclk_disable;
1354 /* Enable OSD if available */
1355 if (soc_info->has_osd)
1356 osdc |= JZ_LCD_OSDC_OSDEN;
1357 if (soc_info->has_alpha)
1358 osdc |= JZ_LCD_OSDC_ALPHAEN;
1359 regmap_write(priv->map, JZ_REG_LCD_OSDC, osdc);
1361 mutex_init(&priv->clk_mutex);
1362 priv->clock_nb.notifier_call = ingenic_drm_update_pixclk;
1364 parent_clk = clk_get_parent(priv->pix_clk);
1365 ret = clk_notifier_register(parent_clk, &priv->clock_nb);
1367 dev_err(dev, "Unable to register clock notifier\n");
1368 goto err_devclk_disable;
1371 private_state = kzalloc(sizeof(*private_state), GFP_KERNEL);
1372 if (!private_state) {
1374 goto err_clk_notifier_unregister;
1377 drm_atomic_private_obj_init(drm, &priv->private_obj, &private_state->base,
1378 &ingenic_drm_private_state_funcs);
1380 ret = drmm_add_action_or_reset(drm, ingenic_drm_atomic_private_obj_fini,
1381 &priv->private_obj);
1383 goto err_private_state_free;
1385 ret = drm_dev_register(drm, 0);
1387 dev_err(dev, "Failed to register DRM driver\n");
1388 goto err_clk_notifier_unregister;
1391 drm_fbdev_generic_setup(drm, 32);
1395 err_private_state_free:
1396 kfree(private_state);
1397 err_clk_notifier_unregister:
1398 clk_notifier_unregister(parent_clk, &priv->clock_nb);
1401 clk_disable_unprepare(priv->lcd_clk);
1403 clk_disable_unprepare(priv->pix_clk);
1407 static int ingenic_drm_bind_with_components(struct device *dev)
1409 return ingenic_drm_bind(dev, true);
1412 static void ingenic_drm_unbind(struct device *dev)
1414 struct ingenic_drm *priv = dev_get_drvdata(dev);
1415 struct clk *parent_clk = clk_get_parent(priv->pix_clk);
1417 clk_notifier_unregister(parent_clk, &priv->clock_nb);
1419 clk_disable_unprepare(priv->lcd_clk);
1420 clk_disable_unprepare(priv->pix_clk);
1422 drm_dev_unregister(&priv->drm);
1423 drm_atomic_helper_shutdown(&priv->drm);
1426 static const struct component_master_ops ingenic_master_ops = {
1427 .bind = ingenic_drm_bind_with_components,
1428 .unbind = ingenic_drm_unbind,
1431 static int ingenic_drm_probe(struct platform_device *pdev)
1433 struct device *dev = &pdev->dev;
1434 struct component_match *match = NULL;
1435 struct device_node *np;
1437 if (!IS_ENABLED(CONFIG_DRM_INGENIC_IPU))
1438 return ingenic_drm_bind(dev, false);
1440 /* IPU is at port address 8 */
1441 np = of_graph_get_remote_node(dev->of_node, 8, 0);
1443 return ingenic_drm_bind(dev, false);
1445 drm_of_component_match_add(dev, &match, component_compare_of, np);
1448 return component_master_add_with_match(dev, &ingenic_master_ops, match);
1451 static int ingenic_drm_remove(struct platform_device *pdev)
1453 struct device *dev = &pdev->dev;
1455 if (!IS_ENABLED(CONFIG_DRM_INGENIC_IPU))
1456 ingenic_drm_unbind(dev);
1458 component_master_del(dev, &ingenic_master_ops);
1463 static int __maybe_unused ingenic_drm_suspend(struct device *dev)
1465 struct ingenic_drm *priv = dev_get_drvdata(dev);
1467 return drm_mode_config_helper_suspend(&priv->drm);
1470 static int __maybe_unused ingenic_drm_resume(struct device *dev)
1472 struct ingenic_drm *priv = dev_get_drvdata(dev);
1474 return drm_mode_config_helper_resume(&priv->drm);
1477 static SIMPLE_DEV_PM_OPS(ingenic_drm_pm_ops, ingenic_drm_suspend, ingenic_drm_resume);
1479 static const u32 jz4740_formats[] = {
1480 DRM_FORMAT_XRGB1555,
1482 DRM_FORMAT_XRGB8888,
1485 static const u32 jz4725b_formats_f1[] = {
1486 DRM_FORMAT_XRGB1555,
1488 DRM_FORMAT_XRGB8888,
1491 static const u32 jz4725b_formats_f0[] = {
1493 DRM_FORMAT_XRGB1555,
1495 DRM_FORMAT_XRGB8888,
1498 static const u32 jz4770_formats_f1[] = {
1499 DRM_FORMAT_XRGB1555,
1502 DRM_FORMAT_XRGB8888,
1503 DRM_FORMAT_XRGB2101010,
1506 static const u32 jz4770_formats_f0[] = {
1508 DRM_FORMAT_XRGB1555,
1511 DRM_FORMAT_XRGB8888,
1512 DRM_FORMAT_XRGB2101010,
1515 static const struct jz_soc_info jz4740_soc_info = {
1516 .needs_dev_clk = true,
1518 .map_noncoherent = false,
1521 .formats_f1 = jz4740_formats,
1522 .num_formats_f1 = ARRAY_SIZE(jz4740_formats),
1523 /* JZ4740 has only one plane */
1526 static const struct jz_soc_info jz4725b_soc_info = {
1527 .needs_dev_clk = false,
1529 .map_noncoherent = false,
1532 .formats_f1 = jz4725b_formats_f1,
1533 .num_formats_f1 = ARRAY_SIZE(jz4725b_formats_f1),
1534 .formats_f0 = jz4725b_formats_f0,
1535 .num_formats_f0 = ARRAY_SIZE(jz4725b_formats_f0),
1538 static const struct jz_soc_info jz4770_soc_info = {
1539 .needs_dev_clk = false,
1541 .map_noncoherent = true,
1544 .formats_f1 = jz4770_formats_f1,
1545 .num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1),
1546 .formats_f0 = jz4770_formats_f0,
1547 .num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0),
1550 static const struct jz_soc_info jz4780_soc_info = {
1551 .needs_dev_clk = true,
1554 .use_extended_hwdesc = true,
1555 .plane_f0_not_working = true, /* REVISIT */
1558 .formats_f1 = jz4770_formats_f1,
1559 .num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1),
1560 .formats_f0 = jz4770_formats_f0,
1561 .num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0),
1564 static const struct of_device_id ingenic_drm_of_match[] = {
1565 { .compatible = "ingenic,jz4740-lcd", .data = &jz4740_soc_info },
1566 { .compatible = "ingenic,jz4725b-lcd", .data = &jz4725b_soc_info },
1567 { .compatible = "ingenic,jz4770-lcd", .data = &jz4770_soc_info },
1568 { .compatible = "ingenic,jz4780-lcd", .data = &jz4780_soc_info },
1571 MODULE_DEVICE_TABLE(of, ingenic_drm_of_match);
1573 static struct platform_driver ingenic_drm_driver = {
1575 .name = "ingenic-drm",
1576 .pm = pm_ptr(&ingenic_drm_pm_ops),
1577 .of_match_table = of_match_ptr(ingenic_drm_of_match),
1579 .probe = ingenic_drm_probe,
1580 .remove = ingenic_drm_remove,
1583 static int ingenic_drm_init(void)
1587 if (drm_firmware_drivers_only())
1590 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) {
1591 err = platform_driver_register(ingenic_ipu_driver_ptr);
1596 return platform_driver_register(&ingenic_drm_driver);
1598 module_init(ingenic_drm_init);
1600 static void ingenic_drm_exit(void)
1602 platform_driver_unregister(&ingenic_drm_driver);
1604 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU))
1605 platform_driver_unregister(ingenic_ipu_driver_ptr);
1607 module_exit(ingenic_drm_exit);
1609 MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
1610 MODULE_DESCRIPTION("DRM driver for the Ingenic SoCs\n");
1611 MODULE_LICENSE("GPL v2");