2 * i.MX drm driver - Television Encoder (TVEv2)
4 * Copyright (C) 2013 Philipp Zabel, Pengutronix
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/clk.h>
17 #include <linux/clk-provider.h>
18 #include <linux/component.h>
19 #include <linux/module.h>
20 #include <linux/i2c.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/spinlock.h>
24 #include <linux/videodev2.h>
26 #include <drm/drm_atomic_helper.h>
27 #include <drm/drm_fb_helper.h>
28 #include <drm/drm_crtc_helper.h>
29 #include <video/imx-ipu-v3.h>
33 #define TVE_COM_CONF_REG 0x00
34 #define TVE_TVDAC0_CONT_REG 0x28
35 #define TVE_TVDAC1_CONT_REG 0x2c
36 #define TVE_TVDAC2_CONT_REG 0x30
37 #define TVE_CD_CONT_REG 0x34
38 #define TVE_INT_CONT_REG 0x64
39 #define TVE_STAT_REG 0x68
40 #define TVE_TST_MODE_REG 0x6c
41 #define TVE_MV_CONT_REG 0xdc
43 /* TVE_COM_CONF_REG */
44 #define TVE_SYNC_CH_2_EN BIT(22)
45 #define TVE_SYNC_CH_1_EN BIT(21)
46 #define TVE_SYNC_CH_0_EN BIT(20)
47 #define TVE_TV_OUT_MODE_MASK (0x7 << 12)
48 #define TVE_TV_OUT_DISABLE (0x0 << 12)
49 #define TVE_TV_OUT_CVBS_0 (0x1 << 12)
50 #define TVE_TV_OUT_CVBS_2 (0x2 << 12)
51 #define TVE_TV_OUT_CVBS_0_2 (0x3 << 12)
52 #define TVE_TV_OUT_SVIDEO_0_1 (0x4 << 12)
53 #define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2 (0x5 << 12)
54 #define TVE_TV_OUT_YPBPR (0x6 << 12)
55 #define TVE_TV_OUT_RGB (0x7 << 12)
56 #define TVE_TV_STAND_MASK (0xf << 8)
57 #define TVE_TV_STAND_HD_1080P30 (0xc << 8)
58 #define TVE_P2I_CONV_EN BIT(7)
59 #define TVE_INP_VIDEO_FORM BIT(6)
60 #define TVE_INP_YCBCR_422 (0x0 << 6)
61 #define TVE_INP_YCBCR_444 (0x1 << 6)
62 #define TVE_DATA_SOURCE_MASK (0x3 << 4)
63 #define TVE_DATA_SOURCE_BUS1 (0x0 << 4)
64 #define TVE_DATA_SOURCE_BUS2 (0x1 << 4)
65 #define TVE_DATA_SOURCE_EXT (0x2 << 4)
66 #define TVE_DATA_SOURCE_TESTGEN (0x3 << 4)
67 #define TVE_IPU_CLK_EN_OFS 3
68 #define TVE_IPU_CLK_EN BIT(3)
69 #define TVE_DAC_SAMP_RATE_OFS 1
70 #define TVE_DAC_SAMP_RATE_WIDTH 2
71 #define TVE_DAC_SAMP_RATE_MASK (0x3 << 1)
72 #define TVE_DAC_FULL_RATE (0x0 << 1)
73 #define TVE_DAC_DIV2_RATE (0x1 << 1)
74 #define TVE_DAC_DIV4_RATE (0x2 << 1)
77 /* TVE_TVDACx_CONT_REG */
78 #define TVE_TVDAC_GAIN_MASK (0x3f << 0)
81 #define TVE_CD_CH_2_SM_EN BIT(22)
82 #define TVE_CD_CH_1_SM_EN BIT(21)
83 #define TVE_CD_CH_0_SM_EN BIT(20)
84 #define TVE_CD_CH_2_LM_EN BIT(18)
85 #define TVE_CD_CH_1_LM_EN BIT(17)
86 #define TVE_CD_CH_0_LM_EN BIT(16)
87 #define TVE_CD_CH_2_REF_LVL BIT(10)
88 #define TVE_CD_CH_1_REF_LVL BIT(9)
89 #define TVE_CD_CH_0_REF_LVL BIT(8)
90 #define TVE_CD_EN BIT(0)
92 /* TVE_INT_CONT_REG */
93 #define TVE_FRAME_END_IEN BIT(13)
94 #define TVE_CD_MON_END_IEN BIT(2)
95 #define TVE_CD_SM_IEN BIT(1)
96 #define TVE_CD_LM_IEN BIT(0)
98 /* TVE_TST_MODE_REG */
99 #define TVE_TVDAC_TEST_MODE_MASK (0x7 << 0)
101 #define IMX_TVE_DAC_VOLTAGE 2750000
109 struct drm_connector connector;
110 struct drm_encoder encoder;
112 spinlock_t lock; /* register lock */
118 struct regmap *regmap;
119 struct regulator *dac_reg;
120 struct i2c_adapter *ddc;
122 struct clk *di_sel_clk;
123 struct clk_hw clk_hw_di;
127 static inline struct imx_tve *con_to_tve(struct drm_connector *c)
129 return container_of(c, struct imx_tve, connector);
132 static inline struct imx_tve *enc_to_tve(struct drm_encoder *e)
134 return container_of(e, struct imx_tve, encoder);
137 static void tve_lock(void *__tve)
138 __acquires(&tve->lock)
140 struct imx_tve *tve = __tve;
142 spin_lock(&tve->lock);
145 static void tve_unlock(void *__tve)
146 __releases(&tve->lock)
148 struct imx_tve *tve = __tve;
150 spin_unlock(&tve->lock);
153 static void tve_enable(struct imx_tve *tve)
157 clk_prepare_enable(tve->clk);
158 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
162 /* clear interrupt status register */
163 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
165 /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */
166 if (tve->mode == TVE_MODE_VGA)
167 regmap_write(tve->regmap, TVE_INT_CONT_REG, 0);
169 regmap_write(tve->regmap, TVE_INT_CONT_REG,
175 static void tve_disable(struct imx_tve *tve)
178 tve->enabled = false;
179 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, 0);
180 clk_disable_unprepare(tve->clk);
184 static int tve_setup_tvout(struct imx_tve *tve)
189 static int tve_setup_vga(struct imx_tve *tve)
195 /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */
196 ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG,
197 TVE_TVDAC_GAIN_MASK, 0x0a);
201 ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG,
202 TVE_TVDAC_GAIN_MASK, 0x0a);
206 ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG,
207 TVE_TVDAC_GAIN_MASK, 0x0a);
211 /* set configuration register */
212 mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM;
213 val = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444;
214 mask |= TVE_TV_STAND_MASK | TVE_P2I_CONV_EN;
215 val |= TVE_TV_STAND_HD_1080P30 | 0;
216 mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN;
217 val |= TVE_TV_OUT_RGB | TVE_SYNC_CH_0_EN;
218 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val);
222 /* set test mode (as documented) */
223 return regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
224 TVE_TVDAC_TEST_MODE_MASK, 1);
227 static int imx_tve_connector_get_modes(struct drm_connector *connector)
229 struct imx_tve *tve = con_to_tve(connector);
236 edid = drm_get_edid(connector, tve->ddc);
238 drm_mode_connector_update_edid_property(connector, edid);
239 ret = drm_add_edid_modes(connector, edid);
246 static enum drm_mode_status
247 imx_tve_connector_mode_valid(struct drm_connector *connector,
248 struct drm_display_mode *mode)
250 struct imx_tve *tve = con_to_tve(connector);
253 /* pixel clock with 2x oversampling */
254 rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000;
255 if (rate == mode->clock)
258 /* pixel clock without oversampling */
259 rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000;
260 if (rate == mode->clock)
263 dev_warn(tve->dev, "ignoring mode %dx%d\n",
264 mode->hdisplay, mode->vdisplay);
269 static struct drm_encoder *imx_tve_connector_best_encoder(
270 struct drm_connector *connector)
272 struct imx_tve *tve = con_to_tve(connector);
274 return &tve->encoder;
277 static void imx_tve_encoder_mode_set(struct drm_encoder *encoder,
278 struct drm_display_mode *orig_mode,
279 struct drm_display_mode *mode)
281 struct imx_tve *tve = enc_to_tve(encoder);
282 unsigned long rounded_rate;
289 * we should try 4k * mode->clock first,
290 * and enable 4x oversampling for lower resolutions
292 rate = 2000UL * mode->clock;
293 clk_set_rate(tve->clk, rate);
294 rounded_rate = clk_get_rate(tve->clk);
295 if (rounded_rate >= rate)
297 clk_set_rate(tve->di_clk, rounded_rate / div);
299 ret = clk_set_parent(tve->di_sel_clk, tve->di_clk);
301 dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n",
305 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
306 TVE_IPU_CLK_EN, TVE_IPU_CLK_EN);
308 if (tve->mode == TVE_MODE_VGA)
309 ret = tve_setup_vga(tve);
311 ret = tve_setup_tvout(tve);
313 dev_err(tve->dev, "failed to set configuration: %d\n", ret);
316 static void imx_tve_encoder_enable(struct drm_encoder *encoder)
318 struct imx_tve *tve = enc_to_tve(encoder);
323 static void imx_tve_encoder_disable(struct drm_encoder *encoder)
325 struct imx_tve *tve = enc_to_tve(encoder);
330 static int imx_tve_atomic_check(struct drm_encoder *encoder,
331 struct drm_crtc_state *crtc_state,
332 struct drm_connector_state *conn_state)
334 struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
335 struct imx_tve *tve = enc_to_tve(encoder);
337 imx_crtc_state->bus_format = MEDIA_BUS_FMT_GBR888_1X24;
338 imx_crtc_state->di_hsync_pin = tve->di_hsync_pin;
339 imx_crtc_state->di_vsync_pin = tve->di_vsync_pin;
344 static const struct drm_connector_funcs imx_tve_connector_funcs = {
345 .fill_modes = drm_helper_probe_single_connector_modes,
346 .destroy = imx_drm_connector_destroy,
347 .reset = drm_atomic_helper_connector_reset,
348 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
349 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
352 static const struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = {
353 .get_modes = imx_tve_connector_get_modes,
354 .best_encoder = imx_tve_connector_best_encoder,
355 .mode_valid = imx_tve_connector_mode_valid,
358 static const struct drm_encoder_funcs imx_tve_encoder_funcs = {
359 .destroy = imx_drm_encoder_destroy,
362 static const struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = {
363 .mode_set = imx_tve_encoder_mode_set,
364 .enable = imx_tve_encoder_enable,
365 .disable = imx_tve_encoder_disable,
366 .atomic_check = imx_tve_atomic_check,
369 static irqreturn_t imx_tve_irq_handler(int irq, void *data)
371 struct imx_tve *tve = data;
374 regmap_read(tve->regmap, TVE_STAT_REG, &val);
376 /* clear interrupt status register */
377 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
382 static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw,
383 unsigned long parent_rate)
385 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
389 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
393 switch (val & TVE_DAC_SAMP_RATE_MASK) {
394 case TVE_DAC_DIV4_RATE:
395 return parent_rate / 4;
396 case TVE_DAC_DIV2_RATE:
397 return parent_rate / 2;
398 case TVE_DAC_FULL_RATE:
406 static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate,
407 unsigned long *prate)
419 static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate,
420 unsigned long parent_rate)
422 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
427 div = parent_rate / rate;
429 val = TVE_DAC_DIV4_RATE;
431 val = TVE_DAC_DIV2_RATE;
433 val = TVE_DAC_FULL_RATE;
435 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
436 TVE_DAC_SAMP_RATE_MASK, val);
439 dev_err(tve->dev, "failed to set divider: %d\n", ret);
446 static struct clk_ops clk_tve_di_ops = {
447 .round_rate = clk_tve_di_round_rate,
448 .set_rate = clk_tve_di_set_rate,
449 .recalc_rate = clk_tve_di_recalc_rate,
452 static int tve_clk_init(struct imx_tve *tve, void __iomem *base)
454 const char *tve_di_parent[1];
455 struct clk_init_data init = {
457 .ops = &clk_tve_di_ops,
462 tve_di_parent[0] = __clk_get_name(tve->clk);
463 init.parent_names = (const char **)&tve_di_parent;
465 tve->clk_hw_di.init = &init;
466 tve->di_clk = clk_register(tve->dev, &tve->clk_hw_di);
467 if (IS_ERR(tve->di_clk)) {
468 dev_err(tve->dev, "failed to register TVE output clock: %ld\n",
469 PTR_ERR(tve->di_clk));
470 return PTR_ERR(tve->di_clk);
476 static int imx_tve_register(struct drm_device *drm, struct imx_tve *tve)
481 encoder_type = tve->mode == TVE_MODE_VGA ?
482 DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC;
484 ret = imx_drm_encoder_parse_of(drm, &tve->encoder, tve->dev->of_node);
488 drm_encoder_helper_add(&tve->encoder, &imx_tve_encoder_helper_funcs);
489 drm_encoder_init(drm, &tve->encoder, &imx_tve_encoder_funcs,
492 drm_connector_helper_add(&tve->connector,
493 &imx_tve_connector_helper_funcs);
494 drm_connector_init(drm, &tve->connector, &imx_tve_connector_funcs,
495 DRM_MODE_CONNECTOR_VGA);
497 drm_mode_connector_attach_encoder(&tve->connector, &tve->encoder);
502 static void imx_tve_disable_regulator(void *data)
504 struct imx_tve *tve = data;
506 regulator_disable(tve->dac_reg);
509 static bool imx_tve_readable_reg(struct device *dev, unsigned int reg)
511 return (reg % 4 == 0) && (reg <= 0xdc);
514 static struct regmap_config tve_regmap_config = {
519 .readable_reg = imx_tve_readable_reg,
522 .unlock = tve_unlock,
524 .max_register = 0xdc,
527 static const char * const imx_tve_modes[] = {
528 [TVE_MODE_TVOUT] = "tvout",
529 [TVE_MODE_VGA] = "vga",
532 static const int of_get_tve_mode(struct device_node *np)
537 ret = of_property_read_string(np, "fsl,tve-mode", &bm);
541 for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++)
542 if (!strcasecmp(bm, imx_tve_modes[i]))
548 static int imx_tve_bind(struct device *dev, struct device *master, void *data)
550 struct platform_device *pdev = to_platform_device(dev);
551 struct drm_device *drm = data;
552 struct device_node *np = dev->of_node;
553 struct device_node *ddc_node;
555 struct resource *res;
561 tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL);
566 spin_lock_init(&tve->lock);
568 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
570 tve->ddc = of_find_i2c_adapter_by_node(ddc_node);
571 of_node_put(ddc_node);
574 tve->mode = of_get_tve_mode(np);
575 if (tve->mode != TVE_MODE_VGA) {
576 dev_err(dev, "only VGA mode supported, currently\n");
580 if (tve->mode == TVE_MODE_VGA) {
581 ret = of_property_read_u32(np, "fsl,hsync-pin",
585 dev_err(dev, "failed to get hsync pin\n");
589 ret = of_property_read_u32(np, "fsl,vsync-pin",
593 dev_err(dev, "failed to get vsync pin\n");
598 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
599 base = devm_ioremap_resource(dev, res);
601 return PTR_ERR(base);
603 tve_regmap_config.lock_arg = tve;
604 tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base,
606 if (IS_ERR(tve->regmap)) {
607 dev_err(dev, "failed to init regmap: %ld\n",
608 PTR_ERR(tve->regmap));
609 return PTR_ERR(tve->regmap);
612 irq = platform_get_irq(pdev, 0);
614 dev_err(dev, "failed to get irq\n");
618 ret = devm_request_threaded_irq(dev, irq, NULL,
619 imx_tve_irq_handler, IRQF_ONESHOT,
622 dev_err(dev, "failed to request irq: %d\n", ret);
626 tve->dac_reg = devm_regulator_get(dev, "dac");
627 if (!IS_ERR(tve->dac_reg)) {
628 if (regulator_get_voltage(tve->dac_reg) != IMX_TVE_DAC_VOLTAGE)
629 dev_warn(dev, "dac voltage is not %d uV\n", IMX_TVE_DAC_VOLTAGE);
630 ret = regulator_enable(tve->dac_reg);
633 ret = devm_add_action_or_reset(dev, imx_tve_disable_regulator, tve);
638 tve->clk = devm_clk_get(dev, "tve");
639 if (IS_ERR(tve->clk)) {
640 dev_err(dev, "failed to get high speed tve clock: %ld\n",
642 return PTR_ERR(tve->clk);
645 /* this is the IPU DI clock input selector, can be parented to tve_di */
646 tve->di_sel_clk = devm_clk_get(dev, "di_sel");
647 if (IS_ERR(tve->di_sel_clk)) {
648 dev_err(dev, "failed to get ipu di mux clock: %ld\n",
649 PTR_ERR(tve->di_sel_clk));
650 return PTR_ERR(tve->di_sel_clk);
653 ret = tve_clk_init(tve, base);
657 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
659 dev_err(dev, "failed to read configuration register: %d\n",
663 if (val != 0x00100000) {
664 dev_err(dev, "configuration register default value indicates this is not a TVEv2\n");
668 /* disable cable detection for VGA mode */
669 ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);
673 ret = imx_tve_register(drm, tve);
677 dev_set_drvdata(dev, tve);
682 static const struct component_ops imx_tve_ops = {
683 .bind = imx_tve_bind,
686 static int imx_tve_probe(struct platform_device *pdev)
688 return component_add(&pdev->dev, &imx_tve_ops);
691 static int imx_tve_remove(struct platform_device *pdev)
693 component_del(&pdev->dev, &imx_tve_ops);
697 static const struct of_device_id imx_tve_dt_ids[] = {
698 { .compatible = "fsl,imx53-tve", },
701 MODULE_DEVICE_TABLE(of, imx_tve_dt_ids);
703 static struct platform_driver imx_tve_driver = {
704 .probe = imx_tve_probe,
705 .remove = imx_tve_remove,
707 .of_match_table = imx_tve_dt_ids,
712 module_platform_driver(imx_tve_driver);
714 MODULE_DESCRIPTION("i.MX Television Encoder driver");
715 MODULE_AUTHOR("Philipp Zabel, Pengutronix");
716 MODULE_LICENSE("GPL");
717 MODULE_ALIAS("platform:imx-tve");